Hello Leonardo --
Barcelona (Family 10h) has only four physical performance
counters. Thus, some other strategy such as multiplexing is
required when collecting 5 performance events during a run
on Barcelona.
As an aside, if people are using Family 15h, 15h has six
core performance counters and f
-- pj
Dr. Paul Drongowski
Consultant at AMD
AMD Boston Design Center
-Original Message-
From: Ivo Steinmann [mailto:isteinm...@bluewin.ch]
Sent: Tuesday, June 21, 2011 7:13 AM
To: perfmon2-devel@lists.sourceforge.net
Cc: Drongowski, Paul
Subject: Re: [perfmon2] AMD IBS Support
Hi Paul
Thx for y
Hello Ivo --
Yep, you will need to use the AMD IBS feature.
Sampling the performance monitoring counters (PMCs) is imprecise.
When a PMC (overflow) generates an interrupt, the processing pipeline is most
probably far beyond the actual instruction which caused the PMC (overflow)
that triggers the
Hello Besar --
The Opteron 2378 is a third generation Opteron ("Shanghai").
As such, it will support IBS including the dispatch op sampling
mode for IBS op sampling. This is the preferred IBS op mode since
it produces a regular distribution of op samples and the distribution
reflects the execution
flects the execution
frequency of the basic block.
This may be a case of TMI, but it should help your
interpretation of the data when you see it.
Take care -- pj
-Original Message-
From: Ramachandra CN [mailto:cn.ramachan...@gmail.com]
Sent: Wednesday, March 17, 2010 7:12 PM
To: Drongowsk
Hello Ram --
Instruction-Based Sampling (BS) is supported on AMD Family 10h
processors (both Phenom(tm) and Opteron(tm)).
An AMD Opteron 180 is a so-called "K8" processor and
pre-dates AMD Family 10h. So, The AMD Opteron 180's do
not support IBS, I'm sorry to say.
The AMD Opteron 2354 is a Famil
Good catch!
Historically, AMD has treated the bit field EventSelect<7:5>
in model specific register MSRC001_00[03:00] Performance Event
Select Register (PERF_CTL[3:0]) like an "event group selector".
Please see the "BIOS and Kernel Developer's Guide for AMD
Family 10h Processors."
Typically, Even
Hello Sergey --
Just to add a few comments to Stephane's.
Northbridge resources are shared across all cores
in the "node" (the cores that are local to the
Northbridge and communicate directly with the NB).
Northbridge events measure memory controller events,
crossbar events, HyperTransport(tm) ev
I think we're referring to the same kernel feature:
http://people.redhat.com/mingo/perfcounters/
http://lwn.net/Articles/315944/
-- pj
-Original Message-
From: Godmar Back [mailto:god...@gmail.com]
Sent: Monday, September 14, 2009 5:29 PM
To: Drongowski, Paul
Cc: per
ember 14, 2009 3:51 PM
To: Drongowski, Paul
Cc: perfmon2-devel@lists.sourceforge.net
Subject: Re: [perfmon2] questions about perfmon2
On Mon, Sep 14, 2009 at 10:03 AM, Drongowski, Paul
wrote:
> Hello Godmar --
>
> WRT Q6: AMD CodeAnalyst Performance Analyzer (tm) uses OProfile
> for data collect
Hello Godmar --
WRT Q6: AMD CodeAnalyst Performance Analyzer (tm) uses OProfile
for data collection on Linux. We also make the source code for
CodeAnalyst available.
As a team, we look to the Linux/open source community for
OS-level profiling support. Robert Richter from AMD has
contributed pe
Hi --
I'm sorry to be joining this discussion so late. A few of my
colleagues pointed me toward the current thread on IBS and I've tried
to catch up by reading the archives. A short self-introduction: I'm a
member of the AMD CodeAnalyst team, Ravi Bhargava and I wrote Appendix G
(concerning IBS)
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