[PEDA] A little OT - PCB labelling

Hello all, What methods of labelling would you recommend for unique identification of PCBs. We have been using thermal printed labels for serial numbers etc, but these are destroyed if a board is reworked. The boards have an area for hand writing serial numbers, but this is removed when solvent

Re: [PEDA] Re[2]: six or eight-layer (or more?) stackups - Capacitance

On 07:14 PM 4/06/2003, John Sheahan said: On Wed, Jun 04, 2003 at 09:34:18AM +0200, Norbert Hoppe wrote: When selecting parallel caps, it is important to remember that as the larger value capacitor goes inductive, the smaller value cap is still capacitive. At a particular frequency, a LC

Re: [PEDA] six or eight-layer (or more?) stackups - Capacitance

common in today's circuits. Also, 0.01 uF caps are less expensive and take up less space (0805 vs. 1206). Huh? Why would you use a 1206 0.1uf for anything unless you needed 50WVDC or more rating? Everything I have read on bypassing for digital says to use 0603 or smaller parts since they

Re: [PEDA] Re[2]: six or eight-layer (or more?) stackups - Capacitance

Ian: Thanks for the refresher lesson in how real world parts you can actually get your hands on perform as opposed to theoretically, a smaller case size will always perform better. Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com - Original Message - From: Ian

Re: [PEDA] eight-layer stackup

Julian, Please see below. JaMi - Original Message - From: Julian Higginson [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Tuesday, June 03, 2003 1:28 AM Subject: Re: [PEDA] eight-layer stackup From: JaMi Smith [mailto:[EMAIL PROTECTED] While there may be some

Re: [PEDA] Re[2]: six or eight-layer (or more?) stackups - Capacitance

On Wed, Jun 04, 2003 at 09:37:19PM +1000, Ian Wilson wrote: Thanks for the well reasoned response Ian. I went through this a few months ago, but needed 0402 package (was a dense board) and a similar line of research showed 100n was the best choice there. But it depends on the particular caps

Re: [PEDA] eight-layer stackup

you just use a via and short track in the component footprint design and then run update free primitives (yes i know they are not 'free') it works no drc probs am i on the same page as this discussion or maybe i have missed something? ds JaMi Smith wrote: Julian, Please see below.

Re: [PEDA] Re[2]: six or eight-layer (or more?) stackups - Capacitance

On 08:28 AM 5/06/2003, John Sheahan said: snip.. Value Size Impedance 103 0603~1 ohm 103 0805~0.5 ohm 103 1206~0.3 ohm 104 0805~1 ohm 104 1206~1 ohm So if you spec a 10nF 0603 you have a resistor, not a decoupler, at 100 MHz. probably only a

[PEDA] Invisible power plane blowouts

Can anyone offer any suggestions on what I've broken? Up until about 20 minutes ago, whenever I had the power planes (COM and 5V/3.3V split) displayed I could see the blowouts around the pads and vias that did not connect to these planes. I wrote a design rule to allow direct connection of vias

Re: [PEDA] Re[2]: six or eight-layer (or more?) stackups - Capacitance

On Thu, Jun 05, 2003 at 10:29:29AM +1000, Ian Wilson wrote: about is minimising the AC impedance between the power nets over a suitably broad range of frequencies and to an adequately low level - both application dependent. Operating past resonance simply means the impedance is inductive

Re: [PEDA] eight-layer stackup

Michael, http://www.hottconsultants.com/tips.html provides some usefull information about layer stack up. Best regards, Ben Uijtenhaak * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: *