On Thu, Jun 05, 2003 at 10:29:29AM +1000, Ian Wilson wrote:

> about is minimising the AC impedance between the power nets over a suitably 
> broad range of frequencies and to an adequately low level - both 
> application dependent.  Operating past resonance simply means the impedance 
> is inductive and rising with freq - so what, as long as it is low enough, 
> that is generally all you need to know.

yes - just as long as we are not getting too near the parallel resonance. A Q
issue as you point out.

> may have problems in production.  I can imagine what the production team 
> would think about trimmable decoupling caps. :-)

select on test decouplers I have yet to resort to fortunately :)

> 
> 1nF of *high-Q* interplane capacitance!  Not likely, even if the parallel 

sorry if I was unclear. I did not mean to suggest the board planes 
were this good.
100p ~ 1N NPO may win in a brief band somewhere between 100M and 1G.
The plane cap helps a bit there and above.
100n or 10n is more useful at lower frequencies, - a NPO does not 
eliminate them - but sometimes can help the 10n/100n's a little 
further away to be useful.

> that much, when one is looking like a high impedance the other is becoming 
> a low impedance - a high impedance in parallel with a low is a low..  Take 
> the published cap models and do some SPICE sims - it is easy to see the 
> results.  Better still use real caps and a spec-an/tracking generator or 
> VNA.

I think the VNA is the tool of choice for designing this stuff.
A spec an can tell you how much noise you have got - but its tough to
be analytical when the noise injection model from a FPGA say is so
lacking.  
john

  


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