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Hello All,
Have a PCB design that is completely routed. The board information report
and DRC report state that everything is 100% routed with no violations. OK
great.
In the schematic side I generate a Netlist. Now I go to the PCB side and
from Netlist Manager I export the Netl
John,
You really don't have to do a netlist compare. I see designers doing this
all of the time. This may have developed because of a mistrust of other
programs they have used because DRCs couldn't be trusted. The bottom line
is the DRC netlist checking in versions 2.8 - 99SE SP 6 work and wo
Hello Mike,
I tried your fool proof method and everything works great. Thanks for
taking the time to help me out. Take care and have a nice night.
-Original Message-
From: Mike Reagan [mailto:[EMAIL PROTECTED]]
Sent: Thursday, February 13, 2003 2:26 PM
To: Protel EDA Forum
Su
At 06:13 PM 2/12/2003, Peter W. Richards wrote:
In Viewdraw, the 'bus label' connecting to the submodule's port determines
what gets hooked to what. If draw a bus with label FOO[7,5,3,1] connected
to a submodule port BAR[0:3] you get exactly what you
drew--FOO[7]->BAR[0], FOO[5]->BAR[1], etc.
John
You are welcomed...but I should practice what I preach. I have been using
this method with 99SE SP6 and have had flawless designs. Ok until last
week , we got a board back with power and gnd were not connected to the
input connector.The original ECO was a minor change, I imported a
Peter,
to answer your question from below, there is a way to do it.
In a top level schematic place a sheet symbol. On the sheet symbol place a
bidirectional port (e.g. 12V). Connect a wire to that port and connet it to your 12V
rail.
On a sub-circuit place a bidirectional port of the same name
