Re: [PEDA] [PROTEL EDA USERS]: Polygon plane problem

[DUTTON Phil]

Hello Ted,
I'm using SP6 with no problem.
Check under your Design Rules for correct clearances, connect styles etc.
Are you assigning the polygon to a net when you create it?

regards,
Phil.


Phil Dutton C.I.D.
Senior CAD Technician
IPC Certified Interconnect Designer

Tenix Defence Systems Pty Ltd 
Systems Division - Adelaide
Second Avenue, Technology Park,
Mawson Lakes.  SOUTH AUSTRALIA  5095


Phone   (08) 8300 4400 (reception)
Fax (08) 8349 7420
email   [EMAIL PROTECTED]
Internet Page   http//www.tenix.com



-Original Message-
From: Ted Tontis [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, 6 February 2001 6:22
To: Multiple recipients of list proteledausers
Subject: [PROTEL EDA USERS]: Polygon plane problem



I think someone already covered this problem, I could not find the response
to it. I am running 99SE with service pack 6 on windows 2k, I did my whole
project on this setup. I am now trying to pore a polygon plane and I am not
getting anywhere with it. When pored on the top layer of my board it fails
to leave a gap between the vias and traces leading to other parts. when I
double click on the pad or via on the plane I get a DRC error (short
circuit) when I double click on the polygon (one trace of it) it has no net
value. I have tried to pore it a number of times and still the same results.
I imported the Ddb to a computer running 99SE service pack 5 and still I get
the same results. I sent Protel a e-mail regarding this but I do not expect
them to get right on it. I hope anyone might have a idea or something to
help me get this problem fixed, they want to get this board into the proto
shop some time this week. 

Thank you,
Ted Tontis 
Design Engineer 
Engage Networks Inc. 
[EMAIL PROTECTED] 
PH 414.273.7600 Ext. 7607 




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Re: [PEDA] [PROTEL EDA USERS]: Polygon plane problem

[Andrew Gray]

Hate to state the obvious, but did you set up all relevant clearance
parameters?

- Original Message -
From: Ted Tontis <[EMAIL PROTECTED]>
To: Multiple recipients of list proteledausers
<[EMAIL PROTECTED]>
Sent: Tuesday, 6 February 2001 08:51
Subject: [PROTEL EDA USERS]: Polygon plane problem


>
> I think someone already covered this problem, I could not find the
response
> to it. I am running 99SE with service pack 6 on windows 2k, I did my whole
> project on this setup. I am now trying to pore a polygon plane and I am
not
> getting anywhere with it. When pored on the top layer of my board it fails
> to leave a gap between the vias and traces leading to other parts. when I
> double click on the pad or via on the plane I get a DRC error (short
> circuit) when I double click on the polygon (one trace of it) it has no
net
> value. I have tried to pore it a number of times and still the same
results.
> I imported the Ddb to a computer running 99SE service pack 5 and still I
get
> the same results. I sent Protel a e-mail regarding this but I do not
expect
> them to get right on it. I hope anyone might have a idea or something to
> help me get this problem fixed, they want to get this board into the proto
> shop some time this week.
>
> Thank you,
> Ted Tontis
> Design Engineer
> Engage Networks Inc.
> [EMAIL PROTECTED]
> PH 414.273.7600 Ext. 7607
>
>
>
>
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[PEDA] [PROTEL EDA USERS]: Polygon plane problem

[Ted Tontis]

I think someone already covered this problem, I could not find the response
to it. I am running 99SE with service pack 6 on windows 2k, I did my whole
project on this setup. I am now trying to pore a polygon plane and I am not
getting anywhere with it. When pored on the top layer of my board it fails
to leave a gap between the vias and traces leading to other parts. when I
double click on the pad or via on the plane I get a DRC error (short
circuit) when I double click on the polygon (one trace of it) it has no net
value. I have tried to pore it a number of times and still the same results.
I imported the Ddb to a computer running 99SE service pack 5 and still I get
the same results. I sent Protel a e-mail regarding this but I do not expect
them to get right on it. I hope anyone might have a idea or something to
help me get this problem fixed, they want to get this board into the proto
shop some time this week. 

Thank you,
Ted Tontis 
Design Engineer 
Engage Networks Inc. 
[EMAIL PROTECTED] 
PH 414.273.7600 Ext. 7607 




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*  email address you originally used to subscribe (do not
*  give an alias unless it was used to subscribe).
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*  to unsubscribe or to subscribe a new email address.
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