Re: [PEDA] help with a stack ??
Just remember to balance you layer stack thicknesses to prevent the board from being warped. - Original Message - From: "Jon Elson" <[EMAIL PROTECTED]> To: "Protel EDA Forum" <[EMAIL PROTECTED]> Sent: Thursday, February 21, 2002 3:59 PM Subject: Re: [PEDA] help with a stack ?? > Robison Michael R CNIN wrote: > > > hello, > > > > i've got a negative (ECL) and a positive (TTL) power plane > > on a board i'm doing. right now i'm figuring on a matching > > ground plane for each power supply, spaced close to the > > rail for switching capacitance. here's the stack i'm > > thinking of: > > > > critical traces > > gnd > > -5.2V > > noncritical traces > > noncritical traces > > +5V > > gnd > > critical traces > > > > does this seem reasonable? i have some semblance of controlled > > impedance with each trace layer referenced to a dc plane. > > other stacks suggestions are welcomed. > > Well, depending on how the board fabricator will actually assemble the > "book" of laminates and prepregs, it should be doable. I guess the > critical > thing is to make sure the critical traces and ground are etched from a > double-sided laminate, then the non-crit traces and power will be on > other > laminates, so you end up with 4 double-sided laminates. This could > cause the noncritical traces to be awfully close together, but also the > power and ground planes will be close together, giving more distributed > capacitance. > > I have done a lot of ECL and mixed ECL/TTL/CMOS mixed analog/digital > boards, mostly on 4 layers. I generally have only one gnd plane and one > > split power plane. Some of the power planes get very complicated, with > interdigitated (zig-zag) voltage regions to bring power under the pads > where it is needed. Some of the inputs to these boards are pretty > tightly > controlled impedances, and so signals on one side are using the gnd for > a ground plane, and signals on the other side use the power planes for > ground plane. I've never really had a problem with the ground plane > issues. I have had crosstalk, and had to completely re place one board > to make the signal flow in, around and out without high level digital > signals ever crossing over low level analog signals (this was on a > 6-layer > board, so I ended up using two signal layers on one side of the > power-gnd > planes for analog, and the other side for digital.) > > For a board like you propose, I would try to use only one gnd plane, and > > use split planes for the + and - voltage supplies. This might get you > down to a 6 layer board, and cut costs. > > > but i need both the ground planes common to each other. > > can i EVEN have two planes called GND? is having two ground > > planes a bad idea? if two ground planes is not a bad idea, > > then how do i tie them together? NOTE: if i tie them together > > i would like to do it in a way that doesn't mess up my design > > rules check. i've noticed that additional vias and traces > > added to a pcb outside the schematic can make the design rules > > check flag them. > > Yeah, I think Protel may have a problem with this. If you have 2 > planes assigned to net GND, then every via or through-hole that > is assigned to net GND will probably have a thermal connection to > BOTH planes. This may be fine, electrically, but may cause problems > in solderability, and certainly will drive techs doing any rework > nuts. > > > i have another question. this is iffy, but i'm a heathen > > designer anyway. this is just a proto board, and although i'd > > like controlled impedance, i don't want to pay for it. SO, > > what i am thinking is that if i get an 8-layer board at the > > standard 62 mil thickness, that they are going to be just about > > forced to give me between 6 to 8 mils between layers, without > > me ever having to spec it. does this sound right? > > I don't think a good board house will charge extra for this, if > you figure it out in advance. DON'T design the board in a vacuum, > ie. figure out what you want and then submit the design. Call > the board fab of your choice, and get them to TELL YOU what > they will use for laminate thickness for this build-up. THEN, you > just use that info to calculate trace width. That way, your job > fits in with their preferred flow. > > How tight a controlled impedance is this? I routinely work with stuff > where analog signals need controlled impedance of 50 Ohms +/- 1 Ohm, > or there are serious reflections. To keep ECL happy, you do
Re: [PEDA] help with a stack ??
At 02:25 PM 2/21/2002 -0500, Robison Michael R CNIN wrote: >hello, > >i've got a negative (ECL) and a positive (TTL) power plane >on a board i'm doing. right now i'm figuring on a matching >ground plane for each power supply, spaced close to the >rail for switching capacitance. here's the stack i'm >thinking of: > >critical traces >gnd >-5.2V >noncritical traces >noncritical traces >+5V >gnd >critical traces > >does this seem reasonable? i have some semblance of controlled >impedance with each trace layer referenced to a dc plane. >other stacks suggestions are welcomed. Since price is an object, you might be able to cut two layers by doing something like this: trace gnd trace trace split power trace You'd have to be able to partition the circuits and you'd have to be very careful how you cross the plane split. You would want no critical traces to cross the split on layers 4 or 6, and layer 1 would be preferred to layer 3. But this would normally be quite doable. >but i need both the ground planes common to each other. >can i EVEN have two planes called GND? You can have two planes which have the GND net assigned to them. Normally you would do nothing else, all ground vias would connect to both planes. You might even add vias in some places to stitch them together more thoroughly. A summary of the principles involved is to watch where the return current will flow and keep the loop area to a minimum. Ideally the return current flows directly below the trace at a constant impedance, but when you switch layers with a via, the current will seek the nearest via or will use the interplane capacitance, and for this reason a better stackup might be trace trace gnd split power trace trace The reason for this is that the interplane capacitance can be maximized. In this case, traces on layers 1 and 2 can be controlled impedance, though the appropriate trace width will of course be larger on layer 1. > is having two ground >planes a bad idea? if two ground planes is not a bad idea, >then how do i tie them together? NOTE: if i tie them together >i would like to do it in a way that doesn't mess up my design >rules check. i've noticed that additional vias and traces >added to a pcb outside the schematic can make the design rules >check flag them. Not if they are assigned the correct nets. To assign a net to a via, just place it touching copper with the appropriate net, and it will pick up that net. Then you can move it to final position. Of course, you can always edit a via to the net you want later, but this way avoids generating, even temporarily, any DRC markers. As to two ground planes, you might have more than that in a complex stackup. Not a problem, except for cost, and sometimes the layers get too thin. It is easier to control impedance on wide traces (i.e., at a given impedance, the thicker the dielectric the wider the trace) because of fab tolerances. >i have another question. this is iffy, but i'm a heathen >designer anyway. this is just a proto board, and although i'd >like controlled impedance, i don't want to pay for it. SO, >what i am thinking is that if i get an 8-layer board at the >standard 62 mil thickness, that they are going to be just about >forced to give me between 6 to 8 mils between layers, without >me ever having to spec it. does this sound right? Better: you can specify the thickness of the material they use, if that does not add cost. Ask them what the dielectric constant of it will be. Or, if you are using a cheap fast proto service like Advanced Circuits where you can have any color as long as it is white, ask them what they will use, then control your trace widths accordingly. Sure, it won't be exact, but this is for folk music, isn't it? (Actually, I know that Mr. Robison does electronics for a very serious employer, but I also understand that the applications are not mission critical, unless things have changed. If you need serious impedance control, you will have to pay for it, but many applications will not need that, even if they are high speed; and this is indeed an engineering question) [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] help with a stack ??
Mike, I've run into trouble by assuming the board house would equalize dielectric thickness in the layer stack. Some do, some don't. I now add a fab note to "equalize dielectric thickness +/- 10%" to get an approximately known dielectric thickness. Or you can specify the prepreg thickness between critical copper layers, even in a proto. Brian Foothill Services LLC >i have another question. this is iffy, but i'm a heathen >designer anyway. this is just a proto board, and although i'd >like controlled impedance, i don't want to pay for it. SO, >what i am thinking is that if i get an 8-layer board at the >standard 62 mil thickness, that they are going to be just about >forced to give me between 6 to 8 mils between layers, without >me ever having to spec it. does this sound right? > >thank you, miker > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] help with a stack ??
Robison Michael R CNIN wrote: > hello, > > i've got a negative (ECL) and a positive (TTL) power plane > on a board i'm doing. right now i'm figuring on a matching > ground plane for each power supply, spaced close to the > rail for switching capacitance. here's the stack i'm > thinking of: > > critical traces > gnd > -5.2V > noncritical traces > noncritical traces > +5V > gnd > critical traces > > does this seem reasonable? i have some semblance of controlled > impedance with each trace layer referenced to a dc plane. > other stacks suggestions are welcomed. Well, depending on how the board fabricator will actually assemble the "book" of laminates and prepregs, it should be doable. I guess the critical thing is to make sure the critical traces and ground are etched from a double-sided laminate, then the non-crit traces and power will be on other laminates, so you end up with 4 double-sided laminates. This could cause the noncritical traces to be awfully close together, but also the power and ground planes will be close together, giving more distributed capacitance. I have done a lot of ECL and mixed ECL/TTL/CMOS mixed analog/digital boards, mostly on 4 layers. I generally have only one gnd plane and one split power plane. Some of the power planes get very complicated, with interdigitated (zig-zag) voltage regions to bring power under the pads where it is needed. Some of the inputs to these boards are pretty tightly controlled impedances, and so signals on one side are using the gnd for a ground plane, and signals on the other side use the power planes for ground plane. I've never really had a problem with the ground plane issues. I have had crosstalk, and had to completely re place one board to make the signal flow in, around and out without high level digital signals ever crossing over low level analog signals (this was on a 6-layer board, so I ended up using two signal layers on one side of the power-gnd planes for analog, and the other side for digital.) For a board like you propose, I would try to use only one gnd plane, and use split planes for the + and - voltage supplies. This might get you down to a 6 layer board, and cut costs. > but i need both the ground planes common to each other. > can i EVEN have two planes called GND? is having two ground > planes a bad idea? if two ground planes is not a bad idea, > then how do i tie them together? NOTE: if i tie them together > i would like to do it in a way that doesn't mess up my design > rules check. i've noticed that additional vias and traces > added to a pcb outside the schematic can make the design rules > check flag them. Yeah, I think Protel may have a problem with this. If you have 2 planes assigned to net GND, then every via or through-hole that is assigned to net GND will probably have a thermal connection to BOTH planes. This may be fine, electrically, but may cause problems in solderability, and certainly will drive techs doing any rework nuts. > i have another question. this is iffy, but i'm a heathen > designer anyway. this is just a proto board, and although i'd > like controlled impedance, i don't want to pay for it. SO, > what i am thinking is that if i get an 8-layer board at the > standard 62 mil thickness, that they are going to be just about > forced to give me between 6 to 8 mils between layers, without > me ever having to spec it. does this sound right? I don't think a good board house will charge extra for this, if you figure it out in advance. DON'T design the board in a vacuum, ie. figure out what you want and then submit the design. Call the board fab of your choice, and get them to TELL YOU what they will use for laminate thickness for this build-up. THEN, you just use that info to calculate trace width. That way, your job fits in with their preferred flow. How tight a controlled impedance is this? I routinely work with stuff where analog signals need controlled impedance of 50 Ohms +/- 1 Ohm, or there are serious reflections. To keep ECL happy, you don't need that tight a control, especially if the traces are short. +/- 10 % should be close enough, and that is much easier to provide. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] help with a stack ??
Mike, use this stack up non critical gnd critical -5 gnd critical +5 (better if this was ground) non critical or gnd critical non critical power gnd non critical critical gnd (if power switch critical and non critical) two reasons why I say put the critical in the center of the board. First your board vender will be able to control the thickness of the traces better, when they plate the board. Second your board will be a lot more quite. You will then only have to factor in the etch factor to keep you impedance. Regards, Ted * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] help with a stack ??
[PEDA] help with a stack ??
hello, i've got a negative (ECL) and a positive (TTL) power plane on a board i'm doing. right now i'm figuring on a matching ground plane for each power supply, spaced close to the rail for switching capacitance. here's the stack i'm thinking of: critical traces gnd -5.2V noncritical traces noncritical traces +5V gnd critical traces does this seem reasonable? i have some semblance of controlled impedance with each trace layer referenced to a dc plane. other stacks suggestions are welcomed. but i need both the ground planes common to each other. can i EVEN have two planes called GND? is having two ground planes a bad idea? if two ground planes is not a bad idea, then how do i tie them together? NOTE: if i tie them together i would like to do it in a way that doesn't mess up my design rules check. i've noticed that additional vias and traces added to a pcb outside the schematic can make the design rules check flag them. i have another question. this is iffy, but i'm a heathen designer anyway. this is just a proto board, and although i'd like controlled impedance, i don't want to pay for it. SO, what i am thinking is that if i get an 8-layer board at the standard 62 mil thickness, that they are going to be just about forced to give me between 6 to 8 mils between layers, without me ever having to spec it. does this sound right? thank you, miker * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
