On 08/03/19 08:20, Thomas Huth wrote:
> cirrus-ci.com also has the possibility to run CI tasks on macOS.
> Since most of the QEMU developers do not have access to macOS yet,
> let's add a CI pipeline for this operating system here, too.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Acked-by: Ed
On Thu, Mar 07, 2019 at 01:32:41AM +0100, Philippe Mathieu-Daudé wrote:
> On 3/6/19 9:05 PM, BALATON Zoltan wrote:
> > Add (partial) emulation of the on-board GPU of the machine. This
> > allows the PMON2000 firmware to run and should also work with Linux
> > console but probably not with X yet.
>
David Gibson writes:
> On Thu, Mar 07, 2019 at 02:03:16PM +0100, Markus Armbruster wrote:
>> Machine "ref405ep" maps its flash memory at address 2^32 - image size.
>> Image size is rounded up to the next multiple of 64KiB. Useless,
>> because pflash_cfi02_realize() fails with "failed to read
> > > * The first priority should be adding an in-process iscsi target that
> > > can be managed with QMP, similar to the built-in NBD server.
> >
> > Well, people used to manage iscsi targets through targetcli, a command
> > line utility. Our intention is, with targetcli and qemu-tcmu, user
cirrus-ci.com also has the possibility to run CI tasks on macOS.
Since most of the QEMU developers do not have access to macOS yet,
let's add a CI pipeline for this operating system here, too.
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Ed Maste
Signed-off-by: Thomas Huth
---
v2:
- Move
"Zoltán Kővágó" writes:
> On 2019-03-07 16:56, Gerd Hoffmann wrote:
>> On Tue, Feb 26, 2019 at 02:39:38AM +0100, Zoltán Kővágó wrote:
>>> On 2019-02-20 22:37, Kővágó, Zoltán wrote:
>>> [...]
diff --git a/audio/audio.c b/audio/audio.c
index ce8e6ea8c2..8ad8cbe559 100644
---
On 08/03/2019 15:30, David Gibson wrote:
> On Fri, Mar 08, 2019 at 12:44:20PM +1100, Alexey Kardashevskiy wrote:
>> NVIDIA V100 GPUs have on-board RAM which is mapped into the host memory
>> space and accessible as normal RAM via an NVLink bus. The VFIO-PCI driver
>> implements special regions
** No longer affects: qemu
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1818880
Title:
Deadlock when detaching network interface
Status in Ubuntu Cloud Archive:
Confirmed
Status in qemu
On 07/03/2019 22.52, Li-Wen Hsu wrote:
> On Fri, Mar 8, 2019 at 4:30 AM Thomas Huth wrote:
>>
>> On 07/03/2019 21.26, Ed Maste wrote:
>>> On Mon, 4 Mar 2019 at 07:11, Philippe Mathieu-Daudé
>>> wrote:
On 3/4/19 11:32 AM, Thomas Huth wrote:
> cirrus-ci.com also has the possibility
On 07/03/2019 22.10, Paolo Bonzini wrote:
> On 04/03/19 12:08, Philippe Mathieu-Daudé wrote:
>> +macos_task:
>> + osx_instance:
>> +image: high-sierra-base
>> + env:
>> +CIRRUS_CLONE_DEPTH: 1
>> + install_script:
>> +- brew install pkg-config glib pixman make sdl2
>
> Could you
On 08/03/2019 02.32, Philippe Mathieu-Daudé wrote:
> The 'file_data' is allocated by read_splashfile() (introduced in
> commit 3d3b8303c6f8). It is then used by fw_cfg_add_file(). Due
> to the contract interface of fw_cfg_add_file(), it has to be valid
> for the lifetime of the FwCfg object.
>
>
Public bug reported:
When qemu-bridge-helper run failed, its parent process qemu is still alive.
This is my command line:
qemu-system-x86_64 -curses -enable-kvm -cpu host -smp 4 -m 4096 \
-vnc :1 \
-kernel /data/xugang_vms/boot/vmlinuz \
-initrd /data/xugang_vms/boot/initram \
-append
On 08/03/2019 07.47, Gerd Hoffmann wrote:
> Hi,
>
>>> As an aside, it might be a nice idea to drop the in-srcdir
>>> build altogether for QEMU anyway -- it's not really a very
>>> good idea and it means our build system has to cope with two
>>> different ways of working to no particularly
On 08/03/2019 02.32, Philippe Mathieu-Daudé wrote:
> Back in abe147e0ce4 when fw_cfg_add_file() was introduced, there
> was no QOM design, object where not created and released at runtime.
> Later 38f3adc34d finished the QOM conversion of the fw_cfg device,
> adding the fw_cfg_common_realize()
On 3/8/19 1:01 AM, David Gibson wrote:
> On Thu, Mar 07, 2019 at 11:35:38PM +0100, Cédric Le Goater wrote:
>> The ISA bus has a different DT nodename on POWER9. Compute the name
>> when the PnvChip is realized, that is before it is used by the machine
>> to populate the device tree with the ISA
On 08/03/2019 02.32, Philippe Mathieu-Daudé wrote:
> The 'boot_splash_filedata_size' was introduced as a global variable
> in 3d3b8303c6f. This variable is used as a 'size' argument to the
> fw_cfg_add_file(). This function has an interface contract with his
> 'data' argument, but there is no such
On 3/8/19 1:19 AM, David Gibson wrote:
> On Thu, Mar 07, 2019 at 08:07:41AM +0100, Cédric Le Goater wrote:
>> On 3/7/19 5:18 AM, David Gibson wrote:
>>> On Wed, Mar 06, 2019 at 09:50:23AM +0100, Cédric Le Goater wrote:
> [snip]
+static uint64_t pnv_lpc_mmio_read(void *opaque, hwaddr addr,
Hi,
> > As an aside, it might be a nice idea to drop the in-srcdir
> > build altogether for QEMU anyway -- it's not really a very
> > good idea and it means our build system has to cope with two
> > different ways of working to no particularly useful end.
>
> I was actually going to propose
On Thu, Mar 7, 2019 at 9:55 PM Marc-André Lureau
wrote:
>
> Hi
>
> On Thu, Mar 7, 2019 at 3:00 PM manish jaggi wrote:
> >
> > Hi List,
> > I am trying to run qemu with spice gl=on with the below command line
> > and getting errors.
> >
> > qemu-system-x86_64 -cdrom
On 3/8/19 1:17 AM, David Gibson wrote:
> On Thu, Mar 07, 2019 at 07:37:51AM +0100, Cédric Le Goater wrote:
>> On 3/7/19 5:10 AM, David Gibson wrote:
>>> On Wed, Mar 06, 2019 at 09:50:20AM +0100, Cédric Le Goater wrote:
The PSI bridge on POWER9 is very similar to POWER8. The BAR is still
From: Alex Bennée
We reject undersized backends with a rather enigmatic "failed to read
the initial flash content" error.
We happily accept oversized images, ignoring their tail. Throwing
away parts of firmware that way is pretty much certain to end in an
even more enigmatic failure to boot.
On Thu, Mar 07, 2019 at 08:01:35AM +0100, Markus Armbruster wrote:
> Alex Bennée writes:
>
> > Markus Armbruster writes:
> >
> >> Machine "ref405ep" maps its flash memory at address 2^32 - image size.
> >> Image size is rounded up to the next multiple of 64KiB. Useless,
> >> because
On Thu, Mar 07, 2019 at 03:02:32PM -0700, Alex Williamson wrote:
> On Thu, 7 Mar 2019 16:05:18 +1100
> Alexey Kardashevskiy wrote:
> > diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c
> > index 40a12001f580..15ec0b4c2723 100644
> > --- a/hw/vfio/pci-quirks.c
> > +++
On Fri, Mar 08, 2019 at 12:44:20PM +1100, Alexey Kardashevskiy wrote:
> NVIDIA V100 GPUs have on-board RAM which is mapped into the host memory
> space and accessible as normal RAM via an NVLink bus. The VFIO-PCI driver
> implements special regions for such GPUs and emulates an NVLink bridge.
>
Patchew URL:
https://patchew.org/QEMU/20190220100358.25566-1-vsement...@virtuozzo.com/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT
On Thu, Mar 07, 2019 at 04:27:36PM +0100, Thomas Huth wrote:
> On 07/03/2019 15.58, Philippe Mathieu-Daudé wrote:
> > Hi Thomas,
>
> ? -^
>
> I could take the patch for tests/data/acpi/rebuild-expected-aml.sh
> through the qtests tree (if Michael or Igor don't want to take it), but
> the
On 3/7/19 7:58 AM, Peter Maydell wrote:
On Wed, 13 Feb 2019 at 04:02, Sandra Loosemore wrote:
This patch adds support for libgloss semihosting to Nios II bare-metal
emulation.
Signed-off-by: Sandra Loosemore
Signed-off-by: Julian Brown
Do you have a link to the spec that defines this
On Thu, Mar 07, 2019 at 02:40:39PM +, Stefan Hajnoczi wrote:
> On Wed, Mar 06, 2019 at 07:55:31PM +0800, Peter Xu wrote:
> > +/*
> > + * We should do this as soon as we enter the thread, because the
> > + * function will silently fail if it fails to acquire the
> > + *
Hi, Stefan
This problem is related with backend vhost-user socket abnormal cases, we
shouldn't ask customers to configure it manually for backend's issues or
depends on guest OS's network configuration.
Thanks
> -Original Message-
> From: Stefan Hajnoczi [mailto:stefa...@gmail.com]
>
On 3/7/19 7:32 PM, Philippe Mathieu-Daudé wrote:
> The Edk2Crypto object is used to hold configuration values specific
> to EDK2.
>
> The edk2_add_host_crypto_policy() function loads crypto policies
> from the host, and register them as fw_cfg named file items.
> So far only the 'https' policy is
On 3/7/19 7:32 PM, Philippe Mathieu-Daudé wrote:
> When debugging a paravirtualized guest firmware, it results very
> useful to dump the fw_cfg table.
> Add a QMP command which returns the most useful fields.
> Since the QMP protocol is not designed for passing stream data,
> we don't display a
-20190307
for you to fetch changes up to b35aec8597e86911d5553c94769f914a52a8b389:
target/hppa: Optimize blr r0,rn (2019-03-07 17:43:12 -0800)
Fix use after free on temporary.
Optmize branch to next insn via br r0
On Fri, Mar 08, 2019 at 01:53:28AM +, Lilijun (Jerry, Cloud Networking)
wrote:
> > -Original Message-
> > From: Michael S. Tsirkin [mailto:m...@redhat.com]
> >
> > On Wed, Mar 06, 2019 at 07:36:44AM +, Lilijun (Jerry, Cloud Networking)
> > wrote:
> > > Thanks a lot for your
For priv levels 1 & 2, we were doing so from do_ibranch_priv.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/hppa/translate.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index
We can eliminate an extra TB in this case, which merely
loads a "return address" into rn.
Signed-off-by: Richard Henderson
---
target/hppa/translate.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index
> -Original Message-
> From: Michael S. Tsirkin [mailto:m...@redhat.com]
>
> On Wed, Mar 06, 2019 at 07:36:44AM +, Lilijun (Jerry, Cloud Networking)
> wrote:
> > Thanks a lot for your advice.
> >
> > Maybe there are two methods to add this option:
> > 1) Firstly, add a vhost-user
Enable the EDK2 Crypto Policy features on the Virt machine.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/virt.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index bb7255a080..bc2b14af48 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -56,6 +56,7
Enable the EDK2 Crypto Policy features on the PC machine.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 0848cdc18f..736211d623 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -38,6 +38,7 @@
The Edk2Crypto object is used to hold configuration values specific
to EDK2.
The edk2_add_host_crypto_policy() function loads crypto policies
from the host, and register them as fw_cfg named file items.
So far only the 'https' policy is supported.
An usercase example is the 'HTTPS Boof' feature
When debugging a paravirtualized guest firmware, it results very
useful to dump the fw_cfg table.
Add a QMP command which returns the most useful fields.
Since the QMP protocol is not designed for passing stream data,
we don't display a fw_cfg item data, only it's size:
{ "execute":
Add a function to read the full content of file on the host, and add
a new 'file' name item to the fw_cfg device.
Signed-off-by: Philippe Mathieu-Daudé
---
v2: s/ptr/data, corrected documentation (Laszlo)
---
hw/nvram/fw_cfg.c | 21 +
include/hw/nvram/fw_cfg.h | 23
NVIDIA V100 GPUs have on-board RAM which is mapped into the host memory
space and accessible as normal RAM via an NVLink bus. The VFIO-PCI driver
implements special regions for such GPUs and emulates an NVLink bridge.
NVLink2-enabled POWER9 CPUs also provide address translation services
which
Similar to the previous commit, use the FWCfgState lifetime state
to hold the 'bst_le16' variable content (renaned as time_le16).
Doing so we avoid a memory leak.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/nvram/fw_cfg.c | 6 +++---
include/hw/nvram/fw_cfg.h | 3 +++
2 files changed,
When debugging a paravirtualized guest firmware, it results very
useful to dump the fw_cfg table.
Add a HMP command which displays the most useful fields.
We display each fw_cfg item data in hexadecimal (only the first 8
bytes):
$ (echo info fw_cfg; echo q) | qemu-system-x86_64 -S -monitor stdio
Each implementation (I/O and MEM) calls fw_cfg_file_slots_allocate()
then fw_cfg_common_realize().
Simplify by moving the fw_cfg_file_slots_allocate() call into
fw_cfg_common_realize() where it belongs.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/nvram/fw_cfg.c | 17 ++---
1 file
Due to the contract interface of fw_cfg_add_file(), the
'reboot_timeout' data has to be valid for the lifetime of the
FwCfg object. For this reason it is copied on the heap with
memdup().
The object state, 'FWCfgState', is also meant to be valid during the
lifetime of the object.
Move the
The 'file_data' is allocated by read_splashfile() (introduced in
commit 3d3b8303c6f8). It is then used by fw_cfg_add_file(). Due
to the contract interface of fw_cfg_add_file(), it has to be valid
for the lifetime of the FwCfg object.
Keep a reference of 'file_data' in FWCfgState to be able to
Add two helpers: one to represent a binary data as a string of
hexadecimal values, and one to restore a such string into its
original binary data.
Signed-off-by: Philippe Mathieu-Daudé
---
include/qemu/cutils.h | 33 ++
util/cutils.c | 55
Called by fw_cfg_common_realize(), fw_cfg_file_slots_allocate()
allocates various buffers.
Free them in fw_cfg_common_unrealize().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/nvram/fw_cfg.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
index
The load/store API eases code review.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/nvram/fw_cfg.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
index 684c2cf00a..8eb76a382c 100644
--- a/hw/nvram/fw_cfg.c
+++ b/hw/nvram/fw_cfg.c
@@
The 'boot_splash_filedata_size' was introduced as a global variable
in 3d3b8303c6f. This variable is used as a 'size' argument to the
fw_cfg_add_file(). This function has an interface contract with his
'data' argument, but there is no such contract for 'size' (this is
not a referenced pointer).
Signed-off-by: Philippe Mathieu-Daudé
---
v2: Drop files that do use fw_cfg (Michael):
- hw/i386/acpi-build.c
- hw/i386/pc.c
---
hw/acpi/piix4.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index 8fd25a5926..7b98121070 100644
--- a/hw/acpi/piix4.c
+++
Back in abe147e0ce4 when fw_cfg_add_file() was introduced, there
was no QOM design, object where not created and released at runtime.
Later 38f3adc34d finished the QOM conversion of the fw_cfg device,
adding the fw_cfg_common_realize() method.
The time has come to add the equivalent destructor and
Add fw_cfg_arch_key_name() to be able to resolve architecture
specific keys. All architectures do have specific keys, thus
implement this function. Architectures that don't use the fw_cfg
device don't have to implement this function, however to ease
the Makefile rules and satisfy the linking, we
Hi,
This series consists of:
- trivial cleanups, add trace events (was in v1)
- add QMP/HMP commands to display the list of fw_cfg entries (reworked from v1)
- add unrealize() method and deallocate various buffers (new in v2)
- add fw_cfg_add_file_from_host (was in v1)
- add
Since commit 578f3c7b0835 ("arm: add fw_cfg to "virt" board",
2014-12-22), the machvirt_init() unconditionally creates the
fw_cfg object. Later, commit c30e15658b1b ("smbios: implement
smbios support for mach-virt", 2015-09-07) added a superfluous
null-check on it.
Remove this superfluous check.
On 3/1/19 10:21 PM, Yoshinori Sato wrote:
> My git repository is bellow.
> git://git.pf.osdn.net/gitroot/y/ys/ysato/qemu.git
Somehow patch 1 did not arrive, so I am reviewing based on
rebasing this branch against master, and then looking at the diff.
> +struct CCop;
Unused?
> +static inline
On Thu, Mar 07, 2019 at 11:35:44PM +0100, Cédric Le Goater wrote:
> The POWER9 processor does not support per-core frequency control. The
> cores are arranged in groups of four, along with their respective L2
> and L3 caches, into a structure known as a Quad. The frequency must be
> managed at the
On Thu, Mar 07, 2019 at 11:35:43PM +0100, Cédric Le Goater wrote:
> Provide a new class attribute to define XSCOM operations per CPU
> family and add a couple of XSCOM addresses controlling the power
> management states of the core on POWER9.
>
> Signed-off-by: Cédric Le Goater
Applied, thanks.
On Thu, Mar 07, 2019 at 11:35:39PM +0100, Cédric Le Goater wrote:
> The LPC Controller on POWER9 is very similar to the one found on
> POWER8 but accesses are now done via on MMIOs, without the XSCOM and
> ECCB logic. The device tree is populated differently so we add a
> specific POWER9 routine
On Thu, Mar 07, 2019 at 11:35:45PM +0100, Cédric Le Goater wrote:
> We now have enough support to let the XSCOM test run on POWER9.
>
> Signed-off-by: Cédric Le Goater
Applied, thanks.
> ---
> tests/pnv-xscom-test.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git
On Thu, Mar 07, 2019 at 11:35:46PM +0100, Cédric Le Goater wrote:
> To improve OPAL/skiboot support. We don't need to strictly model these
> XSCOM accesses.
>
> Signed-off-by: Cédric Le Goater
Applied, thanks.
> ---
> hw/ppc/pnv_xscom.c | 33 +++--
> 1 file
On Thu, Mar 07, 2019 at 11:35:47PM +0100, Cédric Le Goater wrote:
> Activate only stop0 and stop1 levels. We should not need more levels
> when under QEMU.
>
> Signed-off-by: Cédric Le Goater
Applied, although..
> ---
> hw/ppc/pnv.c | 15 +++
> 1 file changed, 15 insertions(+)
>
On Thu, Mar 07, 2019 at 11:35:48PM +0100, Cédric Le Goater wrote:
> We now have enough support to boot a PowerNV machine with a POWER9
> processor. Allow HV mode on POWER9.
>
> Signed-off-by: Cédric Le Goater
Applied.
> ---
> target/ppc/translate_init.inc.c | 3 ++-
> 1 file changed, 2
On Thu, Mar 07, 2019 at 11:35:42PM +0100, Cédric Le Goater wrote:
> The OCC on POWER9 is very similar to the one found on POWER8. Provide
> the same routines with P9 values for the registers and IRQ number.
>
> Signed-off-by: Cédric Le Goater
Applied, thanks.
> ---
>
> Changes in v2 :
>
>
On Thu, Mar 07, 2019 at 11:35:41PM +0100, Cédric Le Goater wrote:
> To ease the introduction of the OCC model for POWER9, provide a new
> class attributes to define XSCOM operations per CPU family and a PSI
> IRQ number.
>
> Signed-off-by: Cédric Le Goater
> Reviewed-by: David Gibson
Applied,
On Thu, Mar 07, 2019 at 11:35:40PM +0100, Cédric Le Goater wrote:
> This is just a simple reminder that SerIRQ routing should be
> addressed.
>
> Signed-off-by: Cédric Le Goater
> ---
Applied, thanks.
> include/hw/ppc/pnv_lpc.h | 2 ++
> hw/ppc/pnv_lpc.c | 14 ++
> 2
On Thu, Mar 07, 2019 at 07:37:51AM +0100, Cédric Le Goater wrote:
> On 3/7/19 5:10 AM, David Gibson wrote:
> > On Wed, Mar 06, 2019 at 09:50:20AM +0100, Cédric Le Goater wrote:
> >> The PSI bridge on POWER9 is very similar to POWER8. The BAR is still
> >> set through XSCOM but the controls are now
On Thu, Mar 07, 2019 at 04:38:28PM +1100, Alexey Kardashevskiy wrote:
>
>
> On 07/03/2019 16:21, David Gibson wrote:
> > The qemu coding standard is to use CamelCase for type and structure names,
> > and the pseries code follows that... sort of. There are quite a lot of
> > places where we bend
On Thu, Mar 07, 2019 at 08:07:41AM +0100, Cédric Le Goater wrote:
> On 3/7/19 5:18 AM, David Gibson wrote:
> > On Wed, Mar 06, 2019 at 09:50:23AM +0100, Cédric Le Goater wrote:
[snip]
> >> +static uint64_t pnv_lpc_mmio_read(void *opaque, hwaddr addr, unsigned
> >> size)
> >> +{
> >> +
On 2019-03-07 16:56, Gerd Hoffmann wrote:
> On Tue, Feb 26, 2019 at 02:39:38AM +0100, Zoltán Kővágó wrote:
>> On 2019-02-20 22:37, Kővágó, Zoltán wrote:
>> [...]
>>> diff --git a/audio/audio.c b/audio/audio.c
>>> index ce8e6ea8c2..8ad8cbe559 100644
>>> --- a/audio/audio.c
>>> +++ b/audio/audio.c
gt;>
>> The following changes since commit 32694e98b8d7a246345448a8f707d2e11d6c65e2:
>>
>> Merge remote-tracking branch
>> 'remotes/ehabkost/tags/machine-next-pull-request' into staging (2019-03-06
>> 18:52:19 +)
>>
>> are available in the Git repository at:
&g
On Thu, 7 Mar 2019, BALATON Zoltan wrote:
I still have the unfinished version using the callbacks which might work with
force_shadow like for cirrus but I'd need to finish and clean that up. Now
that we have both implemented probably will allow switching between them but
may not be able to do
Patchew URL:
https://patchew.org/QEMU/20190221150353.93de8746...@zero.eik.bme.hu/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN
At least two machines, the PPC mac99 and MIPS fulong2e, have an ATI
gfx chip by default (Rage 128 Pro and M6/RV100 respectively) and
guests running on these and the PMON2000 firmware of the fulong2e
expect this to be available. Fortunately these are very similar chips
so they can be mostly
On Thu, Mar 07, 2019 at 11:35:38PM +0100, Cédric Le Goater wrote:
> The ISA bus has a different DT nodename on POWER9. Compute the name
> when the PnvChip is realized, that is before it is used by the machine
> to populate the device tree with the ISA devices.
>
> Signed-off-by: Cédric Le Goater
On Thu, Mar 07, 2019 at 06:05:17PM +, Mark Cave-Ayland wrote:
> All TCG vector operations require pointers to the base address of the vector
> rather than separate access to the top and bottom 64-bits. Convert the VMX TCG
> instructions to use a new avr_full_offset() function instead of
On Thu, Mar 07, 2019 at 06:05:14PM +, Mark Cave-Ayland wrote:
> Instead of having multiple copies of the offset calculation logic, move it to
> a
> single fpr_offset() function.
>
> Signed-off-by: Mark Cave-Ayland
> Reviewed-by: Richard Henderson
Applied, thanks.
> ---
>
On Thu, Mar 07, 2019 at 11:35:35PM +0100, Cédric Le Goater wrote:
> The PSI bridge on POWER9 is very similar to POWER8. The BAR is still
> set through XSCOM but the controls are now entirely done with MMIOs.
> More interrupts are defined and the interrupt controller interface has
> changed to
On Thu, Mar 07, 2019 at 02:03:16PM +0100, Markus Armbruster wrote:
> Machine "ref405ep" maps its flash memory at address 2^32 - image size.
> Image size is rounded up to the next multiple of 64KiB. Useless,
> because pflash_cfi02_realize() fails with "failed to read the initial
> flash content"
On Thu, Mar 07, 2019 at 06:05:15PM +, Mark Cave-Ayland wrote:
> Instead of having multiple copies of the offset calculation logic, move it to
> a
> single vsrl_offset() function.
>
> This commit also renames the existing get_vsr()/set_vsr() functions to
> get_vsrl()/set_vsrl() which better
On Thu, Mar 07, 2019 at 06:05:13PM +, Mark Cave-Ayland wrote:
> After some investigation into Andrew's report of corruption in his ppc64le
> tests at https://lists.gnu.org/archive/html/qemu-devel/2019-02/msg07234.html,
> I
> discovered the underlying cause was that the first 32 VSX registers
On Thu, Mar 07, 2019 at 11:35:34PM +0100, Cédric Le Goater wrote:
> To ease the introduction of the PSI bridge model for POWER9, abstract
> the POWER chip differences in a PnvPsi class model and introduce a
> specific Pnv8Psi type for POWER8. POWER8 interface to the interrupt
> controller is still
On Thu, Mar 07, 2019 at 09:20:56PM +, Mark Cave-Ayland wrote:
> These two patches correct a mistake in the original FWPathProvider
> implementation for Old World and New World Macs whereby the alias name is
> used instead of the node name.
>
> Signed-off-by: Mark Cave-Ayland
Applied,
On Thu, Mar 07, 2019 at 11:35:37PM +0100, Cédric Le Goater wrote:
> It will ease the introduction of the LPC Controller model for POWER9.
>
> Signed-off-by: Cédric Le Goater
> Reviewed-by: David Gibson
Applied, thanks.
> ---
> include/hw/ppc/pnv_lpc.h | 15 +++
> hw/ppc/pnv.c
On Thu, Mar 07, 2019 at 11:35:36PM +0100, Cédric Le Goater wrote:
> The PowerNV LPC Controller exposes different sets of registers for
> each of the functional units it encompasses, among which the OPB
> (On-Chip Peripheral Bus) Master and Arbitrer and the LPC HOST
> Controller.
>
> The mapping
On Thu, Mar 07, 2019 at 04:05:16PM +1100, Alexey Kardashevskiy wrote:
> On sPAPR vfio_listener_region_add() is called in 2 situations:
> 1. a new listener is registered from vfio_connect_container();
> 2. a new IOMMU Memory Region is added from rtas_ibm_create_pe_dma_window().
>
> In both cases
On Thu, Mar 07, 2019 at 06:05:16PM +, Mark Cave-Ayland wrote:
> It isn't possible to include internal.h from cpu.h so move the Vsr* macros
> into cpu.h alongside the other VMX/VSX register access functions.
>
> Signed-off-by: Mark Cave-Ayland
Applied, thanks.
> ---
> target/ppc/cpu.h
> On Mar 7, 2019, at 11:27 AM, Stefan Hajnoczi wrote:
>
> On Thu, Mar 07, 2019 at 02:51:20PM +, Daniel P. Berrangé wrote:
>> On Thu, Mar 07, 2019 at 02:26:09PM +, Stefan Hajnoczi wrote:
>>> On Wed, Mar 06, 2019 at 11:22:53PM -0800, elena.ufimts...@oracle.com wrote:
diff --git
> From: Alex Williamson [mailto:alex.william...@redhat.com]
> Sent: Friday, March 8, 2019 1:44 AM
> > >
> > > > This kind of data needs to be saved / loaded in pre-copy and
> > > > stop-and-copy phase.
> > > > The data of device memory is held in device memory region.
> > >
The ISA bus has a different DT nodename on POWER9. Compute the name
when the PnvChip is realized, that is before it is used by the machine
to populate the device tree with the ISA devices.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/pnv.h | 2 ++
hw/ppc/pnv.c | 18
The PowerNV LPC Controller exposes different sets of registers for
each of the functional units it encompasses, among which the OPB
(On-Chip Peripheral Bus) Master and Arbitrer and the LPC HOST
Controller.
The mapping addresses of each register range are correct but the sizes
are too large. Fix
Activate only stop0 and stop1 levels. We should not need more levels
when under QEMU.
Signed-off-by: Cédric Le Goater
---
hw/ppc/pnv.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index e68d419203e8..8be4d4cbf785 100644
--- a/hw/ppc/pnv.c
+++
To ease the introduction of the OCC model for POWER9, provide a new
class attributes to define XSCOM operations per CPU family and a PSI
IRQ number.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
---
Changes in v2:
- new attributes to define XSCOM operations per CPU family and a
We now have enough support to let the XSCOM test run on POWER9.
Signed-off-by: Cédric Le Goater
---
tests/pnv-xscom-test.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/tests/pnv-xscom-test.c b/tests/pnv-xscom-test.c
index 974f8da5b240..63d464048d53 100644
--- a/tests/pnv-xscom-test.c
Hello,
Here is the second round of the patchset adding support for the POWER9
processor to the PowerNV machine. It includes POWER9 models for the
PSI host bridge, the LPC controller, and a minimalist OCC, some
extensions of the CPU core model to support POWER9 XSCOM addresses and
a new PnvQuad
Provide a new class attribute to define XSCOM operations per CPU
family and add a couple of XSCOM addresses controlling the power
management states of the core on POWER9.
Signed-off-by: Cédric Le Goater
---
Changes in v2 :
- new class attribute to define XSCOM operations per CPU family
The POWER9 processor does not support per-core frequency control. The
cores are arranged in groups of four, along with their respective L2
and L3 caches, into a structure known as a Quad. The frequency must be
managed at the Quad level.
Provide a basic Quad model to fake the settings done by the
We now have enough support to boot a PowerNV machine with a POWER9
processor. Allow HV mode on POWER9.
Signed-off-by: Cédric Le Goater
---
target/ppc/translate_init.inc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate_init.inc.c
The OCC on POWER9 is very similar to the one found on POWER8. Provide
the same routines with P9 values for the registers and IRQ number.
Signed-off-by: Cédric Le Goater
---
Changes in v2 :
- made use of the new class attributes for POWER9
include/hw/ppc/pnv.h | 1 +
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