[PATCH v5] docs/devel: Added cache plugin to the plugins docs

Signed-off-by: Mahmoud Mandour --- v4 -> v5: Fixed the illustrated command since it has path problems... docs/devel/tcg-plugins.rst | 59 ++ 1 file changed, 59 insertions(+) diff --git a/docs/devel/tcg-plugins.rst b/docs/devel/tcg-plugins.rst index

[PATCH v4 0/3] Fuzzer pattern-matching, timeouts, and instrumentation-filtering

v4: - Instead of changing the patterns in the AC97 and ES1370 configs, make the type/name pattern matching case-insensitive. - Copy the instrumentation filter into the build-dir, so it can be adapted on-the-fly. v3: - Check in ./configure whether clang supports

[PATCH v4 2/3] fuzz: add an instrumentation filter

By default, -fsanitize=fuzzer instruments all code with coverage information. However, this means that libfuzzer will track coverage over hundreds of source files that are unrelated to virtual-devices. This means that libfuzzer will optimize inputs for coverage observed in timer code, memory APIs

[PATCH v4 3/3] fuzz: make object-name matching case-insensitive

We have some configs for devices such as the AC97 and ES1370 that were not matching memory-regions correctly, because the configs provided lowercase names. To resolve these problems and prevent them from occurring again in the future, convert both the pattern and names to lower-case, prior to

[PATCH v4 1/3] fuzz: adjust timeout to allow for longer inputs

Using a custom timeout is useful to continue fuzzing complex devices, even after we run into some slow code-path. However, simply adding a fixed timeout to each input effectively caps the maximum input length/number of operations at some artificial value. There are two major problems with this: 1.

Re: [PATCH qemu v22] spapr: Implement Open Firmware client interface

On 6/28/21 02:38, BALATON Zoltan wrote: On Fri, 25 Jun 2021, Alexey Kardashevskiy wrote: The PAPR platform describes an OS environment that's presented by a combination of a hypervisor and firmware. The features it specifies require collaboration between the firmware and the hypervisor.

Re: tests: ReverseDebugging_AArch64.test_aarch64_virt -> InvalidPacketError

On 25.06.2021 20:01, Philippe Mathieu-Daudé wrote: Hi Pavel, FYI as of commit 050cee12315 ("Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-updates-250621-1' into staging") Doesn't it mean, that the real culprit is hidden and we should bisect? the ReverseDebugging_AArch64

Re: [PATCH] arm/aspeed: rainier: Add i2c eeproms and muxes

On Mon, 28 Jun 2021 at 04:49, Joel Stanley wrote: > > On Mon, 28 Jun 2021 at 04:33, Andrew Jeffery wrote: > > > > > > > > On Fri, 25 Jun 2021, at 14:36, Joel Stanley wrote: > > > These are the devices documented by the Rainier device tree. With this > > > we can see the guest discovering the

Re: [PATCH] arm/aspeed: rainier: Add i2c eeproms and muxes

On Mon, 28 Jun 2021 at 04:33, Andrew Jeffery wrote: > > > > On Fri, 25 Jun 2021, at 14:36, Joel Stanley wrote: > > These are the devices documented by the Rainier device tree. With this > > we can see the guest discovering the multiplexers and probing the eeprom > > devices: > > > > i2c i2c-2:

Re: [PATCH] arm/aspeed: rainier: Add i2c eeproms and muxes

On Fri, 25 Jun 2021, at 14:36, Joel Stanley wrote: > These are the devices documented by the Rainier device tree. With this > we can see the guest discovering the multiplexers and probing the eeprom > devices: > > i2c i2c-2: Added multiplexed i2c bus 16 > i2c i2c-2: Added multiplexed i2c bus

Re: Qemu on Haiku

On 28/06/2021 02.38, BALATON Zoltan wrote: On Sun, 27 Jun 2021, Richard Zak wrote: Hopefully last questions: [...] 2) Is it acceptable to have a patch for the configure script, or is that generated? I found some Haiku-related issues there The configure script is not generated, it's just a

[Bug 1295587] Re: Temporal freeze and slowdown while using emulated sb16

[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1295587 Title: Temporal

Re: [PATCH v5 0/6] crypto: Make QCryptoTLSCreds* structures private

Hi, qemu-nbd.c still refers to members of QCryptoTLSCreds* and can't be compiled. Regards, Akihiko Odaki On 2021/06/17 21:18, Philippe Mathieu-Daudé wrote: Missing review: 5 & 6 Follow Daniel suggestion to simplify qcrypto TLS implementations, aiming to solve the OSX build failure. Since

[PATCH v2] ui/cocoa: Use NSWindow's ability to resize

This change brings two new features: - The window will be resizable if "Zoom To Fit" is eanbled - The window can be made full screen by clicking full screen button provided by the platform. (The left-top green button.) Signed-off-by: Akihiko Odaki --- ui/cocoa.m | 542

[PATCH] ui/cocoa: Use NSWindow's ability to resize

This change brings two new features: - The window will be resizable if "Zoom To Fit" is eanbled - The window can be made full screen by clicking full screen button provided by the platform. (The left-top green button.) Signed-off-by: Akihiko Odaki --- ui/cocoa.m | 542

Re: Qemu on Haiku

On Sun, 27 Jun 2021, Richard Zak wrote: Hopefully last questions: 1) What's the format for the subject line for patches? I'm seeing things like "[PATCH 2/4]" or "[PATCH v2 00/10]" what do those numbers mean in this context? I didn't see anything about this mentioned in the SubmitAPatch wiki.

Re: [PATCH] target/riscv: pmp: Fix some typos

On Sun, Jun 27, 2021 at 9:57 PM Bin Meng wrote: > > %s/CSP/CSR > %s/thie/the > > Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Alistair > --- > > target/riscv/pmp.c | 10 +- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/target/riscv/pmp.c

Re: [PATCH 1/2] docs/system: riscv: Fix CLINT name in the sifive_u doc

On Mon, Jun 28, 2021 at 12:28 AM Bin Meng wrote: > > It's Core *Local* Interruptor, not 'Level'. > > Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Alistair > --- > > docs/system/riscv/sifive_u.rst | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git

Re: Qemu on Haiku

Hopefully last questions: 1) What's the format for the subject line for patches? I'm seeing things like "[PATCH 2/4]" or "[PATCH v2 00/10]" what do those numbers mean in this context? I didn't see anything about this mentioned in the SubmitAPatch wiki. 2) Is it acceptable to have a patch for the

Re: [PATCH v8 18/19] arm: Enable Windows 10 trusted SMCCC boot call

On 15.06.21 13:02, Peter Maydell wrote: > On Wed, 19 May 2021 at 21:23, Alexander Graf wrote: >> Windows 10 calls an SMCCC call via SMC unconditionally on boot. It lives >> in the trusted application call number space, but its purpose is unknown. >> >> In our current SMC implementation, we

Re: [PATCH v8 19/19] hvf: arm: Handle Windows 10 SMC call

On 15.06.21 11:31, Peter Maydell wrote: > On Wed, 19 May 2021 at 21:23, Alexander Graf wrote: >> Windows 10 calls an SMCCC call via SMC unconditionally on boot. It lives >> in the trusted application call number space, but its purpose is unknown. >> >> In our current SMC implementation, we

Re: [PATCH v8 13/19] hvf: Add Apple Silicon support

Hi Peter, On 15.06.21 12:21, Peter Maydell wrote: > On Wed, 19 May 2021 at 21:23, Alexander Graf wrote: >> With Apple Silicon available to the masses, it's a good time to add support >> for driving its virtualization extensions from QEMU. >> >> This patch adds all necessary architecture specific

Re: [PATCH V3 5/6] block/rbd: add write zeroes support

> Am 26.06.2021 um 17:57 schrieb Ilya Dryomov : > > On Mon, Jun 21, 2021 at 10:49 AM Peter Lieven wrote: >> >>> Am 18.06.21 um 12:34 schrieb Ilya Dryomov: >>> On Fri, Jun 18, 2021 at 11:00 AM Peter Lieven wrote: Am 16.06.21 um 14:34 schrieb Ilya Dryomov: > On Wed, May 19, 2021 at

[Bug 1897568] Re: Strange keyboard behaviour in Vim editor

Can someone explain why the patch keeps the incorrect behaviour as the default? It’s silly. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1897568 Title: Strange keyboard behaviour in Vim editor

[PATCH 0/4] ppc/Pegasos2: Firmware replacement using VOF

Based-on: <20210625055155.2252896-1-...@ozlabs.ru> ^ That is v22 of Alexey's VOF patch With this series on top of VOF v22 I can now boot Linux and MorphOS on pegasos2 without a firmware blob so I hope this is enough to get this board in 6.1 and also have it enabled so people can start using it

[PATCH 1/4] ppc/pegasos2: Introduce Pegasos2MachineState structure

Add own machine state structure which will be used to store state needed for firmware emulation. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé --- hw/ppc/pegasos2.c | 50 +++ 1 file changed, 37 insertions(+), 13 deletions(-) diff

[PATCH 4/4] ppc/pegasos2: Implement some RTAS functions with VOF

Linux uses RTAS functions to access PCI devices so we need to provide these with VOF. Implement some of the most important functions to allow booting Linux with VOF. With this the board is now usable without a binary ROM image and we can enable it by default as other boards. Signed-off-by:

[PATCH 3/4] ppc/pegasos2: Use Virtual Open Firmware as firmware replacement

The pegasos2 board comes with an Open Firmware compliant ROM based on SmartFirmware but it has some changes that are not open source therefore the ROM binary cannot be included in QEMU. Guests running on the board however depend on services provided by the firmware. The Virtual Open Firmware

Re: [PATCH qemu v22] spapr: Implement Open Firmware client interface

On Fri, 25 Jun 2021, Alexey Kardashevskiy wrote: The PAPR platform describes an OS environment that's presented by a combination of a hypervisor and firmware. The features it specifies require collaboration between the firmware and the hypervisor. Since the beginning, the runtime component of

[PATCH 2/4] target/ppc: Allow virtual hypervisor on CPU without HV

Change the assert in ppc_store_sdr1() to allow vhyp to be set on CPUs without HV bit. This allows using the vhyp interface for firmware emulation on pegasos2. Signed-off-by: BALATON Zoltan --- target/ppc/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/cpu.c

[PATCH v10 4/6] migration/dirtyrate: adjust order of registering thread

From: Hyman Huang(黄勇) registering get_dirtyrate thread in advance so that both page-sampling and dirty-ring mode can be covered. Signed-off-by: Hyman Huang(黄勇) Message-Id: Reviewed-by: Peter Xu --- migration/dirtyrate.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git

[PATCH v10 6/6] migration/dirtyrate: implement dirty-ring dirtyrate calculation

From: Hyman Huang(黄勇) use dirty ring feature to implement dirtyrate calculation. introduce mode option in qmp calc_dirty_rate to specify what method should be used when calculating dirtyrate, either page-sampling or dirty-ring should be passed. introduce "dirty_ring:-r" option in hmp

[PATCH v10 0/6] support dirtyrate at the granualrity of vcpu

From: Hyman Huang(黄勇) v10 - rebase on master - pre-check if dirty log has started when calling memory_global_dirty_log_stop in the ram_save_cleanup. since it will stop dirty log unconditionally, so add if statement to ensure that memory_global_dirty_log_start/stop used in pairs. - modify

[PATCH v10 5/6] migration/dirtyrate: move init step of calculation to main thread

From: Hyman Huang(黄勇) since main thread may "query dirty rate" at any time, it's better to move init step into main thead so that synchronization overhead between "main" and "get_dirtyrate" can be reduced. Signed-off-by: Hyman Huang(黄勇) Message-Id:

[PATCH v10 3/6] migration/dirtyrate: introduce struct and adjust DirtyRateStat

From: Hyman Huang(黄勇) introduce "DirtyRateMeasureMode" to specify what method should be used to calculate dirty rate, introduce "DirtyRateVcpu" to store dirty rate fore each vcpu. use union to store stat data of specific mode Signed-off-by: Hyman Huang(黄勇) Message-Id:

[PATCH v10 1/6] KVM: introduce dirty_pages and kvm_dirty_ring_enabled

From: Hyman Huang(黄勇) dirty_pages is used to calculate dirtyrate via dirty ring, when enabled, kvm-reaper will increase the dirty pages after gfns being dirtied. kvm_dirty_ring_enabled shows if kvm-reaper is working. dirtyrate thread could use it to check if measurement can base on dirty ring

[PATCH v10 2/6] memory: make global_dirty_tracking a bitmask

From: Hyman Huang(黄勇) since dirty ring has been introduced, there are two methods to track dirty pages of vm. it seems that "logging" has a hint on the method, so rename the global_dirty_log to global_dirty_tracking would make description more accurate. dirty rate measurement may start or stop

Re: [RFC PATCH 00/11] RISC-V: support clic v0.9 specification

LIU Zhiwei 於 2021年4月9日 週五 下午3:58寫道： > This patch set gives an implementation of "RISC-V Core-Local Interrupt > Controller(CLIC) Version 0.9-draft-20210217". It comes from [1], where > you can find the pdf format or the source code. > > I take over the job from Michael Clark, who gave the first

Re: [RFC PATCH 10/11] target/riscv: Update interrupt handling in CLIC mode

LIU Zhiwei 於 2021年4月9日 週五 下午3:54寫道： > Decode CLIC interrupt information from exccode, includes interrupt > priviledge mode, interrupt level, and irq number. > > Then update CSRs xcause, xstatus, xepc, xintstatus and jump to > correct PC according to the CLIC specification. > > Signed-off-by: LIU

Re: [PATCH] target/riscv: pmp: Fix some typos

On 6/27/21 1:57 PM, Bin Meng wrote: > %s/CSP/CSR > %s/thie/the > > Signed-off-by: Bin Meng > --- > > target/riscv/pmp.c | 10 +- > 1 file changed, 5 insertions(+), 5 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

[PATCH 2/2] docs/system: riscv: Add documentation for virt machine

This adds detailed documentation for RISC-V `virt` machine, including the following information: - Supported devices - Hardware configuration information - Boot options - Running Linux kernel - Running U-Boot Signed-off-by: Bin Meng --- docs/system/riscv/virt.rst | 138

[PATCH 1/2] docs/system: riscv: Fix CLINT name in the sifive_u doc

It's Core *Local* Interruptor, not 'Level'. Signed-off-by: Bin Meng --- docs/system/riscv/sifive_u.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst index 32d0a1b85d..01108b5ecc 100644 ---

Re: [PATCH v2] block/rbd: Add support for rbd image encryption

On Sun, Jun 27, 2021 at 1:46 PM Or Ozeri wrote: > > Starting from ceph Pacific, RBD has built-in support for image-level > encryption. > Currently supported formats are LUKS version 1 and 2. > > There are 2 new relevant librbd APIs for controlling encryption, both expect > an > open image

Re: [RFC PATCH 11/11] target/riscv: Update interrupt return in CLIC mode

LIU Zhiwei 於 2021年4月9日 週五 下午3:55寫道： > When a vectored interrupt is selected and serviced, the hardware will > automatically clear the corresponding pending bit in edge-triggered mode. > This may lead to a lower priviledge interrupt pending forever. > > Therefore when interrupts return, pull a

[PATCH v2] target/riscv: csr: Remove redundant check in fp csr read/write routines

The following check: if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -RISCV_EXCP_ILLEGAL_INST; } is redundant in fflags/frm/fcsr read/write routines, as the check was already done in fs(). Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v2: -

[PATCH] target/riscv: pmp: Fix some typos

%s/CSP/CSR %s/thie/the Signed-off-by: Bin Meng --- target/riscv/pmp.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 82ed020b10..54abf42583 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -456,7 +456,7 @@

[PATCH v2] block/rbd: Add support for rbd image encryption

Starting from ceph Pacific, RBD has built-in support for image-level encryption. Currently supported formats are LUKS version 1 and 2. There are 2 new relevant librbd APIs for controlling encryption, both expect an open image context: rbd_encryption_format: formats an image (i.e. writes the LUKS

Re: [PATCH] block/rbd: Add support for rbd image encryption

On Sun, Jun 27, 2021 at 1:09 PM Or Ozeri wrote: > > Should I still leave the encryption format part of the state, and just not > report it? or should I also remove it from the state? I'd remove it, reverting to the previous version of the patch except instead of fetching the size with

Re: [PATCH v3 1/1] yank: Unregister function when using TLS migration

On 14.06.21 13:57, Dr. David Alan Gilbert wrote: > cc'ing in qemu-stable - I think we'd probably want this on 6.0 > (It's currently merged as 7de2e8565335c13fb3516cddbe2e40e366cce273 ). > Although you'll probably also want the missing dependency fix > Philippe is working (See: > Mathieu- ( 42)

RE: [PATCH] block/rbd: Add support for rbd image encryption

Should I still leave the encryption format part of the state, and just not report it? or should I also remove it from the state?-"Ilya Dryomov" wrote: -To: "Or Ozeri" From: "Ilya Dryomov" Date: 06/27/2021 02:00PMCc:

Re: [PATCH] block/rbd: Add support for rbd image encryption

On Sun, Jun 27, 2021 at 10:44 AM Or Ozeri wrote: > > Ilya, > > I fixed according to your suggestions, except for the passphrase zeroing. > Looks like it's not a one-liner, but rather a long list of ifdefs to try and > cover all possible platforms/compilers (this is what I've seen they do in >

Re: [RFC PATCH 08/11] target/riscv: Update CSR xnxti in CLIC mode

LIU Zhiwei 於 2021年4月9日 週五 下午3:52寫道： > The CSR can be used by software to service the next horizontal interrupt > when it has greater level than the saved interrupt context > (held in xcause`.pil`) and greater level than the interrupt threshold of > the corresponding privilege mode, > >

Re: [RFC PATCH 06/11] target/riscv: Update CSR xtvec in CLIC mode

LIU Zhiwei 於 2021年4月9日 週五 下午3:51寫道： > The new CLIC interrupt-handling mode is encoded as a new state in the > existing WARL xtvec register, where the low two bits of are 11. > > Signed-off-by: LIU Zhiwei > --- > target/riscv/csr.c | 22 -- > 1 file changed, 20

Re: [PATCH] block/rbd: Add support for rbd image encryption

Ilya,I fixed according to your suggestions, except for the passphrase zeroing.Looks like it's not a one-liner, but rather a long list of ifdefs to try and cover all possible platforms/compilers (this is what I've seen they do in k5-int.h).I didn't want to copy this into rbd.c.I guess that the

[PATCH] block/rbd: Add support for rbd image encryption

Starting from ceph Pacific, RBD has built-in support for image-level encryption. Currently supported formats are LUKS version 1 and 2. There are 2 new relevant librbd APIs for controlling encryption, both expect an open image context: rbd_encryption_format: formats an image (i.e. writes the LUKS

Re: [RFC PATCH 07/11] target/riscv: Update CSR xtvt in CLIC mode

LIU Zhiwei 於 2021年4月9日 週五 下午3:52寫道： > The xtvt WARL XLEN-bit CSR holds the base address of the trap vector table, > aligned on a 64-byte or greater power-of-two boundary. > > Signed-off-by: LIU Zhiwei > --- > target/riscv/cpu.h | 2 ++ > target/riscv/cpu_bits.h | 2 ++ >

Re: [RFC PATCH 02/11] target/riscv: Update CSR xintthresh in CLIC mode

Frank Chang 於 2021年6月27日 週日 上午1:23寫道： > LIU Zhiwei 於 2021年4月9日 週五 下午3:52寫道： > >> The interrupt-level threshold (xintthresh) CSR holds an 8-bit field >> for the threshold level of the associated privilege mode. >> >> For horizontal interrupts, only the ones with higher interrupt levels >> than

Re: [RFC PATCH 04/11] target/riscv: Update CSR xie in CLIC mode

LIU Zhiwei 於 2021年4月9日 週五 下午3:51寫道： > The xie CSR appears hardwired to zero in CLIC mode, replaced by separate > memory-mapped interrupt enables (clicintie[i]). Writes to xie will be > ignored and will not trap (i.e., no access faults). > > Signed-off-by: LIU Zhiwei > --- > target/riscv/csr.c

Re: [RFC PATCH 05/11] target/riscv: Update CSR xip in CLIC mode

LIU Zhiwei 於 2021年4月9日 週五 下午3:52寫道： > The xip CSR appears hardwired to zero in CLIC mode, replaced by separate > memory-mapped interrupt pendings (clicintip[i]). Writes to xip will be > ignored and will not trap (i.e., no access faults). > > Signed-off-by: LIU Zhiwei --- > target/riscv/csr.c