On Tue, Jan 25, 2022 at 10:24:49AM -0600, Eric DeVolder wrote:
> And here is what the main snippet looks like with the above changes (a diff
> is quite messy):
>
> /*
> * Macros for use with construction of the action instructions
> */
> #define BUILD_READ_VALUE(width_in_bits) \
>
On 24/01/2022 23:13, Philippe Mathieu-Daudé via wrote:
This code is easier to review using the load/store API.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/misc/macio/cuda.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/hw/misc/macio/cuda.c
CCing Igor.
Thanks,
drew
On Wed, Jan 26, 2022 at 01:24:10PM +0800, Gavin Shan wrote:
> The default CPU-to-NUMA association is given by mc->get_default_cpu_node_id()
> when it isn't provided explicitly. However, the CPU topology isn't fully
> considered in the default association and it causes
On 24/01/2022 19:33, Philippe Mathieu-Daudé via wrote:
On 1/24/22 20:16, Alex Bennée wrote:
Philippe Mathieu-Daudé writes:
On 1/24/22 11:55, Alex Bennée wrote:
Philippe Mathieu-Daudé writes:
This is my last respin on this series which is fully reviewed.
Just to note the "b4"
On 22/01/2022 00:07, Philippe Mathieu-Daudé via wrote:
Commit 2dd285b5f3 ("tcx: make display updates thread safe")
converted this model to use the DirtyBitmapSnapshot API,
resetting the dirty bitmap in tcx_update_display(). There
is no need to do it again in the DeviceReset handler.
See more
Vladimir Sementsov-Ogievskiy writes:
> 25.01.2022 12:07, Markus Armbruster wrote:
>> Vladimir Sementsov-Ogievskiy writes:
>>
>>> We are going to generate trace events for qmp commands. We should
>>
>> QMP
>>
>>> generate both trace_*() function calls and trace-events files listing
>>> events
On Tue, 25 Jan 2022, Eric DeVolder wrote:
> Ani,
> Thanks for the feedback! Inline responses below.
> eric
>
> On 1/25/22 04:53, Ani Sinha wrote:
> >
> >
> > > +
> > > +action = ACTION_BEGIN_CLEAR_OPERATION;
> > > +BUILD_WRITE_REGISTER_VALUE(32, ERST_ACTION_OFFSET, action);
> > > +
> >
在 2022/1/25 20:46, Andrew Jones 写道:
On Tue, Jan 25, 2022 at 07:46:43PM +0800, chenxiang (M) wrote:
Hi Andrew,
在 2022/1/25 18:26, Andrew Jones 写道:
On Tue, Jan 25, 2022 at 05:15:34PM +0800, chenxiang via wrote:
From: Xiang Chen
Since the patchset ("Build ACPI Heterogeneous Memory
> On Jan 25, 2022, at 1:38 PM, Dr. David Alan Gilbert
> wrote:
>
> * Jag Raman (jag.ra...@oracle.com) wrote:
>>
>>
>>> On Jan 19, 2022, at 7:12 PM, Michael S. Tsirkin wrote:
>>>
>>> On Wed, Jan 19, 2022 at 04:41:52PM -0500, Jagannathan Raman wrote:
Allow PCI buses to be part of
The default CPU-to-NUMA association is given by mc->get_default_cpu_node_id()
when it isn't provided explicitly. However, the CPU topology isn't fully
considered in the default association and it causes CPU topology broken
warnings on booting Linux guest.
For example, the following warning
> On Jan 25, 2022, at 11:00 AM, Stefan Hajnoczi wrote:
>
> Hi Jag,
> Thanks for this latest revision. The biggest outstanding question I have
> is about the isolated address spaces design.
Thank you for taking the time to review the patches, Stefan!
>
> This patch series needs a PCIBus with
Hi Jagannathan,
On 19/1/22 22:42, Jagannathan Raman wrote:
Avocado tests for libvfio-user in QEMU - tests startup,
hotplug and migration of the server object
Signed-off-by: Elena Ufimtseva
Signed-off-by: John G Johnson
Signed-off-by: Jagannathan Raman
---
MAINTAINERS| 1
> On Jan 25, 2022, at 10:10 AM, Stefan Hajnoczi wrote:
>
> On Wed, Jan 19, 2022 at 04:42:01PM -0500, Jagannathan Raman wrote:
>> Setup a handler to run vfio-user context. The context is driven by
>> messages to the file descriptor associated with it - get the fd for
>> the context and hook up
> On Jan 25, 2022, at 9:48 AM, Stefan Hajnoczi wrote:
>
> On Wed, Jan 19, 2022 at 04:42:00PM -0500, Jagannathan Raman wrote:
>> Find the PCI device with specified id. Initialize the device context
>> with the QEMU PCI device
>>
>> Signed-off-by: Elena Ufimtseva
>> Signed-off-by: John G
From: Frank Chang
In SPI-mode, CMD58 returns R3 response with the format:
39 32 31 0
++ +---+
| R1 | |OCR|
++ +---+
Where R1
From: Luis Pires
New macros that add FLAGS and FLAGS2 checking were added for
both TRANS and TRANS64.
Signed-off-by: Luis Pires
[ferst: - TRANS_FLAGS2 instead of TRANS_FLAGS_E
- Use the new macros in load/store vector insns ]
Signed-off-by: Matheus Ferst
Reviewed-by: Richard Henderson
From: Matheus Ferst
This patch series implements 5 missing instructions from PowerISA v3.0
and 40 new instructions from PowerISA v3.1, moving 62 other instructions
to decodetree along the way.
v2:
- New patch (30) to remove xscmpnedp
Lucas Coutinho (2):
target/ppc: Move vexts[bhw]2[wd] to
From: Matheus Ferst
Signed-off-by: Matheus Ferst
---
target/ppc/helper.h | 9 ++--
target/ppc/insn32.decode| 4 ++
target/ppc/int_helper.c | 50 +
target/ppc/translate/vmx-impl.c.inc | 69 +++--
From: "Lucas Mateus Castro (alqotel)"
Moved the instructions vmulesb, vmulosb, vmuleub, vmuloub,
vmulesh, vmulosh, vmuleuh, vmulouh, vmulesw, vmulosw,
muleuw and vmulouw from legacy to decodetree. Implemented
the instructions vmulesd, vmulosd, vmuleud, vmuloud.
Signed-off-by: Lucas Mateus
Hi,
On 26/1/22 00:59, Kenneth Adam Miller wrote:
Hello all,
I would like to emulate something on a pi so that I don't have to pay as
high of a translation penalty since the guest and host will share the
same arch. I'm finding that on some forums that people have been having
trouble getting
From: "Lucas Mateus Castro (alqotel)"
Moved instructions vmulld, vmulhuw, vmulhsw, vmulhud and vmulhsd to
decodetree
Signed-off-by: Lucas Mateus Castro (alqotel)
Signed-off-by: Matheus Ferst
---
target/ppc/helper.h | 8
target/ppc/insn32.decode| 6
From: Víctor Colombo
xscmpnedp was added in ISA v3.0 but removed in v3.0B. This patch
removes this instruction as it was not in the final version of v3.0.
Signed-off-by: Víctor Colombo
Acked-by: Greg Kurz
Reviewed-by: Cédric Le Goater
Reviewed-by: Richard Henderson
Signed-off-by: Matheus
From: Víctor Colombo
Also, fixes these instructions not being capitalized.
Signed-off-by: Víctor Colombo
Signed-off-by: Matheus Ferst
---
target/ppc/fpu_helper.c | 8
target/ppc/helper.h | 8
target/ppc/translate/vsx-impl.c.inc | 30
From: Víctor Colombo
Refactor xs{max,min}cdp VSX_MAX_MINC helper to prepare for
xs{max,min}cqp implementation.
Signed-off-by: Víctor Colombo
Signed-off-by: Matheus Ferst
---
target/ppc/fpu_helper.c | 23 +--
1 file changed, 9 insertions(+), 14 deletions(-)
diff --git
From: Víctor Colombo
Signed-off-by: Víctor Colombo
Signed-off-by: Matheus Ferst
---
target/ppc/fpu_helper.c | 2 ++
target/ppc/helper.h | 2 ++
target/ppc/insn32.decode| 3 +++
target/ppc/translate/vsx-impl.c.inc | 2 ++
4 files changed, 9 insertions(+)
From: Víctor Colombo
Signed-off-by: Víctor Colombo
Signed-off-by: Matheus Ferst
---
target/ppc/fpu_helper.c | 21 +++
target/ppc/helper.h | 1 +
target/ppc/insn32.decode| 11 +++---
target/ppc/translate/vsx-impl.c.inc | 31
On 24/01/2022 20:13, Philippe Mathieu-Daudé via wrote:
This code is easier to review using the load/store API.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/misc/macio/cuda.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
Reviewed-by: Matheus Ferst
--
Matheus K. Ferst
On 1/25/22 1:00 AM, Christoph Muellner wrote:
-ori . 110 . 0010011 @i
+{
+ [
+# *** RV32 Zicbop Sandard Extension (hints in the ori-space) ***
+prefetch_i ... 0 . 110 0 0010011 @cbo_pref
+prefetch_r ... 1 . 110 0
Hello all,
I would like to emulate something on a pi so that I don't have to pay as
high of a translation penalty since the guest and host will share the same
arch. I'm finding that on some forums that people have been having trouble
getting QEMU to run on raspberry pi. The posts are kind of old,
On 22-01-25 11:18:08, Ben Widawsky wrote:
> Really awesome work Jonathan. Dan and I are wrapping up some of the kernel
> bits,
> so all I'll do for now is try to run this, but I hope to be able to review the
> parts I'm familiar with at least.
>
> On 22-01-24 17:16:23, Jonathan Cameron wrote:
>
On 1/24/22 4:17 PM, LIU Zhiwei wrote:
On 2022/1/24 上午8:59, Alistair Francis wrote:
From: Alistair Francis
This series adds a MO_ op to specify that a load instruction should
produce a store fault. This is used on RISC-V to produce a store/amo
fault when an atomic access fails.
Hi Alistair,
On 1/26/22 9:06 AM, Peter Maydell wrote:
On Tue, 25 Jan 2022 at 22:05, Richard Henderson
wrote:
On 1/11/22 3:47 AM, Idan Horowitz wrote:
If the given range specifies no addresses to be flushed there's no reason
to schedule a function on all CPUs that does nothing.
Signed-off-by: Idan
Jonathan Cameron writes:
> On Tue, 25 Jan 2022 17:02:32 +
> Alex Bennée wrote:
>
>> Jonathan Cameron writes:
>>
>> > From: Jonathan Cameron
>> >
>> > The concept of these is introduced in [1] in terms of the
>> > description the CEDT ACPI table. The principal is more general.
>> >
On 1/13/22 2:03 PM, Zenghui Yu wrote:
Hi,
I've just exercised the SVE emulation in QEMU with
| `qemu-system-aarch64 -M virt,virtualization=on,gic-version=3 \
| -cpu max -accel tcg [...]`
Since QEMU sets ID_AA64MMFR1_EL1.VH for -cpu max, the Linux guest I use
was booting with VHE enabled and
1. Use --add-trace-events when generate qmp commands
2. Add corresponding .trace-events files as outputs in qapi_files
custom target
3. Define global qapi_trace_events list of .trace-events file targets,
to fill in trace/qapi.build and to use in trace/meson.build
4. In trace/meson.build use
On Tue, 25 Jan 2022 at 22:05, Richard Henderson
wrote:
>
> On 1/11/22 3:47 AM, Idan Horowitz wrote:
> > If the given range specifies no addresses to be flushed there's no reason
> > to schedule a function on all CPUs that does nothing.
> >
> > Signed-off-by: Idan Horowitz
> > ---
> >
We don't generate trace events for tests/ and qga/ because that it is
not simple and not necessary. We have corresponding comments in both
tests/meson.build and qga/meson.build.
Still to not miss possible future qapi code generation call, and not to
forget to enable trace events generation, let's
On 1/11/22 3:47 AM, Idan Horowitz wrote:
If the given range specifies no addresses to be flushed there's no reason
to schedule a function on all CPUs that does nothing.
Signed-off-by: Idan Horowitz
---
target/arm/helper.c | 4
1 file changed, 4 insertions(+)
diff --git
Move error_propagate() to if (err) and make "if (err)" block mandatory.
This is to simplify further commit, which will bring trace events
generation for QMP commands.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
docs/devel/qapi-code-gen.rst | 2 +-
scripts/qapi/commands.py | 10
Previous commits enabled trace events generation for most of QAPI
generated code (except for tests/ and qga/). Let's update documentation
to illustrate it.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
docs/devel/qapi-code-gen.rst | 21 -
1 file changed, 20 insertions(+),
Add trace generation disabled by default and new option --gen-trace to
enable it. The next commit will enable it for qapi/, but not for qga/
and tests/. Making it work for the latter two would involve some Meson
hackery to ensure we generate the trace-events files before trace-tool
uses them.
We are going to generate trace events for QMP commands. We should
generate both trace_*() function calls and trace-events files listing
events for trace generator.
So, add an output module FOO.trace-events for each FOO schema module.
Since we're going to add trace events only to command
This series aims to add trace points for each qmp command with help of
qapi code generator.
v5: small fixes and rewordings, + reshuffle patches so that main meson change
now is like in v3 and Paolo's a-b make sense again.
01: - fix/reword commit message
- fix typing in qapi/gen.py
-
Making trace generation work for tests/ and qga/ would involve some
Meson hackery to ensure we generate the trace-events files before
trace-tool uses them. Since we don't actually support tracing there
anyway, we bypass that problem.
Let's add corresponding comments.
Signed-off-by: Vladimir
On 1/11/22 3:47 AM, Idan Horowitz wrote:
+/*
+ * If the length is larger than the jump cache size, then it will take
+ * longer to clear each entry individually than it will to clear it all.
+ */
+if (d.len >= (TARGET_PAGE_SIZE * TB_JMP_CACHE_SIZE)) {
+
On 1/14/22 7:20 AM, Philipp Tomsich wrote:
new file mode 100644
index 00..b8a5d031b5
--- /dev/null
+++ b/target/riscv/insn_trans/trans_xventanacondops.inc
The filename suffix should be ".c.inc".
+static bool gen_condmask(DisasContext *ctx, arg_r *a, TCGCond cond)
+{
+TCGv dest =
24.01.2022 23:15, Alex Bennée wrote:
From: Michael Tokarev
For a long time, we assumed that libxml2 is necessary for parallels
block format support (block/parallels*). However, this format actually
does not use libxml [*]. Since this is the only user of libxml2 in
whole QEMU tree, we can drop
On 1/14/22 7:20 AM, Philipp Tomsich wrote:
+static inline bool always_true_p(CPURISCVState *env
__attribute__((__unused__)),
+ DisasContext *ctx
__attribute__((__unused__)))
+{
+return true;
+}
Drop the inline; the function will be instantiated so that
> On Jan 25, 2022, at 5:44 AM, Stefan Hajnoczi wrote:
>
> On Wed, Jan 19, 2022 at 04:41:56PM -0500, Jagannathan Raman wrote:
>> Signed-off-by: Elena Ufimtseva
>> Signed-off-by: John G Johnson
>> Signed-off-by: Jagannathan Raman
>> ---
>> hw/remote/machine.c | 57
On 1/24/22 16:15, Fabiano Rosas wrote:
The --disable-tcg build broke when do_rfi stopped being inlined.
Fixes: 62e79ef914 ("target/ppc: Remove static inline")
Signed-off-by: Fabiano Rosas
---
Reviewed-by: Daniel Henrique Barboza
target/ppc/excp_helper.c | 2 --
1 file changed, 2
On 25/1/22 20:24, Michael S. Tsirkin wrote:
__get_cpuid_max returns an unsigned value.
For consistency, store the result in an unsigned variable.
Found by running ./configure --extra-cflags=-Wconversion
Cc: Paolo Bonzini
Cc: Richard Henderson
Signed-off-by: Michael S. Tsirkin
---
Richard,
On 18.01.2022 14:21, Chao Peng wrote:
KVM_MEM_PRIVATE is not exposed by default but architecture code can turn
on it by implementing kvm_arch_private_memory_supported().
Also private memslot cannot be movable and the same file+offset can not
be mapped into different GFNs.
Signed-off-by: Yu
__get_cpuid_max returns an unsigned value.
For consistency, store the result in an unsigned variable.
Found by running ./configure --extra-cflags=-Wconversion
Cc: Paolo Bonzini
Cc: Richard Henderson
Signed-off-by: Michael S. Tsirkin
---
Richard, if appropriate pls queue this.
Thanks!
Really awesome work Jonathan. Dan and I are wrapping up some of the kernel bits,
so all I'll do for now is try to run this, but I hope to be able to review the
parts I'm familiar with at least.
On 22-01-24 17:16:23, Jonathan Cameron wrote:
> Previous version was RFC v3: CXL 2.0 Support.
> No
On Samstag, 22. Januar 2022 13:57:31 CET Volker Rümelin wrote:
Replace open-coded buffer arithmetic with the new function
audio_ring_posb(). That's the position in backward direction
of a given point at a given distance.
Signed-off-by: Volker Rümelin
---
First of all, getting rid of all those
At the start, drop membership of all supplementary groups. This is
not required.
If we have membership of "root" supplementary group and when we switch
uid/gid using setresuid/setsgid, we still retain membership of existing
supplemntary groups. And that can allow some operations which are not
* Jag Raman (jag.ra...@oracle.com) wrote:
>
>
> > On Jan 19, 2022, at 7:12 PM, Michael S. Tsirkin wrote:
> >
> > On Wed, Jan 19, 2022 at 04:41:52PM -0500, Jagannathan Raman wrote:
> >> Allow PCI buses to be part of isolated CPU address spaces. This has a
> >> niche usage.
> >>
> >>
On Tue, Jan 25, 2022 at 06:13:13PM +, Jonathan Cameron wrote:
> On Tue, 25 Jan 2022 17:15:58 +
> Alex Bennée wrote:
>
> > Jonathan Cameron writes:
> >
> > > This adds code to instantiate the slightly extended ACPI root port
> > > description in DSDT as per the CXL 2.0 specification.
>
On Tue, 25 Jan 2022 17:15:58 +
Alex Bennée wrote:
> Jonathan Cameron writes:
>
> > This adds code to instantiate the slightly extended ACPI root port
> > description in DSDT as per the CXL 2.0 specification.
> >
> > Basically a cut and paste job from the i386/pc code.
>
> This fails to
> On Jan 25, 2022, at 5:32 AM, Stefan Hajnoczi wrote:
>
> On Wed, Jan 19, 2022 at 04:41:55PM -0500, Jagannathan Raman wrote:
>> Allow hotplugging of PCI(e) devices to remote machine
>>
>> Signed-off-by: Elena Ufimtseva
>> Signed-off-by: John G Johnson
>> Signed-off-by: Jagannathan Raman
>>
On 1/25/22 18:34, Stefan Hajnoczi wrote:
> Personal repos may not have release tags (v6.0.0, v6.1.0, etc) and this
> causes cross_system_build_job to fail when pretty-printing a unique
> qemu-setup-*.exe name:
>
> version="$(git describe --match v[0-9]*)";
> ^^ fails
On Tue, Jan 25, 2022 at 10:24:49AM -0600, Eric DeVolder wrote:
> Ani,
> Thanks for the feedback! Inline responses below.
> eric
>
> On 1/25/22 04:53, Ani Sinha wrote:
> >
> >
> > On Mon, 24 Jan 2022, Eric DeVolder wrote:
> >
> > > This builds the ACPI ERST table to inform OSPM how to
On Dienstag, 25. Januar 2022 16:33:46 CET Greg Kurz wrote:
> On Sat, 22 Jan 2022 20:12:16 +0100
>
> Christian Schoenebeck wrote:
> > The 9p test cases use mkdtemp() to create a temporary directory for
> > running the 'local' 9p tests with real files/dirs. Unlike mktemp()
> > which only generates
On Tue, 25 Jan 2022 17:34:54 +
Stefan Hajnoczi wrote:
> Personal repos may not have release tags (v6.0.0, v6.1.0, etc) and this
> causes cross_system_build_job to fail when pretty-printing a unique
> qemu-setup-*.exe name:
>
> version="$(git describe --match v[0-9]*)";
>
On Tue, 25 Jan 2022 17:02:32 +
Alex Bennée wrote:
> Jonathan Cameron writes:
>
> > From: Jonathan Cameron
> >
> > The concept of these is introduced in [1] in terms of the
> > description the CEDT ACPI table. The principal is more general.
> > Unlike once traffic hits the CXL root
Personal repos may not have release tags (v6.0.0, v6.1.0, etc) and this
causes cross_system_build_job to fail when pretty-printing a unique
qemu-setup-*.exe name:
version="$(git describe --match v[0-9]*)";
^^ fails ^^^
mv -v qemu-setup*.exe
On Dienstag, 25. Januar 2022 12:08:21 CET Akihiko Odaki wrote:
> On Tue, Jan 25, 2022 at 7:32 PM Peter Maydell
wrote:
> > On Tue, 25 Jan 2022 at 04:14, Akihiko Odaki
wrote:
> > > I'm neutral about the decision. I think QEMU should avoid using
> > > Objective-C code except for interactions with
On Tue, Jan 25, 2022 at 10:32:45AM -0600, Eric DeVolder wrote:
> Hi Michael,
> Thanks for examining this! Inline response below.
> eric
>
> On 1/25/22 06:05, Michael S. Tsirkin wrote:
> > On Tue, Jan 25, 2022 at 04:23:49PM +0530, Ani Sinha wrote:
> > >
> > >
> > > On Mon, 24 Jan 2022, Eric
Based-on: <20220118104434.4117879-1-peter.mayd...@linaro.org>
[PATCH] Remove unnecessary minimum_version_id_old fields
After applying this patch, there is other use of load_state_old and
minimum_version_id_old. As there already were deprecated, just remove them.
Juan Quintela (1):
migration:
Jonathan Cameron writes:
> This adds code to instantiate the slightly extended ACPI root port
> description in DSDT as per the CXL 2.0 specification.
>
> Basically a cut and paste job from the i386/pc code.
This fails to build on all machines:
FAILED: qemu-system-mips64el
c++ -m64
Peter Maydell wrote:
> The migration code will not look at a VMStateDescription's
> minimum_version_id_old field unless that VMSD has set the
> load_state_old field to something non-NULL. (The purpose of
> minimum_version_id_old is to specify what migration version is needed
> for the code in
They were already deprecated and after ppc removal no users on the
tree. RIP.
Signed-off-by: Juan Quintela
---
docs/devel/migration.rst| 7 +--
include/migration/vmstate.h | 2 --
migration/vmstate.c | 6 --
3 files changed, 1 insertion(+), 14 deletions(-)
diff --git
Juan Quintela wrote:
> Hi
>
> Today we have the KVM devel call. We discussed how to create machines
> from QMP without needing to recompile QEMU.
>
>
> Three different problems:
> - startup QMP (*)
> not discussed today
> - one binary or two
> not discussed today
> - being able to create
Jonathan Cameron writes:
> From: Jonathan Cameron
>
> The concept of these is introduced in [1] in terms of the
> description the CEDT ACPI table. The principal is more general.
> Unlike once traffic hits the CXL root bridges, the host system
> memory address routing is implementation defined
Gerd Hoffmann writes:
> Hi,
>
>> +static void artist_vram_write4(ARTISTState *s, struct vram_buffer *buf,
>> + uint32_t offset, uint32_t data)
>
>> +static int get_vram_offset(ARTISTState *s, struct vram_buffer *buf,
>> + int pos, int
On 25/1/22 17:39, Juan Quintela wrote:
Hi
Today we have the KVM devel call. We discussed how to create machines
from QMP without needing to recompile QEMU.
Three different problems:
- startup QMP (*)
not discussed today
- one binary or two
not discussed today
- being able to create
On Tue, Jan 25, 2022 at 5:35 AM Igor Mammedov wrote:
> On Mon, 24 Jan 2022 12:11:51 -0800
> Patrick Venture wrote:
>
> > This parameter is to be used in the processor_id lower 32-bit entry in
> > the type 4 table. The upper 32-bits represent the features for the CPU.
> > This patch leaves
Hi
Please, send any topic that you are interested in covering.
For last week call, we already have one topic.
- get QMP startup early
People asked for Paolo and Daniel to discuss this, so I added them to
this email.
At the end of Monday I will send an email with the agenda or the
On 21.01.22 18:05, Emanuele Giuseppe Esposito wrote:
Allow writable exports to get BLK_PERM_RESIZE permission
from creation, in fuse_export_create().
In this way, there is no need to give the permission in
fuse_do_truncate(), which might be run in an iothread.
Permissions should be set only in
On 25.01.22 17:42, Philippe Mathieu-Daudé wrote:
> On 25/1/22 15:54, Nico Boehr wrote:
>> On Tue, 2022-01-25 at 14:13 +0100, David Hildenbrand wrote:
>>> I think you can actually just reuse in2_m2_64a, similar as we handle
>>> SCKC
>>
>> I tried my SCK tests with your patch, it works just as well
On 1/25/22 12:10, Thomas Huth wrote:
> On 24/01/2022 23.03, Philippe Mathieu-Daudé via wrote:
>> Extract fuse_fallocate_punch_hole() to avoid #ifdef'ry
>> mixed within if/else statement.
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>> block/export/fuse.c | 59
Hi
Today we have the KVM devel call. We discussed how to create machines
from QMP without needing to recompile QEMU.
Three different problems:
- startup QMP (*)
not discussed today
- one binary or two
not discussed today
- being able to create machines dynamically.
everybody agrees
On 25/1/22 15:54, Nico Boehr wrote:
On Tue, 2022-01-25 at 14:13 +0100, David Hildenbrand wrote:
I think you can actually just reuse in2_m2_64a, similar as we handle
SCKC
I tried my SCK tests with your patch, it works just as well and seems
much cleaner, thanks.
Do you want to send this or
This parameter is to be used in the processor_id entry in the type 4
table.
This parameter is set as optional and if left will use the values from
the CPU model.
This enables hiding the host information from the guest and allowing AMD
VMs to run pretending to be Intel for some userspace software
On Tue, 25 Jan 2022 13:55:29 +
Alex Bennée wrote:
Hi Alex,
Thanks for taking a look so quickly!
> Jonathan Cameron writes:
>
> > Previous version was RFC v3: CXL 2.0 Support.
> > No longer an RFC as I would consider the vast majority of this
> > to be ready for detailed review. There are
Hi Michael,
Thanks for examining this! Inline response below.
eric
On 1/25/22 06:05, Michael S. Tsirkin wrote:
On Tue, Jan 25, 2022 at 04:23:49PM +0530, Ani Sinha wrote:
On Mon, 24 Jan 2022, Eric DeVolder wrote:
This builds the ACPI ERST table to inform OSPM how to communicate
with the
Ani,
Thanks for the feedback! Inline responses below.
eric
On 1/25/22 04:53, Ani Sinha wrote:
On Mon, 24 Jan 2022, Eric DeVolder wrote:
This builds the ACPI ERST table to inform OSPM how to communicate
with the acpi-erst device.
Signed-off-by: Eric DeVolder
---
hw/acpi/erst.c | 188
The syntax of the fd passing case misses the "addr.type=" key. Add it.
Signed-off-by: Kevin Wolf
---
storage-daemon/qemu-storage-daemon.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/storage-daemon/qemu-storage-daemon.c
b/storage-daemon/qemu-storage-daemon.c
index
On Tue, Jan 25, 2022 at 08:50:54AM +0100, Gerd Hoffmann wrote:
> Hi,
>
> > > { 'struct' : 'FirmwareMappingFlash',
> > > - 'data' : { 'executable' : 'FirmwareFlashFile',
> > > - 'nvram-template' : 'FirmwareFlashFile' } }
> > > + 'data' : { 'mode': 'FirmwareFlashMode',
>
On Wed, Jan 19, 2022 at 04:42:01PM -0500, Jagannathan Raman wrote:
> Setup a handler to run vfio-user context. The context is driven by
> messages to the file descriptor associated with it - get the fd for
> the context and hook up the handler with it
>
> Signed-off-by: Elena Ufimtseva
>
On Mon, Jan 24, 2022 at 02:50:39PM +0100, Markus Armbruster wrote:
> Stefan Reiter writes:
>
> > Since the removal of the generic 'qmp_change' command, one can no longer
> > replace
> > the 'default' VNC display listen address at runtime (AFAIK). For our users
> > who
> > need to set up a
Hi Jag,
Thanks for this latest revision. The biggest outstanding question I have
is about the isolated address spaces design.
This patch series needs a PCIBus with its own Memory Space, I/O Space,
and interrupts. That way a single QEMU process can host vfio-user
servers that different VMs connect
On Wed, Jan 19, 2022 at 04:42:00PM -0500, Jagannathan Raman wrote:
> Find the PCI device with specified id. Initialize the device context
> with the QEMU PCI device
>
> Signed-off-by: Elena Ufimtseva
> Signed-off-by: John G Johnson
> Signed-off-by: Jagannathan Raman
> ---
>
Cédric Le Goater writes:
> On 1/24/22 19:46, Fabiano Rosas wrote:
>> This series splits the exception code for BookS CPUs: 970, POWER5+,
>> POWER7, POWER8, POWER9, POWER10. After dealing with the 405, let's go
>> back to something more familiar to give everyone a break.
>>
>> No upfront fixes
On Wed, Jan 19, 2022 at 04:41:59PM -0500, Jagannathan Raman wrote:
> create a context with the vfio-user library to run a PCI device
>
> Signed-off-by: Elena Ufimtseva
> Signed-off-by: John G Johnson
> Signed-off-by: Jagannathan Raman
> ---
> hw/remote/vfio-user-obj.c | 78
On Tue, 2022-01-25 at 14:13 +0100, David Hildenbrand wrote:
> I think you can actually just reuse in2_m2_64a, similar as we handle
> SCKC
I tried my SCK tests with your patch, it works just as well and seems
much cleaner, thanks.
Do you want to send this or should I make a v2 and add you as
> On Jan 25, 2022, at 5:27 AM, Stefan Hajnoczi wrote:
>
> On Wed, Jan 19, 2022 at 04:41:54PM -0500, Jagannathan Raman wrote:
>> Signed-off-by: Elena Ufimtseva
>> Signed-off-by: John G Johnson
>> Signed-off-by: Jagannathan Raman
>> ---
>> include/hw/qdev-core.h | 5 +
>>
On Wed, Jan 19, 2022 at 04:42:06PM -0500, Jagannathan Raman wrote:
> + * The client subsequetly asks the remote server for any data that
subsequently
> +static void vfu_mig_state_running(vfu_ctx_t *vfu_ctx)
> +{
> +VfuObject *o = vfu_get_private(vfu_ctx);
> +VfuObjectClass *k =
Hi!
maybe theis was already discussed earlier, but anyway: do we already
have an idea about whether (and if so how) BU "consulting" level
associates will participate in the DE community? This will be more
important as their ranks grow.
Thanks,
Paolo
Forwarded Message
On Sat, 22 Jan 2022 20:12:16 +0100
Christian Schoenebeck wrote:
> The 9p test cases use mkdtemp() to create a temporary directory for
> running the 'local' 9p tests with real files/dirs. Unlike mktemp()
> which only generates a unique file name, mkdtemp() also creates the
> directory, therefore
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