On 01/12/2022 21.51, Richard Henderson wrote:
On 12/1/22 10:44, Thomas Huth wrote:
The SET ADDRESS SPACE CONTROL FAST instruction is not privileged, it can be
used from problem space, too. Just the switching to the home address space
is privileged and should still generate a privilege
On 2/12/22 06:39, Richard Henderson wrote:
Remove whitespace at end of line, plus one place this also
highlights some missing braces.
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 33 +
tcg/ppc/tcg-target.c.inc | 2 +-
2 files changed, 18
On 2/12/22 04:00, Vikram Garhwal wrote:
Add a new machine xenpv which creates a IOREQ server to register/connect with
Xen Hypervisor.
Optional: When CONFIG_TPM is enabled, it also creates a tpm-tis-device, adds a
TPM emulator and connects to swtpm running on host machine via chardev socket
and
On 2/12/22 03:59, Vikram Garhwal wrote:
Replace g_malloc with g_new and perror with error_setg_errno.
Signed-off-by: Vikram Garhwal
---
hw/xen/xen-hvm-common.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
@@ -717,7 +717,7 @@ void destroy_hvm_domain(bool reboot)
Hi Stefano and Vikram,
On 2/12/22 03:59, Vikram Garhwal wrote:
From: Stefano Stabellini
This is done to prepare for enabling xenpv support for ARM architecture.
On ARM it is possible to have a functioning xenpv machine with only the
PV backends and no IOREQ server. If the IOREQ server
On 2/12/22 03:59, Vikram Garhwal wrote:
xen-mapcache.c contains common functions which can be used for enabling Xen on
aarch64 with IOREQ handling. Moving it out from hw/i386/xen to hw/xen to make it
accessible for both aarch64 and x86.
Signed-off-by: Vikram Garhwal
Signed-off-by: Stefano
Add one instead of dropping odd addresses to the constant pool.
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.c.inc | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index
This reverts 829e1376d940 ("tcg/s390: Introduce TCG_REG_TB"), and
several follow-up patches. The primary motivation is to reduce the
less-tested code paths, pre-z10. Secondarily, this allows the
unconditional use of TCG_TARGET_HAS_direct_jump, which might be more
important for performance than
The MIE2 facility adds 3-operand versions of multiply.
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target-con-set.h | 1 +
tcg/s390x/tcg-target.h | 1 +
tcg/s390x/tcg-target.c.inc | 34 --
3 files changed, 26 insertions(+), 10 deletions(-)
On Fri, 2022-11-11 at 10:47 -0500, Emanuele Giuseppe Esposito wrote:
> Using the new accel-blocker API, mark where ioctls are being called
> in KVM. Next, we will implement the critical section that will take
> care of performing memslots modifications atomically, therefore
> preventing any new
On Thu, Dec 01, 2022 at 06:16:46PM -0800, Vishal Annapurve wrote:
> On Tue, Oct 25, 2022 at 8:18 AM Chao Peng wrote:
> >
...
> > +}
> > +
> > +SYSCALL_DEFINE1(memfd_restricted, unsigned int, flags)
> > +{
>
> Looking at the underlying shmem implementation, there seems to be no
> way to enable
On Fri, 2022-11-11 at 10:47 -0500, Emanuele Giuseppe Esposito wrote:
> This API allows the accelerators to prevent vcpus from issuing
> new ioctls while execting a critical section marked with the
> accel_ioctl_inhibit_begin/end functions.
>
> Note that all functions submitting ioctls must mark
One has 3 register arguments; the other has 2 plus an m3 field.
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.c.inc | 57 +-
1 file changed, 32 insertions(+), 25 deletions(-)
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
Return both regular and inverted condition codes from tgen_cmp2.
This lets us choose after the fact which comparision we want.
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.c.inc | 25 +
1 file changed, 17 insertions(+), 8 deletions(-)
diff --git
Daniel P. Berrangé writes:
> On Thu, Dec 01, 2022 at 04:49:25PM +0100, Markus Armbruster wrote:
>> Daniel P. Berrangé writes:
>>
>> > On Thu, Dec 01, 2022 at 01:39:13PM +0100, Markus Armbruster wrote:
[...]
>> >> Would you like me to bump spice-server as well? To which version?
>> >
>> >
This is andc, orc, nand, nor, eqv.
We can use nor for implementing not.
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target-con-set.h | 1 +
tcg/s390x/tcg-target.h | 25 +
tcg/s390x/tcg-target.c.inc | 100 +
3 files changed, 114
The MIE2 facility adds a 3-operand signed 64x64->128 multiply.
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target-con-set.h | 1 +
tcg/s390x/tcg-target.h | 2 +-
tcg/s390x/tcg-target.c.inc | 8
3 files changed, 10 insertions(+), 1 deletion(-)
diff --git
Based-on: 20221202053958.223890-1-richard.hender...@linaro.org
("[PATCH for-8.0 v3 00/34] tcg misc patches")
This contains two patches that exercise the register pair patches
within the "tcg misc patches" patch set. Then a couple of misc
cleanups, then support for the MIE2, MIE3, and POPCOUNT
There is an older form that produces per-byte results,
and a newer form that produces per-register results,
and a vector form that produces per-element results.
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.h | 5 ++--
tcg/s390x/tcg-target.c.inc | 51
There are multiple variations, with different fields.
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.c.inc | 47 +-
1 file changed, 26 insertions(+), 21 deletions(-)
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index
Previously we hard-coded R2 and R3.
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target-con-set.h | 4 ++--
tcg/s390x/tcg-target-con-str.h | 8 +--
tcg/s390x/tcg-target.c.inc | 43 +-
3 files changed, 35 insertions(+), 20 deletions(-)
diff --git
The new select instruction provides two separate register inputs,
whereas the old load-on-condition instruction overlaps one of the
register inputs with the destination.
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.c.inc | 21 +
1 file changed, 21 insertions(+)
Generalize movcond to support pre-computed conditions, and the same
set of arguments at all times. This will be assumed by a following
patch, which needs to reuse tgen_movcond_int.
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target-con-set.h | 3 +-
tcg/s390x/tcg-target.c.inc | 78
Reuse code from movcond to conditionally copy a2 to dest,
based on the condition codes produced by FLOGR.
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target-con-set.h | 1 +
tcg/s390x/tcg-target.c.inc | 26 +++---
2 files changed, 12 insertions(+), 15
In confidential computing usages, whether a page is private or shared is
necessary information for KVM to perform operations like page fault
handling, page zapping etc. There are other potential use cases for
per-page memory attributes, e.g. to make memory read-only (or no-exec,
or exec-only,
A large page with mixed private/shared subpages can't be mapped as large
page since its sub private/shared pages are from different memory
backends and may also treated by architecture differently. When
private/shared memory are mixed in a large page, the current lpage_info
is not sufficient to
Register/unregister private memslot to fd-based memory backing store
restrictedmem and implement the callbacks for restrictedmem_notifier:
- invalidate_start()/invalidate_end() to zap the existing memory
mappings in the KVM page table.
- error() to request KVM_REQ_MEMORY_MCE and later exit
Unmap the existing guest mappings when memory attribute is changed
between shared and private. This is needed because shared pages and
private pages are from different backends, unmapping existing ones
gives a chance for page fault handler to re-populate the mappings
according to the new
In memory encryption usage, guest memory may be encrypted with special
key and can be accessed only by the guest itself. We call such memory
private memory. It's valueless and sometimes can cause problem to allow
userspace to access guest private memory. This new KVM memslot extension
allows guest
A KVM_MEM_PRIVATE memslot can include both fd-based private memory and
hva-based shared memory. Architecture code (like TDX code) can tell
whether the on-going fault is private or not. This patch adds a
'is_private' field to kvm_page_fault to indicate this and architecture
code is expected to set
Currently in mmu_notifier invalidate path, hva range is recorded and
then checked against by mmu_notifier_retry_hva() in the page fault
handling path. However, for the to be introduced private memory, a page
fault may not have a hva associated, checking gfn(gpa) makes more sense.
For existing hva
This new KVM exit allows userspace to handle memory-related errors. It
indicates an error happens in KVM at guest memory range [gpa, gpa+size).
The flags includes additional information for userspace to handle the
error. Currently bit 0 is defined as 'private memory' where '1'
indicates error
This patch series implements KVM guest private memory for confidential
computing scenarios like Intel TDX[1]. If a TDX host accesses
TDX-protected guest memory, machine check can happen which can further
crash the running host system, this is terrible for multi-tenant
configurations. The host
From: "Kirill A. Shutemov"
Introduce 'memfd_restricted' system call with the ability to create
memory areas that are restricted from userspace access through ordinary
MMU operations (e.g. read/write/mmap). The memory content is expected to
be used through the new in-kernel interface by a third
Pre-compute the function call layout for each helper at startup.
Drop TCG_CALL_DUMMY_ARG, as we no longer need to leave gaps
in the op->args[] array. This allows several places to stop
checking for NULL TCGTemp, to which TCG_CALL_DUMMY_ARG mapped.
For tcg_gen_callN, loop over the arguments once.
Use the official extend/extract functions instead of routines
that will shortly be internal to tcg.
Cc: Mark Cave-Ayland
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 21 -
1 file changed, 4 insertions(+), 17 deletions(-)
diff --git
While we initialize this value in cpu_common_reset, that
isn't called during startup, so set it as well in init.
This fixes -singlestep versus the very first TB.
Fixes: 04f5b647ed07 ("accel/tcg: Handle -singlestep in curr_cflags")
Signed-off-by: Richard Henderson
---
hw/core/cpu-common.c | 1 +
There is only one use, and BLR is perhaps even more
self-documentary than CALLR.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c.inc | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index
Prepare to replace a bunch of separate ifdefs with a
consistent way to describe the ABI of a function call.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg-internal.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/tcg/tcg-internal.h
For 32-bit hosts when TCG_TARGET_CALL_ALIGN_ARGS was set, use
TCG_CALL_ARG_EVEN. For 64-bit hosts, TCG_TARGET_CALL_ALIGN_ARGS
was silently ignored, so always use TCG_CALL_ARG_NORMAL.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 2 +-
Better to re-use the existing function for copying ops.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/plugin-gen.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
index
On 02.12.22 04:00, Vikram Garhwal wrote:
Add a new machine xenpv which creates a IOREQ server to register/connect with
Xen Hypervisor.
Optional: When CONFIG_TPM is enabled, it also creates a tpm-tis-device, adds a
TPM emulator and connects to swtpm running on host machine via chardev socket
and
The first thing that temp_sync does is check mem_coherent,
so there's no need for the caller to do so.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 0f58013a5a..36a33a122c 100644
---
Instead of requiring a separate hash table lookup,
put a pointer to the CIF into TCGHelperInfo.
Signed-off-by: Richard Henderson
Message-Id: <2022074101.2069454-27-richard.hender...@linaro.org>
[PMD: Split from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé
Message-Id:
The assignment to mem_coherent should be done with any
modification, not simply with a newly allocated register.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index db64799e03..d1e91b8acc 100644
---
Replace goto allocate_in_reg with a boolean.
Remove o_preferred_regs which isn't used, except to copy.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 45 +
1 file changed, 21 insertions(+), 24 deletions(-)
diff
We will shortly have the possibility of more that two outputs,
though only for calls (for which preferences are moot). Avoid
direct references to op->output_pref[] when possible.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 5 +
tcg/tcg.c
There are several instances where we need to be able to
allocate a pair of registers to related inputs/outputs.
Add 'p' and 'm' register constraints for this, in order to
be able to allocate the even/odd register first or second.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 2 +
Move the error-generating fallback from tcg-op.c, and
replace "_link_error" with modern QEMU_ERROR markup.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op.h | 33 +
include/tcg/tcg.h| 12
For 64-bit hosts that had TCG_TARGET_EXTEND_ARGS, set
TCG_TARGET_CALL_ARG_I32 to TCG_CALL_ARG_EXTEND.
Otherwise, use TCG_CALL_ARG_NORMAL.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 1 +
tcg/arm/tcg-target.h | 1 +
The count is not itself an enumerator. Move it outside to
prevent the compiler from considering it with -Wswitch-enum.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
We copied all of the arguments in copy_op_nocheck.
We only need to replace the one argument that we change.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/plugin-gen.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/accel/tcg/plugin-gen.c
The function pointer is immediately after the output and input
operands; no need to search.
Signed-off-by: Richard Henderson
---
accel/tcg/plugin-gen.c | 29 +++--
1 file changed, 11 insertions(+), 18 deletions(-)
diff --git a/accel/tcg/plugin-gen.c
This contains a few bits that I've queued for 8.0, as well
as the first half of the TCGv_i128 patch set (just prior to
the introduction of TCG_TYPE_I128).
Included are the paired register patches, which have seen
changes since v2, and a bit more testing on s390x host
(which uses register pairs
The hppa host code has been removed since 2013; this
should have been deleted at the same time.
Fixes: 802b5081233a ("tcg-hppa: Remove tcg backend")
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 1 -
tcg/arm/tcg-target.h | 1 -
This eliminates an ifdef for TCI, and will be required for
expanding the call for TCGv_i128.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 12 ++--
tcg/aarch64/tcg-target.c.inc | 12 +---
tcg/arm/tcg-target.c.inc
From: Mark Cave-Ayland
Convert tcg/README to rst and move it to docs/devel as a new "TCG Intermediate
Representation" page. There are a few minor changes to improve the aesthetic
of the final output which are as follows:
- Rename the title from "Tiny Code Generator - Fabrice Bellard" to "TCG
We have been allocating a worst case number of arguments
to support calls. Instead, allow the size to vary.
By default leave space for 4 args, to maximize reuse,
but allow calls to increase the number of args to 32.
Signed-off-by: Richard Henderson
---
include/exec/helper-head.h | 2 --
Record the location of a TCGTemp within a larger object.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 1 +
tcg/tcg.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index
Unused since commit 7b7d8b2d9a ("tcg/tci: Use ffi for calls").
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tci.c| 1 -
tcg/tci/tcg-target.c.inc | 4
2 files changed, 5 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index
From: Philippe Mathieu-Daudé
We are going to modify this code, so fix its style first to avoid:
ERROR: spaces required around that '*' (ctx:VxV)
#281: FILE: tcg/s390x/tcg-target.c.inc:1224:
+uintptr_t mask = ~(0xull << i*16);
^
From: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-Id: <2022074101.2069454-27-richard.hender...@linaro.org>
[PMD: Split from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20221122180804.938-3-phi...@linaro.org>
---
tcg/tcg.c | 83
From: Philippe Mathieu-Daudé
In the unlikely case of invalid typecode mask, the function
will abort instead of returning a NULL pointer.
Signed-off-by: Richard Henderson
Message-Id: <2022074101.2069454-27-richard.hender...@linaro.org>
[PMD: Split from bigger patch]
Signed-off-by: Philippe
Like CONFIG_TCG, the enabled method of execution is a host property
not a guest property. This exposes the define to compile-once files.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
meson.build | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git
Change 32-bit tci TCG_TARGET_CALL_ARG_I32 to TCG_CALL_ARG_EVEN, to
force 32-bit values to be aligned to 64-bit. With a small reorg
to the argument processing loop, this neatly replaces an ifdef for
CONFIG_TCG_INTERPRETER.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
We now check the consistency of reg_to_temp[] with each update,
so the utility of checking consistency at the end of each
opcode is minimal. In addition, the form of this check is
quite expensive, consuming 10% of a checking-enabled build.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 76
Allocate the first of a pair at the lower address, and the
second of a pair at the higher address. This will make it
easier to find the beginning of the larger memory block.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg-internal.h | 4 ++--
tcg/tcg.c
Remove whitespace at end of line, plus one place this also
highlights some missing braces.
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 33 +
tcg/ppc/tcg-target.c.inc | 2 +-
2 files changed, 18 insertions(+), 17 deletions(-)
diff --git
Create two new functions, set_temp_val_{reg,nonreg}.
Assert that the reg_to_temp mapping is correct before
any changes are made.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 159 +-
1 file changed, 85 insertions(+), 74 deletions(-)
diff
Add a helper function for computing the size of a type.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 16
tcg/tcg.c | 27 ---
2 files changed, 28 insertions(+), 15 deletions(-)
diff --git
Hi Julien,
From: Julien Grall
Date: Sunday, October 16, 2022 at 10:48 AM
To: Garhwal, Vikram , qemu-devel@nongnu.org
Cc: Stabellini, Stefano , Peter Maydell
, Stefano Stabellini ,
Anthony Perard , Paul Durrant , open
list:ARM TCG CPUs , open list:X86 Xen CPUs
Subject: Re: [PATCH v1 10/12]
From: Stefano Stabellini
In preparation to moving most of xen-hvm code to an arch-neutral location, move:
- shared_vmport_page
- log_for_dirtybit
- dirty_bitmap
- suspend
- wakeup
out of XenIOState struct as these are only used on x86, especially the ones
related to dirty logging.
Updated
Replace g_malloc with g_new and perror with error_setg_errno.
Signed-off-by: Vikram Garhwal
---
hw/xen/xen-hvm-common.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/hw/xen/xen-hvm-common.c b/hw/xen/xen-hvm-common.c
index 03128e575b..4ba5141fa2 100644
---
xen-mapcache.c contains common functions which can be used for enabling Xen on
aarch64 with IOREQ handling. Moving it out from hw/i386/xen to hw/xen to make it
accessible for both aarch64 and x86.
Signed-off-by: Vikram Garhwal
Signed-off-by: Stefano Stabellini
---
hw/i386/meson.build
In preparation to moving most of xen-hvm code to an arch-neutral location,
move non IOREQ references to:
- xen_get_vmport_regs_pfn
- xen_suspend_notifier
- xen_wakeup_notifier
- xen_ram_init
towards the end of the xen_hvm_init_pc() function.
This is done to keep the common ioreq functions in one
From: Stefano Stabellini
On ARM it is possible to have a functioning xenpv machine with only the
PV backends and no IOREQ server. If the IOREQ server creation fails continue
to the PV backends initialization.
Also, moved the IOREQ registration and mapping subroutine to new function
Add a new machine xenpv which creates a IOREQ server to register/connect with
Xen Hypervisor.
Optional: When CONFIG_TPM is enabled, it also creates a tpm-tis-device, adds a
TPM emulator and connects to swtpm running on host machine via chardev socket
and support TPM functionalities for a guest
From: Stefano Stabellini
have_xen_pci_passthrough is only used for Xen x86 VMs.
Signed-off-by: Stefano Stabellini
Reviewed-by: Alex Bennée
---
meson.build | 2 ++
1 file changed, 2 insertions(+)
diff --git a/meson.build b/meson.build
index 5c6b5a1c75..81d36420f0 100644
--- a/meson.build
+++
From: Stefano Stabellini
This patch does following:
1. creates arch_handle_ioreq() and arch_xen_set_memory(). This is done in
preparation for moving most of xen-hvm code to an arch-neutral location,
move the x86-specific portion of xen_set_memory to arch_xen_set_memory.
Also, move
xenstore_record_dm_state() will also be used in aarch64 xenpv machine.
Signed-off-by: Vikram Garhwal
Signed-off-by: Stefano Stabellini
---
accel/xen/xen-all.c | 2 +-
include/hw/xen/xen.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/accel/xen/xen-all.c
Add CONFIG_XEN for aarch64 device to support build for ARM targets.
Signed-off-by: Vikram Garhwal
Signed-off-by: Stefano Stabellini
Reviewed-by: Alex Bennée
---
meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index
From: Stefano Stabellini
This is done to prepare for enabling xenpv support for ARM architecture.
On ARM it is possible to have a functioning xenpv machine with only the
PV backends and no IOREQ server. If the IOREQ server creation fails,
continue to the PV backends initialization.
Hi Ard,
在 2022/12/1 19:07, Ard Biesheuvel 写道:
On Thu, 1 Dec 2022 at 09:07, Ard Biesheuvel wrote:
On Thu, 1 Dec 2022 at 08:15, chenxiang (M) wrote:
Hi Ard,
在 2022/11/30 16:18, Ard Biesheuvel 写道:
On Wed, 30 Nov 2022 at 08:53, Marc Zyngier wrote:
On Wed, 30 Nov 2022 02:52:35 +,
libvirt issue： https://gitlab.com/libvirt/libvirt/-/issues/261
1、start vm with usb cdrom
2、 get qemu cmdline
qemu ... -blockdev
{"driver":"file","filename":"/tmp/cdrom","node-name":"libvirt-1-storage","auto-read-only":true,"discard":"unmap"}
-blockdev
On Tue, Oct 25, 2022 at 8:18 AM Chao Peng wrote:
>
> From: "Kirill A. Shutemov"
>
> Introduce 'memfd_restricted' system call with the ability to create
> memory areas that are restricted from userspace access through ordinary
> MMU operations (e.g. read/write/mmap). The memory content is
The QEMU side calls kvm_get_msrs() to save the pmu registers from the KVM
side to QEMU, and calls kvm_put_msrs() to store the pmu registers back to
the KVM side.
However, only the Intel gp/fixed/global pmu registers are involved. There
is not any implementation for AMD pmu registers. The
This patchset is to fix two svm pmu virtualization bugs, x86 only.
version 1:
https://lore.kernel.org/all/20221119122901.2469-1-dongli.zh...@oracle.com/
1. The 1st bug is that "-cpu,-pmu" cannot disable svm pmu virtualization.
To use "-cpu EPYC" or "-cpu host,-pmu" cannot disable the pmu
On Thu, 2022-12-01 at 22:08 +0800, Bin Meng wrote:
> The pending register upper limit is currently set to
> plic->num_sources >> 3, which is wrong, e.g.: considering
> plic->num_sources is 7, the upper limit becomes 0 which fails
> the range check if reading the pending register at pending_base.
>
The "perf stat" at the VM side still works even we set "-cpu host,-pmu" in
the QEMU command line. That is, neither "-cpu host,-pmu" nor "-cpu EPYC"
could disable the pmu virtualization in an AMD environment.
We still see below at VM kernel side ...
[0.510611] Performance Events: Fam17h+ core
On Thu, 2022-12-01 at 22:08 +0800, Bin Meng wrote:
> "hartid-base" and "priority-base" are zero by default. There is no
> need to initialize them to zero again.
>
> Signed-off-by: Bin Meng
> ---
>
> hw/riscv/opentitan.c | 2 --
> 1 file changed, 2 deletions(-)
Reviewed-by: Wilfred Mallawa
>
On Thu, 2022-12-01 at 22:08 +0800, Bin Meng wrote:
> At present magic number is used to create "riscv,ndev" property
> in the dtb. Let's use the macro SIFIVE_U_PLIC_NUM_SOURCES that
> is used to instantiate the PLIC model instead.
>
> Signed-off-by: Bin Meng
> ---
>
> hw/riscv/sifive_u.c | 3
On Thu, 2022-12-01 at 22:08 +0800, Bin Meng wrote:
> Per chapter 10 in Freedom E310 manuals [1][2][3], E310 G002 and G003
> supports 52 interrupt sources while G000 supports 51 interrupt
> sources.
>
> We use the value of G002 and G003, so it is 53 (including source 0).
>
> [1] G000 manual:
>
On Thu, 2022-12-01 at 22:08 +0800, Bin Meng wrote:
> Per chapter 6.5.2 in [1], the number of interupt sources including
> interrupt source 0 should be 187.
>
> [1] PolarFire SoC MSS TRM:
>
On Thu, 2022-12-01 at 22:08 +0800, Bin Meng wrote:
> H-mode has been removed since priv spec 1.10. Drop it.
>
> Signed-off-by: Bin Meng
> ---
>
> include/hw/intc/sifive_plic.h | 1 -
> hw/intc/sifive_plic.c | 1 -
> 2 files changed, 2 deletions(-)
Reviewed-by: Wilfred Mallawa
>
>
On Thu, 2022-12-01 at 22:08 +0800, Bin Meng wrote:
> PLIC is not included in the 'spike' machine.
>
> Signed-off-by: Bin Meng
> ---
>
> hw/riscv/spike.c | 1 -
> 1 file changed, 1 deletion(-)
>
Reviewed-by: Wilfred Mallawa
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index
On Thu, 2022-12-01 at 22:07 +0800, Bin Meng wrote:
> Since commit ef6310064820 ("hw/riscv: opentitan: Update to the latest
> build")
> the IBEX PLIC model was replaced with the SiFive PLIC model in the
> 'opentitan' machine but we forgot the add the dependency there.
>
> Signed-off-by: Bin Meng
On Thu, Dec 01, 2022 at 12:21:21PM +, Alex Bennée wrote:
>
> "Michael S. Tsirkin" writes:
>
> > On Thu, Dec 01, 2022 at 10:14:39AM +, Alex Bennée wrote:
> >> Do you think rust-vmm's vhost crates have enough of the state
> >> management to manage vhost and vhost-user backends? Maybe it
On 12/1/22 10:44, Thomas Huth wrote:
The SET ADDRESS SPACE CONTROL FAST instruction is not privileged, it can be
used from problem space, too. Just the switching to the home address space
is privileged and should still generate a privilege exception. This bug is
e.g. causing programs like Java
On 12/1/22 11:13, Alex Bennée wrote:
I'm not sure I want to take this anymore. It's confusing to use. I
really think what I should do instead is improve the TCG register
allocator.
Whats the ultimate aim for the rewrite? Hold values in target registers
over the extended block? What about
Hi Paul,
From: Paul Durrant
Date: Wednesday, October 19, 2022 at 7:54 AM
To: Garhwal, Vikram , qemu-devel@nongnu.org
Cc: Stabellini, Stefano , Michael S. Tsirkin
, Marcel Apfelbaum , Paolo Bonzini
, Richard Henderson ,
Eduardo Habkost , Stefano Stabellini
, Anthony Perard , open
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