On 09/02/23 1:49 am, Eric Blake wrote:
On Wed, Feb 08, 2023 at 09:35:59AM +, Het Gala wrote:
'migrate-incoming' QAPI design have been modified into well-defined
MigrateChannel struct to prevent multiple encoding of uri strings on
the destination side.'uri' parameter is kept for backward
On 8/2/23 23:43, Titus Rwantare wrote:
The 8-bit expander has different register offsets than the 16-bit one,
making them incompatible.
Following extract/deposit API suggestion on previous patch, an
alternatively is to use PCAGPIOClass::input_port/output_port/...
offset fields.
On 09/02/23 1:47 am, Eric Blake wrote:
On Wed, Feb 08, 2023 at 09:35:56AM +, Het Gala wrote:
Existing 'migrate' QAPI design enforces transport mechanism, ip address
of destination interface and corresponding port number in the form
of a unified string 'uri' parameter for initiating a
On 07/02/2023 2:56, Juan Quintela wrote:
External email: Use caution opening links or attachments
We split the function into to:
- state_pending_estimate: We estimate the remaining state size without
stopping the machine.
- state pending_exact: We calculate the exact amount of remaining
Hi Titus,
On 8/2/23 23:43, Titus Rwantare wrote:
The PCA6416 is an i2c device with 16 GPIOs.
Reviewed-by: Hao Wu
Signed-off-by: Titus Rwantare
---
hw/arm/Kconfig | 1 +
hw/gpio/Kconfig | 4 +
hw/gpio/meson.build | 1 +
On Wed, Feb 08, 2023 at 04:12:51PM -0500, Michael S. Tsirkin wrote:
> This reverts commit eebb38a5633a77f5fa79d6486d5b2fcf8fbe3c07.
>
> Fixes: eebb38a563 ("x86: use typedef for SetupData struct")
> Signed-off-by: Michael S. Tsirkin
This one was actually good, I reverted so other reverts are
On Fri, Dec 02, 2022 at 02:13:40PM +0800,
Chao Peng wrote:
> +static int kvm_vm_ioctl_set_mem_attributes(struct kvm *kvm,
> +struct kvm_memory_attributes *attrs)
> +{
> + gfn_t start, end;
> + unsigned long i;
> + void *entry;
> + u64
On 8/2/23 23:40, Titus Rwantare wrote:
On Mon, 6 Feb 2023 at 13:38, Philippe Mathieu-Daudé wrote:
Hi Titus,
On 6/2/23 20:49, Titus Rwantare wrote:
This is a simple i2c device that allows i2c capable devices to have
GPIOs.
Reviewed-by: Hao Wu
Signed-off-by: Titus Rwantare
---
On 9/2/23 06:19, Thomas Huth wrote:
On 08/02/2023 18.19, Paolo Bonzini wrote:
The following changes since commit
ae2b5d8381a73b27f35f19c988d45c78bb4d5768:
Merge tag 'pull-include-2023-02-06-v2' of
https://repo.or.cz/qemu/armbru into staging (2023-02-08 10:40:06 +)
are available in
John Snow writes:
> On Wed, Feb 8, 2023 at 11:31 AM Markus Armbruster wrote:
>>
>> John Snow writes:
>>
>> > This is part five (c), and focuses on sharing strict types between
>> > parser.py and expr.py.
>> >
>> > gitlab: https://gitlab.com/jsnow/qemu/-/commits/python-qapi-cleanup-pt5c
>> >
>>
On 9/2/23 01:33, Alistair Francis wrote:
From: Alistair Francis
This patch adds some active RISC-V members as reviewers to the
MAINTAINERS file.
Signed-off-by: Alistair Francis
---
MAINTAINERS | 3 +++
1 file changed, 3 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
On 8/2/23 21:32, Maxime Coquelin wrote:
Maxime Coquelin (3):
docs: vhost-user: replace _SLAVE_ with _BACKEND_
libvhost-user: Adopt new backend naming
vhost-user: Adopt new backend naming
docs/interop/vhost-user.rst | 40 +++
hw/virtio/vhost-user.c
John Snow writes:
> The idea here is to combine 'TopLevelExpr' and 'ParsedExpression' into
> one type that accomplishes the purposes of both types;
>
> 1. TopLevelExpr is meant to represent a JSON Object, but only those that
> represent what qapi-schema calls a TOP-LEVEL-EXPR, i.e. definitions,
On 09/02/2023 8:03, Dov Murik wrote:
> Hi Michael,
>
> On 08/02/2023 23:12, Michael S. Tsirkin wrote:
>> All attempts to fix up passing RNG seed via setup_data entry failed.
>> Let's just rip out all of it. We'll start over.
>>
>>
>> Warning: all I did was git revert the relevant patches and
zisslpcfi protects forward control flow (if enabled) by enforcing all
indirect call and jmp must land on a landing pad instruction `lpcll`
short for landing pad and check lower label value. If target of an
indirect call or jmp is not `lpcll` then cpu/hart must raise an illegal
instruction
CSR_SSP and CSR_LPLR are new CSR additions to cpu/hart. This patch allows
access to these CSRs. A predicate routine handles access to these CSR as
per specification.
This patch also implments new bit definitions in menvcfg/henvcfg/mstatus/
sstatus CSRs to master enabled cfi and enable forward cfi
Implementation for forward cfi and backward cfi needs helper function
to determine if currently fcfi and bcfi are enabled. Enable depends on
privilege mode and settings in sstatus/menvcfg/henvcfg/mseccfg CSRs.
Signed-off-by: Deepak Gupta
Signed-off-by: Kip Walker
---
target/riscv/cpu.h
`zisslpcfi` extension adds two new CSRs. CSR_SSP and CSR_LPLR.
- CSR_SSP: This CSR holds shadow stack pointer for current privilege mode
CSR_SSP is accessible in all modes. Each mode must establish
it's own CSR_SSP.
- CSR_LPLR: This CSR holds label value set at the callsite
zisslpcfi protects returns(back cfi) using shadow stack. If compiled with
enabled compiler, function prologs will have `sspush ra` instruction to
push return address on shadow stack and function epilogs will have
`sspop t0; sschckra` instruction sequences. `sspop t0` will pop the
value from top of
Introducing riscv `zisslpcfi` extension to riscv target. `zisslpcfi`
extension provides hardware assistance to riscv hart to enable control
flow integrity (CFI) for software.
`zisslpcfi` extension expects hart to implement `zimops`. `zimops` stands
for "unprivileged integer maybe operations".
This patch adds support to disassemble Zisslpcfi instructions.
Signed-off-by: Deepak Gupta
Signed-off-by: Kip Walker
---
disas/riscv.c | 127 +-
1 file changed, 126 insertions(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index
This patch implements instruction encodings for zisslpcfi instructions.
Additionally this patch implements zimops encodings as well. If Zisslpcfi
is supported by CPU but not enabled then all Zisslpcfi instructions
default to Zimops instuction behavior i.e. mov 0 to rd.
zisslpcfi defines following
zisslpcfi's forward cfi if enabled on a hart, enables tracking of
indirect branches. CPU/hart internally keeps a state `elp` short
for expecting landing pad instruction. This state goes into
LP_EXPECTED on an indirect branch. But an interrupt/exception can occur
before target instruction is
Still learning to use git send-mail. Hopefully this time cover-letter
also reaches everyone.
I am sending this patch series as RFC for an extension which helps
software enforce control-flow integrity (cfi) on riscv CPUs. Currently
spec is called zisslpcfi spec -
CSR_SSP and CSR_LPLR are new CSR additions to cpu/hart. This patch allows
access to these CSRs. A predicate routine handles access to these CSR as
per specification.
This patch also implments new bit definitions in menvcfg/henvcfg/mstatus/
sstatus CSRs to master enabled cfi and enable forward cfi
zisslpcfi protects returns(back cfi) using shadow stack. If compiled with
enabled compiler, function prologs will have `sspush ra` instruction to
push return address on shadow stack and function epilogs will have
`sspop t0; sschckra` instruction sequences. `sspop t0` will pop the
value from top of
This patch implements instruction encodings for zisslpcfi instructions.
Additionally this patch implements zimops encodings as well. If Zisslpcfi
is supported by CPU but not enabled then all Zisslpcfi instructions
default to Zimops instuction behavior i.e. mov 0 to rd.
zisslpcfi defines following
zisslpcfi's forward cfi if enabled on a hart, enables tracking of
indirect branches. CPU/hart internally keeps a state `elp` short
for expecting landing pad instruction. This state goes into
LP_EXPECTED on an indirect branch. But an interrupt/exception can occur
before target instruction is
Introducing riscv `zisslpcfi` extension to riscv target. `zisslpcfi`
extension provides hardware assistance to riscv hart to enable control
flow integrity (CFI) for software.
`zisslpcfi` extension expects hart to implement `zimops`. `zimops` stands
for "unprivileged integer maybe operations".
`zisslpcfi` extension adds two new CSRs. CSR_SSP and CSR_LPLR.
- CSR_SSP: This CSR holds shadow stack pointer for current privilege mode
CSR_SSP is accessible in all modes. Each mode must establish
it's own CSR_SSP.
- CSR_LPLR: This CSR holds label value set at the callsite
zisslpcfi protects forward control flow (if enabled) by enforcing all
indirect call and jmp must land on a landing pad instruction `lpcll`
short for landing pad and check lower label value. If target of an
indirect call or jmp is not `lpcll` then cpu/hart must raise an illegal
instruction
Implementation for forward cfi and backward cfi needs helper function
to determine if currently fcfi and bcfi are enabled. Enable depends on
privilege mode and settings in sstatus/menvcfg/henvcfg/mseccfg CSRs.
Signed-off-by: Deepak Gupta
Signed-off-by: Kip Walker
---
target/riscv/cpu.h
This patch adds support to disassemble Zisslpcfi instructions.
Signed-off-by: Deepak Gupta
Signed-off-by: Kip Walker
---
disas/riscv.c | 127 +-
1 file changed, 126 insertions(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index
On 2/9/2023 1:59 PM, Xiaoyao Li wrote:
> On 2/9/2023 12:21 PM, Wang, Lei wrote:
>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>> index 88aa780566..e638a31d34 100644
>> --- a/target/i386/cpu.c
>> +++ b/target/i386/cpu.c
>> @@ -4377,6 +4377,28 @@ static bool
Hi Michael,
On 08/02/2023 23:12, Michael S. Tsirkin wrote:
> All attempts to fix up passing RNG seed via setup_data entry failed.
> Let's just rip out all of it. We'll start over.
>
>
> Warning: all I did was git revert the relevant patches and resolve the
> (trivial) conflicts. Not even
On 2/9/2023 12:21 PM, Wang, Lei wrote:
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 88aa780566..e638a31d34 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4377,6 +4377,28 @@ static bool x86_cpu_have_filtered_features(X86CPU *cpu)
return false;
}
+static void
When MSECCFG.MML is set, after checking the address range in PMP if the
asked permissions are not same as programmed in PMP, the default
permissions are applied. This should only be the case when there
is no matching address is found.
This patch skips applying default rules when matching address
On 08/02/2023 20.43, Philippe Mathieu-Daudé wrote:
On 8/2/23 20:26, Fabiano Rosas wrote:
We currently have a situation where disabling a Kconfig might result
in a runtime error when QEMU selects the corresponding device as a
default value for an option. But first a disambiguation:
Kconfig
On 08/02/2023 18.19, Paolo Bonzini wrote:
Test that it does not cause a SIGSEGV, and cover a valid configuration
as well.
Signed-off-by: Paolo Bonzini
---
tests/qtest/libqtest.c| 28 +-
tests/qtest/libqtest.h| 12 ++
tests/qtest/readconfig-test.c
On 08/02/2023 18.19, Paolo Bonzini wrote:
The following changes since commit ae2b5d8381a73b27f35f19c988d45c78bb4d5768:
Merge tag 'pull-include-2023-02-06-v2' of https://repo.or.cz/qemu/armbru
into staging (2023-02-08 10:40:06 +)
are available in the Git repository at:
On 08/02/2023 17.48, Andrea Bolognani wrote:
On Tue, Feb 07, 2023 at 08:20:31PM +0100, Andrew Jones wrote:
On Tue, Feb 07, 2023 at 06:38:15AM -0800, Andrea Bolognani wrote:
Well, it looks like -no-acpi will come for free after all, thanks to
the code you pasted above, as long as the machine
On 2023/2/9 08:33, Alistair Francis wrote:
From: Alistair Francis
This patch adds some active RISC-V members as reviewers to the
MAINTAINERS file.
Signed-off-by: Alistair Francis
---
MAINTAINERS | 3 +++
1 file changed, 3 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index
On 2/9/2023 11:29 AM, Xiaoyao Li wrote:
> On 2/9/2023 9:04 AM, Wang, Lei wrote:
>> On 2/6/2023 3:43 PM, Yuan Yao wrote:
>>> On Fri, Jan 06, 2023 at 12:38:24AM -0800, Lei Wang wrote:
Some feature words, e.g., feature words in AMX-related CPUID leaf 0x1D and
0x1E are not bit-wise but
Add encode, trans* functions for Zcmp instructions
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn16.decode| 18 +++
target/riscv/insn_trans/trans_rvzce.c.inc | 189
Separate c_fld/c_fsd from fld/fsd to add additional check for
c.fld{sp}/c.fsd{sp} which is useful for zcmp/zcmt to reuse
their encodings
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn16.decode
Add encode, trans* functions and helper functions support for Zcmt
instrutions
Add support for jvt csr
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h| 4 ++
This patchset implements RISC-V Zc* extension v1.0.2-1 version instructions.
Specification:
https://github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-zce-upstream-v11
To test Zc* implementation,
On Tue, 2022-11-29 at 15:50 -0500, Peter Xu wrote:
> On Tue, Nov 29, 2022 at 05:28:26PM -0300, Leonardo Bras Soares Passos wrote:
> > Hello Peter,
>
> Leo,
>
> >
> > On Thu, Nov 24, 2022 at 1:04 PM Peter Xu wrote:
> > >
> > > On Wed, Nov 09, 2022 at 02:56:29AM -0300, Leonardo Bras wrote:
> >
Expose zca,zcb,zcf,zcd,zcmp,zcmt properties
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 196473a60f..eb9e74ecd5 100644
Add encode and trans* functions support for Zcb instructions
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn16.decode| 23 +
target/riscv/insn_trans/trans_rvzce.c.inc | 100
Add properties for Zca,Zcb,Zcf,Zcd,Zcmp,Zcmt extension
Add check for these properties
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 43 +++
target/riscv/cpu.h
Separate c_flw/c_fsw from flw/fsw to add check for Zcf extension
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn16.decode | 8
target/riscv/insn_trans/trans_rvf.c.inc | 18
Modify the check for C extension to Zca (C implies Zca)
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Reviewed-by: Wilfred Mallawa
---
target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
target/riscv/translate.c
Zcmp/Zcmt instructions will override disasm for c.fld*/c.fsd*
instructions currently
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Acked-by: Alistair Francis
---
disas/riscv.c | 228 +-
1 file changed, 227 insertions(+), 1 deletion(-)
On Wed, Feb 8, 2023 at 4:32 PM wrote:
>
> From: Frank Chang
>
> The RVV specification does not require that the core needs to support
> the privileged specification v1.12.0 to support RVV, and there is no
> dependency from ISA level.
>
> This commit removes the restriction from both RVV CSRs and
On 2/9/2023 9:04 AM, Wang, Lei wrote:
On 2/6/2023 3:43 PM, Yuan Yao wrote:
On Fri, Jan 06, 2023 at 12:38:24AM -0800, Lei Wang wrote:
Some feature words, e.g., feature words in AMX-related CPUID leaf 0x1D and
0x1E are not bit-wise but multiple bits represents one value. Handle this
situation
On Tue, Feb 7, 2023 at 9:46 AM Dongli Zhang wrote:
>
> The cpu_dump_state() does not print the cpu index. When the
> cpu_dump_state() is invoked due to the KVM failure, we are not able to tell
> from which CPU the state is. The below is an example.
>
> KVM internal error. Suberror: 764064
>
On Tue, Feb 7, 2023 at 2:41 PM Bin Meng wrote:
>
> Upgrade OpenSBI from v1.1 to v1.2 and the pre-built bios images.
>
> The v1.2 release includes the following commits:
>
> 994c8cf lib: sbi_timer: Added a conditional wait function which can timeout
> caa5eea lib: sbi: add check for ipi device for
On Tue, Feb 7, 2023 at 2:41 PM Bin Meng wrote:
>
> Upgrade OpenSBI from v1.1 to v1.2 and the pre-built bios images.
>
> The v1.2 release includes the following commits:
>
> 994c8cf lib: sbi_timer: Added a conditional wait function which can timeout
> caa5eea lib: sbi: add check for ipi device for
Hi Juan,
>-Original Message-
>From: Juan Quintela
>Sent: Tuesday, February 7, 2023 8:57 AM
>To: qemu-devel@nongnu.org
>Cc: qemu-bl...@nongnu.org; Stefan Berger ;
>Stefan Hajnoczi ; Halil Pasic ;
>John Snow ; David Hildenbrand ;
>Fam Zheng ; Thomas Huth ; Daniel P.
>Berrangé ; Laurent
On Wed, 8 Feb 2023 at 18:02, Warner Losh wrote:
> On Fri, Jan 27, 2023 at 3:02 PM Stefan Hajnoczi wrote:
>>
>> On Fri, 27 Jan 2023 at 12:10, Warner Losh wrote:
>> >
>> > [[ cc list trimmed to just qemu-devel ]]
>> >
>> > On Fri, Jan 27, 2023 at 8:18 AM Stefan Hajnoczi wrote:
>> >>
>> >> Dear
On 2023/2/9 8:33, Alistair Francis wrote:
From: Alistair Francis
This patch adds some active RISC-V members as reviewers to the
MAINTAINERS file.
Signed-off-by: Alistair Francis
---
MAINTAINERS | 3 +++
1 file changed, 3 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index
Hi,
I saw a PoC:
https://lore.kernel.org/qemu-devel/20220525121422.3...@huawei.com/T/ to
implement memory pooling and fabric manager on qemu. Is there any further
development on this? Can qemu emulate a memory pooling on a simple case
that two virtual machines connected to a CXL switch where
On 2/6/2023 3:43 PM, Yuan Yao wrote:
> On Fri, Jan 06, 2023 at 12:38:24AM -0800, Lei Wang wrote:
>> Some feature words, e.g., feature words in AMX-related CPUID leaf 0x1D and
>> 0x1E are not bit-wise but multiple bits represents one value. Handle this
>> situation when the values specified are not
On Tue, Feb 7, 2023 at 12:03 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> In this new version patch 1 was changed to extract the lower 32 bits of
> the 64 bit address when running 32 bit CPUs. The difference now, in comparison
> with what was being done in version 6, is that now we're doing that
From: Alistair Francis
This patch adds some active RISC-V members as reviewers to the
MAINTAINERS file.
Signed-off-by: Alistair Francis
---
MAINTAINERS | 3 +++
1 file changed, 3 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 96e25f62ac..847bc7f131 100644
--- a/MAINTAINERS
+++
On Thu, Feb 2, 2023 at 2:54 PM Sunil V L wrote:
>
> RISC-V ACPI related functionality for virt machine is added in
> virt-acpi-build.c. Add the maintainer entry.
>
> Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
Alistair
> ---
> MAINTAINERS | 6 ++
> 1 file changed, 6
On Thu, Feb 2, 2023 at 2:54 PM Sunil V L wrote:
>
> Add Multiple APIC Description Table (MADT) with the
> INTC structure for each cpu.
>
> Signed-off-by: Sunil V L
Acked-by: Alistair Francis
Alistair
> ---
> hw/riscv/virt-acpi-build.c | 37 +
> 1 file
On Thu, Feb 2, 2023 at 2:54 PM Sunil V L wrote:
>
> memmap needs to be exported outside of virt.c so that
> modules like acpi can use it. Hence, add a pointer field
> in RiscVVirtState structure and initialize it with the
> memorymap.
>
> Signed-off-by: Sunil V L
Acked-by: Alistair Francis
On Thu, Feb 2, 2023 at 2:54 PM Sunil V L wrote:
>
> ACPI needs OEM_ID and OEM_TABLE_ID for the machine. Add these fields
> in the RISCVVirtState structure and initialize with default values.
>
> Signed-off-by: Sunil V L
Acked-by: Alistair Francis
Alistair
> ---
> hw/riscv/virt.c | 4
Nuvoton's PSPI is a general purpose SPI module which enables
connections to SPI-based peripheral devices.
Signed-off-by: Hao Wu
Reviewed-by: Chris Rauer
Reviewed-by: Philippe Mathieu-Daude
---
MAINTAINERS| 6 +-
hw/ssi/meson.build | 2 +-
hw/ssi/npcm_pspi.c
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Philippe Mathieu-Daude
---
docs/system/arm/nuvoton.rst | 2 +-
hw/arm/npcm7xx.c| 25 +++--
include/hw/arm/npcm7xx.h| 2 ++
3 files changed, 26 insertions(+), 3 deletions(-)
diff --git
Havard is no longer working on the Nuvoton systems for a while
and won't be able to do any work on it in the future. So I'll
take over maintaining the Nuvoton system from him.
Signed-off-by: Hao Wu
Acked-by: Havard Skinnemoen
Reviewed-by: Philippe Mathieu-Daude
---
MAINTAINERS | 2 +-
1 file
This patch set adds peripheral SPI (PSPI) modules
to NPCM7XX SoCs. These modules can be used to
connect any SPI peripheral devices to the SoC.
This module will also be used in the next generation
NPCM8XX SoCs which haven't been merged yet.
-- Changes from v2 --
Change max_access_size to 2 to
Thanks for pointing that out. I'll send another version to fix that.
On Tue, Feb 7, 2023 at 11:48 PM Philippe Mathieu-Daudé
wrote:
> On 7/2/23 20:45, Hao Wu wrote:
> > Nuvoton's PSPI is a general purpose SPI module which enables
> > connections to SPI-based peripheral devices.
> >
> >
QEMU configure script goes into an infinite error printing loop
when in read only directory due to 'build' dir never being created.
Checking if 'mkdir dir' succeeds prevents this error.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/321
---
configure | 15 ++-
1 file
Always initialize --help display option
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/321
---
configure | 676 +++---
1 file changed, 338 insertions(+), 338 deletions(-)
diff --git a/configure b/configure
index 3b384914ce..1fb4d145f1
QEMU configure script goes into an infinite error printing loop
when in read only directory due to 'build' dir never being created.
1 - Checking if 'mkdir dir' succeeds and if the directory is
writeable prevents this error.
2 - Since we exit early on error in (1), code for reading in
arguments
On Tue, Feb 7, 2023 at 8:56 AM Markus Armbruster wrote:
> Peter Maydell writes:
>
> > The command line option '-singlestep' and its HMP equivalent
> > the 'singlestep' command are very confusingly named, because
> > they have nothing to do with single-stepping the guest (either
> > via the gdb
On Fri, Jan 27, 2023 at 3:02 PM Stefan Hajnoczi wrote:
> On Fri, 27 Jan 2023 at 12:10, Warner Losh wrote:
> >
> > [[ cc list trimmed to just qemu-devel ]]
> >
> > On Fri, Jan 27, 2023 at 8:18 AM Stefan Hajnoczi
> wrote:
> >>
> >> Dear QEMU, KVM, and rust-vmm communities,
> >> QEMU will apply
The PCA6416 is an i2c device with 16 GPIOs.
Reviewed-by: Hao Wu
Signed-off-by: Titus Rwantare
---
hw/arm/Kconfig | 1 +
hw/gpio/Kconfig | 4 +
hw/gpio/meson.build | 1 +
hw/gpio/pca_i2c_gpio.c | 388
This device has the same register layout as the pca9538, but 4 fewer
gpio pins. This commit lowers the number of pins initialised, and reuses
the pca9538 logic.
Reviewed-by: Hao Wu
Signed-off-by: Titus Rwantare
---
hw/gpio/pca_i2c_gpio.c | 18 ++
The 8-bit expander has different register offsets than the 16-bit one,
making them incompatible.
Reviewed-by: Hao Wu
Signed-off-by: Titus Rwantare
---
hw/gpio/pca_i2c_gpio.c | 94 ++
include/hw/gpio/pca_i2c_gpio.h | 7 +++
2 files changed, 101
This patch series contains a set of i2c GPIO expanders,
with support for 4, 8, and 16 GPIO connections.
The devices are configured as GPIO *inputs by default, but can have pins
configured to be inputs with qmp commands.
For example, the following snippet in a board file for a system,
configures
Signed-off-by: Titus Rwantare
---
hw/i2c/core.c | 8 +---
hw/i2c/trace-events | 2 +-
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
index d4ba8146bf..c583c1497a 100644
--- a/hw/i2c/core.c
+++ b/hw/i2c/core.c
@@ -161,7 +161,8 @@ static int
On Mon, 6 Feb 2023 at 14:27, Corey Minyard wrote:
>
> On Mon, Feb 06, 2023 at 07:49:34PM +, Titus Rwantare wrote:
> > This is a simple i2c device that allows i2c capable devices to have
> > GPIOs.
> >
> > Reviewed-by: Hao Wu
> > Signed-off-by: Titus Rwantare
> > ---
> > hw/arm/Kconfig
On Mon, 6 Feb 2023 at 13:38, Philippe Mathieu-Daudé wrote:
>
> Hi Titus,
>
> On 6/2/23 20:49, Titus Rwantare wrote:
> > This is a simple i2c device that allows i2c capable devices to have
> > GPIOs.
> >
> > Reviewed-by: Hao Wu
> > Signed-off-by: Titus Rwantare
> > ---
> > hw/arm/Kconfig
On Mon, 6 Feb 2023 at 17:29, Dong, Eddie wrote:
> > -Original Message-
> > From: qemu-devel-bounces+eddie.dong=intel@nongnu.org > devel-bounces+eddie.dong=intel@nongnu.org> On Behalf Of Titus
> > Rwantare
> > Sent: Monday, February 6, 2023 11:50 AM
> > To:
On Mon, 6 Feb 2023 at 19:43, Joel Stanley wrote:
>
> On Mon, 6 Feb 2023 at 19:51, Titus Rwantare wrote:
> >
> > This is a simple i2c device that allows i2c capable devices to have
> > GPIOs.
>
> Nice.
>
> In Linux this is supported by a driver called pca953x. Would it make
> sense to name your
Gavin Shan wrote:
> arm64 has different capability from x86 to enable the dirty ring, which
> is KVM_CAP_DIRTY_LOG_RING_ACQ_REL. To enable it in kvm_dirty_ring_init()
> when KVM_CAP_DIRTY_LOG_RING isn't supported.
>
> Signed-off-by: Gavin Shan
Reviewed-by: Juan Quintela
Gavin Shan wrote:
> When KVM device "kvm-arm-gicv3" or "arm-its-kvm" is used, we have to
> enable the backup bitmap for the dirty ring. Otherwise, the migration
> will fail because those two devices are using the backup bitmap to track
> dirty guest memory, corresponding to various hardware
On 2/7/23 05:05, Peter Maydell wrote:
On Tue, 24 Jan 2023 at 00:01, Richard Henderson
wrote:
We will need 2 bits to represent ARMSecurityState.
Do not attempt to replace or widen secure, even though it
logically overlaps the new field -- there are uses within
e.g. hw/block/pflash_cfi01.c,
Gavin Shan wrote:
> Due to multiple capabilities associated with the dirty ring for different
> architectures: KVM_CAP_DIRTY_{LOG_RING, LOG_RING_ACQ_REL} for x86 and
> arm64 separately. There will be more to be done in order to support the
> dirty ring for arm64.
>
> Lets add helper
Gavin Shan wrote:
> When dirty ring is enabled on ARM64, the backup bitmap may be used
> to track the dirty pages in no-running-vcpu situations. The original
> bitmap is the primary one, used for the dirty ring buffer. We need
> the secondary bitmap to collect the backup bitmap for ARM64.
>
> No
On 2/7/23 05:00, Peter Maydell wrote:
static inline bool arm_is_secure(CPUARMState *env)
{
-if (arm_is_el3_or_mon(env)) {
-return true;
-}
-return arm_is_secure_below_el3(env);
+ARMSecuritySpace ss = arm_security_space(env);
+return ss == ARMSS_Secure || ss ==
On 2/7/23 04:53, Peter Maydell wrote:
On Tue, 24 Jan 2023 at 00:01, Richard Henderson
wrote:
This includes GPCCR, GPTBR, MFAR, the TLB flush insns PAALL,
PAALLOS, RPALOS, RPAOS, and the cache flush insn CIPAPA.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 19
On Wed, 8 Feb 2023 06:38:30 +
John Johnson wrote:
> > On Feb 6, 2023, at 12:33 PM, Alex Williamson
> > wrote:
> >
> > On Wed, 1 Feb 2023 21:55:51 -0800
> > John Johnson wrote:
> >
> >> Server holds device current device pending state
> >> Use irq masking commands in socket case
> >>
On 2/7/23 00:43, Anton Johansson wrote:
Signed-off-by: Anton Johansson
---
target/arm/cpu-param.h | 2 --
target/arm/cpu.c| 5 +
target/i386/cpu-param.h | 4
target/i386/cpu.c | 5 +
4 files changed, 10 insertions(+), 6 deletions(-)
diff --git
On 2/7/23 00:43, Anton Johansson wrote:
diff --git a/accel/tcg/tb-jmp-cache.h b/accel/tcg/tb-jmp-cache.h
index b3f6e78835..083939b302 100644
--- a/accel/tcg/tb-jmp-cache.h
+++ b/accel/tcg/tb-jmp-cache.h
static inline TranslationBlock *
-tb_jmp_cache_get_tb(CPUJumpCache *jc, uint32_t hash)
This reverts commit eebb38a5633a77f5fa79d6486d5b2fcf8fbe3c07.
Fixes: eebb38a563 ("x86: use typedef for SetupData struct")
Signed-off-by: Michael S. Tsirkin
---
hw/i386/x86.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index
1 - 100 of 354 matches
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