On Wed, Sep 20, 2023 at 6:39 AM Andreas K. Huettel wrote:
>
> Hi Alistair,
>
> > It would be great to get a strace of the failure to narrow down what
> > it is. From there it should be not too hard to find and fix.
>
> thanks a lot. Here's as much info as I could get wi
On Wed, Jun 5, 2024 at 4:35 PM wrote:
>
> From: Frank Chang
>
> Add standard extension implied rules to enable the implied extensions of
> the standard extension recursively.
>
> Signed-off-by: Frank Chang
Acked-by: Alistair Francis
Alistair
> ---
>
On Wed, Jun 5, 2024 at 4:34 PM wrote:
>
> From: Frank Chang
>
> Add MISA extension implied rules to enable the implied extensions
> of MISA recursively.
>
> Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Alistair
> ---
&g
> +typedef struct riscv_cpu_implied_exts_rule RISCVCPUImpliedExtsRule;
> +
> +struct riscv_cpu_implied_exts_rule {
> +/* Bitmask indicates the rule enabled status for the harts. */
> +uint64_t enabled;
I'm not clear why we need this
Alistair
> +/* True if this is a
On Tue, Jun 11, 2024 at 5:16 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 6/10/24 3:32 PM, Andrew Jones wrote:
> > On June 10, 2024 2:34:58 AM GMT+02:00, Alistair Francis
> > wrote:
> >> On Fri, May 24, 2024 at 3:43 AM Daniel Henrique Barboza
> >> wrot
hilippe Mathieu-Daudé
> Reviewed-by: Anton Johansson
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/Kconfig | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/Kconfig b/target/riscv/Kconfig
> index 5f30df22f2..c332616d36 1
t would probably be helpful to document these somewhere, so others
can use them as a starting point for running this
Alistair
>
> The Linux kernel used for tests can be found here:
>
> https://github.com/tjeznach/linux/tree/riscv_iommu_v6-rc3
>
> This is a newer version of the foll
eption codes for sw-check and hw-err
> target/riscv: Support the version for ss1p13
>
> Jim Shu (1):
> target/riscv: Reuse the conversion function of priv_spec
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> target/riscv/cpu.c | 8 ++--
> tar
On Thu, Jun 6, 2024 at 11:51 PM Fea.Wang wrote:
>
> Add RISC-V privilege 1.13 support.
>
> Signed-off-by: Fea.Wang
> Signed-off-by: Fea.Wang
> Reviewed-by: Frank Chang
> Reviewed-by: Weiwei Li
> Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Alistair
>
Du (3):
> target/riscv/kvm: add software breakpoints support
> target/riscv/kvm: handle the exit with debug reason
> target/riscv/kvm: define TARGET_KVM_HAVE_GUEST_DEBUG
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> configs/targets/riscv64-softmmu.mak | 1 +
> target/riscv/kvm/kvm-cpu.c | 89 +
> 2 files changed, 90 insertions(+)
>
> --
> 2.17.1
>
On Tue, Jun 4, 2024 at 4:24 PM Fea.Wang wrote:
>
> Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in
> mstateen0 that controls access to the hedeleg.
>
> Signed-off-by: Fea.Wang
> Reviewed-by: Frank Chang
> Reviewed-by: Weiwei Li
Reviewed-by: Alista
The idea is that we add
support and then let users enable it.
Alistair
> ---
> target/riscv/cpu.c | 6 +-
> target/riscv/tcg/tcg-cpu.c | 4
> 2 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index e9e69
On Tue, Jun 4, 2024 at 4:23 PM Fea.Wang wrote:
>
> Add macros and variables for RISC-V privilege 1.13 support.
>
> Signed-off-by: Fea.Wang
> Reviewed-by: Frank Chang
> Reviewed-by: Weiwei Li
> Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Alistair
> -
HW breakpoints support
> 2. A 'corner case' in which the debug exception is not inserted by the
> debugger, need to be re-injected to the guest.
>
> v2 resend->v3:
> - rebased.
I think you rebased on the wrong tree. Do you mind rebasing on
https://github.com/alistair23/qemu/tree/riscv-
On Thu, May 30, 2024 at 2:12 AM Rajnesh Kanwal wrote:
>
> Signed-off-by: Rajnesh Kanwal
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/insn32.decode | 1 -
> target/riscv/insn_trans/trans_privileged.c.inc | 5 -
> 2 files changed, 6 del
thon3-devel)
>
> - I used the generated file
> 'Documentation/devicetree/bindings/processed-schema.json'
> as a 'processed schema'.
>
> Series applicable on both master and alistair/riscv-to-apply.next.
>
> Changes from v1:
> - added patches 2 to 7 to fix the
> Fixes: 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt
> machine")
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/riscv/virt.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
>
Fixes: 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt
> machine")
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/riscv/virt.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/riscv/
t-controller/riscv,imsics.yaml
>
> Reported-by: Conor Dooley
> Fixes: 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt
> machine")
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/riscv/virt.c | 3 +
> Fixes: e6faee65855b ("hw/riscv: virt: Add optional AIA APLIC support to virt
> machine")
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/riscv/virt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>
Fixes: e6faee65855b ("hw/riscv: virt: Add optional AIA APLIC support to virt
> machine")
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/riscv/virt.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
>
rted-by: Conor Dooley
> Fixes: e6faee65855b ("hw/riscv: virt: Add optional AIA APLIC support to virt
> machine")
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/riscv/virt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deleti
, move 'aplic_name'
> inside the conditional to avoid allocating a string that won't be used
> when socket == NULL.
>
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/riscv/virt.c | 13 -
> 1 file changed, 8 insertions(+), 5
virt: Add optional AIA APLIC support to virt
> machine")
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/riscv/virt.c | 2 ++
> include/hw/riscv/virt.h | 1 +
> 2 files changed, 3 insertions(+)
>
> diff --git
On Tue, May 28, 2024 at 6:12 PM Chao Du wrote:
>
> To enable the KVM GUEST DEBUG for RISC-V at QEMU side.
>
> Signed-off-by: Chao Du
> Reviewed-by: Daniel Henrique Barboza
> Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
Alistair
> ---
> configs/targets
On Tue, May 28, 2024 at 6:12 PM Chao Du wrote:
>
> If the breakpoint belongs to the userspace then set the ret value.
>
> Signed-off-by: Chao Du
> Reviewed-by: Daniel Henrique Barboza
> Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
Alistair
> ---
> target/
gle-step debugging.
>
> Implement kvm_arch_update_guest_debug(): Set the control flag
> when there are active breakpoints. This will help KVM to know
> the status in the userspace.
>
> Add some stubs which are necessary for building, and will be
> implemented later.
>
> Signed
On Tue, May 28, 2024 at 5:32 PM Sunil V L wrote:
>
> RISC-V is going to use new HID RSCV0003 for generi UART. So, update the
> HID.
>
> Signed-off-by: Sunil V L
Acked-by: Alistair Francis
Alistair
> ---
> hw/riscv/virt-acpi-build.c | 2 +-
> 1 file changed, 1
On Tue, May 28, 2024 at 5:32 PM Sunil V L wrote:
>
> PLIC and APLIC should be in namespace as well. So, add them using the
> defined HID.
>
> Signed-off-by: Sunil V L
Acked-by: Alistair Francis
Alistair
> ---
> hw/riscv/virt-acpi-build.c | 47 +++
r. This matches the example given in the ACPI specification section
> 6.2.13.1 as well.
>
> Enable creating link devices outside the scope of PCI root complex based
> on the flag which gets set currently only for RISC-V.
>
> Signed-off-by: Sunil V L
Acked-by: Alistair Francis
Al
/riscv: Apply modularized matching conditions for icount trigger
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> target/riscv/debug.c | 129 ---
> 1 file changed, 85 insertions(+), 44 deletions(-)
>
> --
> 2.34.1
>
>
On Mon, Jun 3, 2024 at 4:00 PM Yuming Yu-Ming Chang(張育銘)
wrote:
>
> Hi Alistair,
>
> I think we need the following patch to fix this issue:
I have dropped the original patch from my tree. Please fix the issue
and send a new patch with the fix incorporated.
Alista
iscv-crypto-vector-zvkb.adoc?plain=1#L10
>
> Signed-off-by: Jerry Zhang Jian
When sending a new version can you please include all previous tags
(unless there are major changes)
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/tcg/tcg-cpu.c | 4
> 1 file change
st.
>
> As part of this effort, it is found that uefi-test-tools is currently
> broken to build. So, updated its Makefile as well to use python based
> edk2 build script.
It would be great to get someone who knows the UEFI world better than I
do to ack these changes, especially the first few pa
ese are all new files being added for the first time. Hence, iASL diff
> output is not added.
>
> Signed-off-by: Sunil V L
Acked-by: Alistair Francis
Alistair
> ---
> tests/data/acpi/virt/riscv64/APIC | Bin 0 -> 116 bytes
> tests/data/acpi/virt/riscv64/DSDT
On Fri, May 24, 2024 at 4:15 PM Sunil V L wrote:
>
> Add basic ACPI table test case for RISC-V.
>
> Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
Alistair
> ---
> tests/qtest/bios-tables-test.c | 27 +++
> 1 file changed, 27 inserti
On Fri, May 24, 2024 at 4:15 PM Sunil V L wrote:
>
> As per process documented (steps 1-3) in bios-tables-test.c, add empty
> AML data files for RISC-V ACPI tables and add the entries in
> bios-tables-test-allowed-diff.h.
>
> Signed-off-by: Sunil V L
Acked-by: Alistair
On Fri, May 24, 2024 at 4:14 PM Sunil V L wrote:
>
> Enable building the test application for RISC-V with appropriate
> dependencies updated.
>
> Signed-off-by: Sunil V L
> Acked-by: Gerd Hoffmann
Acked-by: Alistair Francis
Alistair
> ---
> tests/uefi-tes
On Thu, May 23, 2024 at 10:46 PM LIU Zhiwei
wrote:
>
> Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Alistair
> ---
> disas/riscv.c | 60 +++
> 1 file changed, 60 insertions(+)
>
> diff --git a/disas/riscv.c b/
On Thu, May 23, 2024 at 10:44 PM LIU Zhiwei
wrote:
>
> Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/insn32.decode | 2 ++
> target/riscv/insn_trans/trans_rvzabha.c.inc | 14 ++
> 2 files chan
On Thu, May 23, 2024 at 10:44 PM LIU Zhiwei
wrote:
>
> Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/insn_trans/trans_rvzacas.c.inc | 13 -
> target/riscv/translate.c| 13 +
> 2 files chan
On Thu, May 23, 2024 at 10:44 PM LIU Zhiwei
wrote:
>
> Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu_cfg.h | 1 +
> target/riscv/insn32.decode | 20 +++
> target/riscv/insn_trans/trans_r
On Thu, May 23, 2024 at 10:43 PM LIU Zhiwei
wrote:
>
> Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/insn_trans/trans_rva.c.inc | 21 -
> target/riscv/translate.c| 21 +
> 2
an be redefined by later extension.
>
> Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Alistair
> ---
> disas/riscv.c | 23 +++
> 1 file changed, 23 insertions(+)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 4cd769f165..41050246f3 100
fined in the Zimop extension, the C.MOP.n instructions
> are defined to not write any register.
>
> In current implementation, C.MOP.n only has an check function, without any
> other more behavior.
>
> Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
A
On Wed, May 22, 2024 at 4:32 PM LIU Zhiwei wrote:
>
> Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Alistair
> ---
> disas/riscv.c | 100 ++
> 1 file changed, 100 insertions(+)
>
> diff --git a/disas/riscv.c b/
tructions named MOP.RR.n, where n
> is an integer between 0 and 7.
>
> These 40 MOPs initially are defined to simply write zero to x[rd],
> but are designed to be redefined by later extensions to perform some
> other action.
>
> Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair
t go through riscv_cpu_set_irq()
> path, it's better to keep local and guest range separate to avoid
> confusion and any future issues.
>
> Patches can be found here on github [0] and v1 of the series
> can be found here [1].
>
> Patches are based on alistair/riscv-to-apply.next.
On Thu, Mar 7, 2024 at 12:36 PM Alvin Che-Chia Chang(張哲嘉)
wrote:
>
> Hi Alistair,
>
> Please also take a look at this series, I guess it is ready to be applied,
> thanks!
This is all acked now, do you mind rebasing on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next an
ot;)
> Fixes: 40336d5b1d ("target/riscv: Add HS-mode virtual interrupt and IRQ
> filtering support.")
>
> Signed-off-by: Rajnesh Kanwal
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu_bits.h | 3 ++-
> target/riscv/csr.c | 9 -
> 2 fi
he width of the masks.
>
> Fixes: 1697837ed9 ("target/riscv: Add M-mode virtual interrupt and IRQ
> filtering support.")
> Fixes: 40336d5b1d ("target/riscv: Add HS-mode virtual interrupt and IRQ
> filtering support.")
>
> Signed-off-by: Rajnesh Kanwal
>
ed only by setting
> hvictl.IID = 9. Software might want to use the pair IID = 9, IPRIO = 0
> generally to represent
> no interrupt in hvictl.
>
> (See riscv-interrupts-1.0: Interrupts at VS level)
>
> Signed-off-by: Irina Ryapolova
Acked-by: Alistair Francis
Ali
ster/riscv-asm.md
It might be worth for each dot point to point directly to the
reference on why we should change it. Also I don't think it is trivial
in the sense that it should go via the qemu-trivial tree.
Alistair
>
> Signed-off-by: Simeo
On Tue, Jun 4, 2024 at 10:46 AM Alistair Francis wrote:
>
> On Wed, May 15, 2024 at 6:02 PM Fea.Wang wrote:
> >
> > Add RISC-V privilege 1.13 support.
> >
> > Signed-off-by: Fea.Wang
> > Reviewed-by: Frank Chang
> > Reviewed-by: Weiwei Li
On Wed, May 15, 2024 at 6:01 PM Fea.Wang wrote:
>
> Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in
> SMSTATEEN0 that controls access to the hedeleg.
I don't see this in the spec. I only see P1P13 in mstateen0
Alistair
>
> Signed-off-by: Fea.Wang
>
st reading zero and writing ignore. Besides, for accessing HEDELEGH, it
> should be controlled by mstateen0 'P1P13' bit.
>
> Signed-off-by: Fea.Wang
> Reviewed-by: Frank Chang
> Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu_bits.h |
On Wed, May 15, 2024 at 6:02 PM Fea.Wang wrote:
>
> Based on the priv-1.13.0, add the exception codes for Software-check and
> Hardware-error.
>
> Signed-off-by: Fea.Wang
> Reviewed-by: Frank Chang
> Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Alistair
On Wed, May 15, 2024 at 6:02 PM Fea.Wang wrote:
>
> Add RISC-V privilege 1.13 support.
>
> Signed-off-by: Fea.Wang
> Reviewed-by: Frank Chang
> Reviewed-by: Weiwei Li
> Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c
On Wed, May 15, 2024 at 6:03 PM Fea.Wang wrote:
>
> From: Jim Shu
>
> Public the conversion function of priv_spec in cpu.h, so that tcg-cpu.c
> could also use it.
>
> Signed-off-by: Jim Shu
> Signed-off-by: Fea.Wang
> Reviewed-by: Frank Chang
> Reviewed-by: LIU
rivilege level.
>
> [1]: https://github.com/riscv/riscv-debug-spec/releases/tag/task_group_vote
> [2]: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0.0-rc1-asciidoc
>
> Signed-off-by: Alvin Chang
Reviewed-by: Alistair Francis
type 3 triggers.
>
> Signed-off-by: Alvin Chang
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/debug.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/debug.c b/target/riscv/debug.c
> index 9f9f332019..eb45e2c147 1006
urn false to stop the loop.
> Now we keep looping all the triggers until we find a matched trigger.
>
> Only load/store bits and loaded/stored address should be further checked
> in riscv_cpu_debug_check_watchpoint().
>
> Signed-off-by: Alvin Chang
Acked-by: Alistair Fra
On Wed, May 29, 2024 at 2:56 PM Philippe Mathieu-Daudé
wrote:
>
> ping?
I originally missed this patch somehow and it has then been fixed
separately as part of
https://patchew.org/QEMU/20240514023910.301766-1-alistair.fran...@wdc.com/
Alistair
>
> On 19/4/24 13:05, Philippe Mathieu
8-phi...@linaro.org>
> [rth: Use g_strdup_printf]
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/riscv/virt.c | 17 +
> 1 file changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt
On Fri, Apr 12, 2024 at 5:37 PM Richard Henderson
wrote:
>
> Allocate and fill a GString instead of snprintf and
> appending to a fixed sized buffer.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
>
of such case.
Signed-off-by: Huang Tao
Suggested-by: Richard Henderson
Reviewed-by: LIU Zhiwei
Cc: qemu-stable
Message-ID: <20240325021654.6594-1-eric.hu...@linux.alibaba.com>
Signed-off-by: Alistair Francis
---
target/riscv/vector_internals.c | 22 ++
1 file chang
wed-by: Andrew Jones
Reviewed-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwei
Message-ID: <20240514110217.22516-1-rbradf...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 2 +-
target/riscv/tcg/tcg-cpu.c | 2 +-
2 files c
From: Max Chou
The opfv_narrow_check needs to check the single width float operator by
require_rvf.
Signed-off-by: Max Chou
Reviewed-by: Daniel Henrique Barboza
Cc: qemu-stable
Message-ID: <20240322092600.1198921-4-max.c...@sifive.com>
Signed-off-by: Alistair Francis
---
target
: <20240422171425.333037-2-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis
---
target/riscv/kvm/kvm-cpu.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index d2491d84e2..473416649f
LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Max Chou
Reviewed-by: Weiwei Li
Message-ID:
Cc: qemu-stable
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a74f0eb29c..
From: Alistair Francis
When running the instruction
```
cbo.flush 0(x0)
```
QEMU would segfault.
The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
allocated.
In order to fix this let's use the existing get_address()
helper. This also has the benefit of performing poin
est
physical address that faulted, shifted by 2 bits. *For other traps, mtval2
is set to zero...*
Signed-off-by: Alexei Filippov
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20240503103052.6819-1-alexei.filip...@syntacore.com>
Cc: qemu-stable
Signed-off-by:
integer to double width float, so the opfxv_widen_check function doesn’t
need require_rvf for the single width operator(integer).
Signed-off-by: Max Chou
Reviewed-by: Daniel Henrique Barboza
Cc: qemu-stable
Message-ID: <20240322092600.1198921-3-max.c...@sifive.com>
Signed-off-by: Alistair F
is
implementation-specific.
Signed-off-by: Andrew Jones
Reviewed-by: Christoph Müllner
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20240424142808.62936-2-ajo...@ventanamicro.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h
Odaki
Cc: Alex Bennée
Reported-by: Robin Dapp
Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwei
Acked-by: Alex Bennée
Reviewed-by: Akihiko Odaki
Reviewed-by: Alistair Francis
Cc: qem
-by: Max Chou
Reviewed-by: Daniel Henrique Barboza
Cc: qemu-stable
Message-ID: <20240322092600.1198921-2-max.c...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff
Message-ID: <20240322092600.1198921-5-max.c...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 16
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv
81366-1-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis
---
target/riscv/sbi_ecall_interface.h | 17 +
target/riscv/kvm/kvm-cpu.c | 111 +
2 files changed, 128 insertions(+)
diff --git a/target/riscv/sbi_ecall_interface.h
-by: Yong-Xuan Wang
Reviewed-by: Andrew Jones
Cc: qemu-stable
Message-ID: <20240515091129.28116-1-yongxuan.w...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/kvm/kvm-cpu.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/riscv/kvm/kvm-c
-devel/2024-02/msg00775.html
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Christoph Müllner
Message-ID: <20240429073656.2486732-1-christoph.muell...@vrull.eu>
Signed-off-by: Alistair Francis
---
MAINTAINERS | 1 +
target/riscv/cpu.h | 3 ++
target
-by: Jason Chien
Reviewed-by: Frank Chang
Reviewed-by: Max Chou
Message-ID: <20240328022343.6871-4-jason.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/gdbstub.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/gdbstub.c b/target
-by: Daniel Henrique Barboza
Message-ID: <20240328022343.6871-3-jason.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu_cfg.h | 1 +
target/riscv/cpu.c | 2 ++
target/riscv/tcg/tcg-cpu.c | 17 +++--
3 files changed, 14 insertions(+), 6 del
aise_mmu_exception() to prioritize it.
Reported-by: Joseph Chan
Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU
translation stage")
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20240413105929.7030-1-alexei.filip...
From: Alistair Francis
Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
CSRs are part of the disassembly.
Reported-by: Eric DeVolder
Signed-off-by: Alistair Francis
Fixes: ea10325917 ("R
ng ebreaks.
Write 'badaddr' in all ebreak breakpoints to write the appropriate
'tval' during riscv_do_cpu_interrrupt().
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Message-ID: <20240416230437.1869024-3-dbarb...@ven
-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-ID: <20240506023607.29544-1-eric.hu...@linux.alibaba.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 1 +
target/riscv/tcg/tcg-cpu.h | 15 +++
target/riscv/cpu.c
by: Daniel Henrique Barboza
Cc: qemu-stable
Message-ID: <20240422134605.534207-2-ajo...@ventanamicro.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 3 +++
target/riscv/csr.c | 18 ++
target/riscv/kvm/kvm-cpu.c | 25 +
3 f
ts into env->badaddr, which is
used as as scratch area for traps with address information. 'tval' is
then set during riscv_cpu_do_interrupt().
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by: LIU Zhiwei
Message-ID: <20240416230437.1869024-2-dbarb...@ve
.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu_cfg.h | 1 +
target/riscv/cpu.c | 2 ++
target/riscv/cpu_helper.c | 2 +-
target/riscv/csr.c | 2 +-
target/riscv/tcg/tcg-cpu.c
: <20240409014445.278-1-gaoshanliu...@163.com>
Signed-off-by: Alistair Francis
---
hw/intc/riscv_aplic.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index fc5df0d598..32edd6d07b 100644
--- a/hw/intc/riscv_aplic.
---
Alexei Filippov (1):
target/riscv: do not set mtval2 for non guest-page faults
Alistair Francis (2):
target/riscv: rvzicbo: Fixup CBO extension register calculation
disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
Andrew Jones (2):
target/riscv/kvm: Fix expos
to 63
which belongs to the range [48-63] in order to avoid any future
collisions with reserved exception.
Signed-off-by: Clément Léger
Reviewed-by: Alistair Francis
Message-ID: <20240422135840.1959967-1-cle...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu_bits.h | 2
From: Cheng Yang
Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
to set the address of initrd in FDT to support 64-bit address.
Signed-off-by: Cheng Yang
Reviewed-by: Alistair Francis
Message-ID:
Signed-off-by: Alistair Francis
---
hw/riscv/boot.c | 4 ++--
1 file changed, 2
f why it isn't working. I suspect you need to ignore the
checks for debug accesses
Alistair
> ---
> Hi maintainers,
> Do I need to make any further improvements to this patch?
>
> Best regards,
> Yuming
>
> target/riscv/cpu.h | 4
> target/riscv/csr.
Odaki
Cc: Alex Bennée
Reported-by: Robin Dapp
Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwei
Acked-by: Alex Bennée
Reviewed-by: Akihiko Odaki
Reviewed-by: Alistair Francis
Cc: qem
est
physical address that faulted, shifted by 2 bits. *For other traps, mtval2
is set to zero...*
Signed-off-by: Alexei Filippov
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20240503103052.6819-1-alexei.filip...@syntacore.com>
Cc: qemu-stable
Signed-off-by:
-by: Jason Chien
Reviewed-by: Frank Chang
Reviewed-by: Max Chou
Message-ID: <20240328022343.6871-4-jason.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/gdbstub.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/gdbstub.c b/target
.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu_cfg.h | 1 +
target/riscv/cpu.c | 2 ++
target/riscv/cpu_helper.c | 2 +-
target/riscv/csr.c | 2 +-
target/riscv/tcg/tcg-cpu.c
LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Max Chou
Reviewed-by: Weiwei Li
Message-ID:
Cc: qemu-stable
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a74f0eb29c..
to 63
which belongs to the range [48-63] in order to avoid any future
collisions with reserved exception.
Signed-off-by: Clément Léger
Reviewed-by: Alistair Francis
Message-ID: <20240422135840.1959967-1-cle...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu_bits.h | 2
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