[PATCH v5 11/18] target/riscv: support for 128-bit U-type instructions

Adding the 128-bit version of lui and auipc, and introducing to that end a "set register with immediate" function to handle extension on 128 bits. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas Reviewed-by: Richard Henderson --- target/riscv/translate.c

[PATCH v5 01/18] exec/memop: Adding signedness to quad definitions

Renaming defines for quad in their various forms so that their signedness is now explicit. Done using git grep as suggested by Philippe, with a bit of hand edition to keep assignments aligned. Signed-off-by: Frédéric Pétrot Reviewed-by: Philippe Mathieu-Daudé --- include/exec/memop.h

[PATCH v5 18/18] target/riscv: actual functions to realize crs 128-bit insns

, we also add read and write accesses to the machine and supervisor scratch registers. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/cpu.h | 7 ++ target/riscv/cpu_bits.h | 3 + target/riscv/csr.c | 199 ++-- 3 files

[PATCH v5 05/18] target/riscv: separation of bitwise logic and arithmetic helpers

Introduction of a gen_logic function for bitwise logic to implement instructions in which not propagation of information occurs between bits and use of this function on the bitwise instructions. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas Reviewed-by: Richard Henderson

[PATCH v5 17/18] target/riscv: modification of the trans_csrxx for 128-bit support

As opposed to the gen_arith and gen_shift generation helpers, the csr insns do not have a common prototype, so the choice to generate 32/64 or 128-bit helper calls is done in the trans_csrxx functions. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas Reviewed-by: Richard Henderson

[PATCH v5 04/18] target/riscv: additional macros to check instruction support

of RV64, we keep for now the RV64 only tests for extensions other than RVI and RVM. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas Reviewed-by: Richard Henderson --- target/riscv/translate.c | 20 1 file changed, 16 insertions(+), 4 deletions(-) diff --git

[PATCH v5 06/18] target/riscv: array for the 64 upper bits of 128-bit registers

The upper 64-bit of the 128-bit registers have now a place inside the cpu state structure, and are created as globals for future use. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/cpu.h | 2 ++ target/riscv/cpu.c | 9 + target/riscv

[PATCH v5 03/18] qemu/int128: addition of div/rem 128-bit operations

Addition of div and rem on 128-bit integers, using the 128/64->128 divu and 64x64->128 mulu in host-utils. These operations will be used within div/rem helpers in the 128-bit riscv target. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- include/qemu/int128.h | 6 ++

[PATCH v5 00/18] Adding partial support for 128-bit riscv target

the upper 64-bits Frédéric Pétrot (18): exec/memop: Adding signedness to quad definitions exec/memop: Adding signed quad and octo defines qemu/int128: addition of div/rem 128-bit operations target/riscv: additional macros to check instruction support target/riscv: separation of bitwise logic

Re: [PATCH v3 20/20] target/riscv: Enable uxl field write

nt64_t mask, but this is not so nice. What solution would be best in your opinion ? Thanks, Frédéric r~ -- +---+ | Frédéric Pétrot, Pr. Grenoble INP-Ensimag/TIMA, Ensimag deputy director | | Mob/Pho: +33 6 74 57 99 65/+33

[PATCH v4 17/17] target/riscv: actual functions to realize crs 128-bit insns

to the machine and supervisor scratch registers. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/cpu.h | 12 +++ target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 192 +--- 3 files changed, 172 insertions(+), 33 deletions

[PATCH v4 16/17] target/riscv: modification of the trans_csrxx for 128-bit support

As opposed to the gen_arith and gen_shift generation helpers, the csr insns do not have a common prototype, so the choice to generate 32/64 or 128-bit helper calls is done in the trans_csrxx functions. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas Reviewed-by: Richard Henderson

[PATCH v4 11/17] target/riscv: support for 128-bit shift instructions

Handling shifts for 32, 64 and 128 operation length for RV128, following the general framework for handling various olens proposed by Richard. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/insn32.decode | 10 ++ target/riscv/translate.c

[PATCH v4 08/17] target/riscv: accessors to registers upper part and 128-bit load/store

-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- configs/targets/riscv128-softmmu.mak| 3 +- target/riscv/insn16.decode | 27 +- target/riscv/insn32.decode | 5 ++ target/riscv/translate.c| 43 + target/riscv/insn_trans

[PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructions

The 128-bit bitwise instructions do not need any function prototype change as the functions can be applied independently on the lower and upper part of the registers. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/translate.c | 21 +++-- 1 file

[PATCH v4 07/17] target/riscv: moving some insns close to similar insns

or, where they more logically belong. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvi.c.inc | 34 - 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/target/riscv/insn_trans

[PATCH v4 06/17] target/riscv: setup everything so that riscv128-softmmu compiles

, adding risc128-sofmmu to --target-list produces a (no so useful yet) executable. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- configs/devices/riscv128-softmmu/default.mak | 17 +++ configs/targets/riscv128-softmmu.mak | 5 + include/disas/dis-asm.h

[PATCH v4 13/17] target/riscv: support for 128-bit M extension

handled through the existing generation functions. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/cpu.h | 3 + target/riscv/helper.h | 6 + target/riscv/insn32.decode | 7 + target/riscv/m128_helper.c

[PATCH v4 15/17] target/riscv: helper functions to wrap calls to 128-bit csr insns

version. The trans_csrxx functions supporting 128-bit are yet to be implemented. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 4 target/riscv/helper.h| 3 +++ target/riscv/csr.c | 17

[PATCH v4 12/17] target/riscv: support for 128-bit arithmetic instructions

Addition of 128-bit adds and subs in their various sizes. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/insn32.decode | 3 + target/riscv/translate.c| 63 ++-- target/riscv/insn_trans/trans_rvb.c.inc | 20 +-- target/riscv

[PATCH v4 01/17] exec/memop: Rename MO_Q definition as MO_UQ and add MO_UO

Introducing defines for unsigned quad, signed quad, and unsigned octo access types to handle load and store by 128-bit processors. Signed-off-by: Frédéric Pétrot Reviewed-by: Philippe Mathieu-Daudé --- include/exec/memop.h | 13 target/arm/translate-a32.h

[PATCH v4 02/17] qemu/int128: addition of a few 128-bit operations

Addition of not, xor, div and rem on 128-bit integers, used in particular within div/rem and csr helpers for computations on 128-bit registers in the 128-bit riscv target. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- include/qemu/int128.h | 26 + util/int128.c

[PATCH v4 10/17] target/riscv: support for 128-bit U-type instructions

Adding the 128-bit version of lui and auipc, and introducing to that end a set register with immediat function to handle extension on 128 bits. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/translate.c| 22 ++ target/riscv

[PATCH v4 05/17] target/riscv: array for the 64 upper bits of 128-bit registers

The upper 64-bit of the 128-bit registers have now a place inside the cpu state structure, and are created as globals for future use. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/cpu.h | 2 ++ target/riscv/cpu.c | 9 + target/riscv

[PATCH v4 14/17] target/riscv: adding high part of some csrs

Adding the high part of a very minimal set of csr. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 4 target/riscv/machine.c | 2 ++ 2 files changed, 6 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv

[PATCH v4 04/17] target/riscv: separation of bitwise logic and aritmetic helpers

Introduction of a gen_logic function for bitwise logic to implement instructions in which not propagation of information occurs between bits and use of this function on the bitwise instructions. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas Reviewed-by: Richard Henderson

[PATCH v4 00/17] Adding partial support for 128-bit riscv target

: - 128-bit atomic align accesses: for now, mttcg is disabled, my understanding there is, to say the least, low - full 64/128 bit integration to remove the need for a 128-bit executable. There are places in which I do not yet see clearly how to handle this. Frédéric Pétrot (17): exec/memop

[PATCH v4 03/17] target/riscv: additional macros to check instruction support

of RV64, we keep for now the RV64 only tests for extensions other than RVI and RVM. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/translate.c | 20 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/target/riscv/translate.c b

Re: [PATCH v3 13/21] target/riscv: support for 128-bit shift instructions

Le 20/10/2021 à 21:06, Richard Henderson a écrit : > On 10/19/21 2:48 AM, Frédéric Pétrot wrote: > > Hmm.  3 * (and + shift + cmp + cmov) + 2 * (sub + or) = 16 ops. > Not horrible... > > Let's see. > >     ls = sh & 63;    1 >     rs = -sh & 63;  

Re: [PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bit registers

Le 20/10/2021 à 16:44, Richard Henderson a écrit : > On 10/19/21 2:47 AM, Frédéric Pétrot wrote: >> The upper 64-bit of the 128-bit registers have now a place inside >> the cpu state structure, and are created as globals for future use. >> >> Signed-off-by: Fréd

Re: [PATCH v3 04/21] target/riscv: additional macros to check instruction support

Le 20/10/2021 à 16:08, Richard Henderson a écrit : > On 10/19/21 2:47 AM, Frédéric Pétrot wrote: >> + >> +#define REQUIRE_64_OR_128BIT(ctx) do { \ >> +    if (get_xl(ctx) == MXL_RV32) { \ >> +    return false;  \ >> +    } 

Re: [PATCH v3 21/21] target/riscv: support for 128-bit satp

Le 21/10/2021 à 01:09, Richard Henderson a écrit : > On 10/19/21 2:48 AM, Frédéric Pétrot wrote: >> Support for a 128-bit satp. This is a bit more involved than necessary >> because we took the opportunity to increase the page size to 16kB, and >> change the page table

Re: [PATCH v3 11/21] target/riscv: support for 128-bit bitwise instructions

Le 20/10/2021 à 19:47, Richard Henderson a écrit : > On 10/19/21 2:48 AM, Frédéric Pétrot wrote: >> The 128-bit bitwise instructions do not need any function prototype change >> as the functions can be applied independently on the lower and upper part of >> the regist

[PATCH v3 19/21] target/riscv: actual functions to realize crs 128-bit insns

The csrs are accessed through function pointers: we set-up the table for the 128-bit accesses, make the stub a function that does what it should, and implement basic accesses on read-only csrs. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/cpu.h | 16

[PATCH v3 18/21] target/riscv: modification of the trans_csrxx for 128-bit support

As opposed to the gen_arith and gen_shift generation helpers, the csr insns do not have a common prototype, so the choice to generate 32/64 or 128-bit helper calls is done in the trans_csrxx functions. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/insn_trans

[PATCH v3 21/21] target/riscv: support for 128-bit satp

for the merging of the 32-bit and 64-bit riscv versions in a single executable. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/cpu-param.h | 9 +++- target/riscv/cpu_bits.h | 10 target/riscv/cpu_helper.c | 54 ++-- target/riscv/csr.c

[PATCH v3 14/21] target/riscv: support for 128-bit arithmetic instructions

Addition of 128-bit adds and subs in their various sizes. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/insn32.decode | 3 + target/riscv/translate.c| 105 --- target/riscv/insn_trans/trans_rvb.c.inc | 20 +-- target

[PATCH v3 20/21] target/riscv: adding 128-bit access functions for some csrs

Access to mstatus, mtvec, mscratch and mepc is implemented. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 111 ++-- 2 files changed, 108 insertions(+), 4 deletions(-) diff --git

[PATCH v3 12/21] target/riscv: support for 128-bit U-type instructions

Adding the 128-bit version of lui and auipc. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/insn_trans/trans_rvi.c.inc | 19 +-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv

[PATCH v3 16/21] target/riscv: adding high part of some csrs

Adding the high part of a minimal set of csr. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/cpu.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8b96ccb37a..27ec4fec63 100644 --- a/target/riscv/cpu.h

[PATCH v3 08/21] target/riscv: adding accessors to the registers upper part

that the misa_mxl_max field is const. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/translate.c | 45 1 file changed, 45 insertions(+) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index b64fe8470d..b6ddcf7a10 100644

[PATCH v3 17/21] target/riscv: helper functions to wrap calls to 128-bit csr insns

function that is currently a stub. The trans_csrxx functions supporting 128-bit are yet to be implemented. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/cpu.h | 4 target/riscv/helper.h| 3 +++ target/riscv/csr.c | 7 +++ target/riscv

[PATCH v3 15/21] target/riscv: support for 128-bit M extension

handled through the existing generation functions. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/cpu.h | 1 + target/riscv/helper.h | 6 + target/riscv/insn32.decode | 7 + target/riscv/m128_helper.c

[PATCH v3 01/21] memory: change define name for consistency

Changed MO_Q into MO_UQ so as to avoid confusion, as suggested by Philippe Mathieu-Daudé. Signed-off-by: Frédéric Pétrot --- include/exec/memop.h | 8 target/arm/translate-a32.h | 4 ++-- target/arm/translate-a64.c | 8

[PATCH v3 13/21] target/riscv: support for 128-bit shift instructions

Handling shifts for 32, 64 and 128 operation length for RV128, following the general framework for handling various olens proposed by Richard. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/insn32.decode | 10 + target/riscv/translate.c

[PATCH v3 11/21] target/riscv: support for 128-bit bitwise instructions

The 128-bit bitwise instructions do not need any function prototype change as the functions can be applied independently on the lower and upper part of the registers. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/translate.c | 22 ++ 1 file

[PATCH v3 05/21] target/riscv: separation of bitwise logic and aritmetic helpers

Introduction of a gen_logic function for bitwise logic to implement instructions in which not propagation of information occurs between bits and use of this function on the bitwise instructions. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/translate.c

[PATCH v3 10/21] target/riscv: support for 128-bit loads and store

The 128-bit ISA adds ldu, lq and sq. We provide here support for these instructions. Note that although we compute a 128-bit address, we only use the lower 64-bit to actually address memory, cowardly utilizing the existing address translation mechanism of QEMU. Signed-off-by: Frédéric Pétrot Co

[PATCH v3 09/21] target/riscv: moving some insns close to similar insns

or, where they more logically belong. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/insn_trans/trans_rvi.c.inc | 34 - 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv

[PATCH v3 07/21] target/riscv: setup everything so that riscv128-softmmu compiles

), it is implicitly there in '#else' statements. Most added infrastructure files are no far from being copies of the 64-bit version. Once this patch applied, adding risc128-sofmmu to --target-list produces a (no so useful yet) executable. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- configs

[PATCH v3 03/21] Int128.h: addition of a few 128-bit operations

Addition of not, xor, div and rem on 128-bit integers, used in particular within div/rem and csr helpers for computations on 128-bit registers. These will be used by the 128-bit riscv version. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- include/qemu/int128.h | 264

[PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bit registers

The upper 64-bit of the 128-bit registers have now a place inside the cpu state structure, and are created as globals for future use. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/cpu.h | 1 + target/riscv/translate.c | 5 - 2 files changed, 5

[PATCH v3 04/21] target/riscv: additional macros to check instruction support

Given that the 128-bit version of the riscv spec adds new instructions, and that some instructions that were previously only available in 64-bit mode are now available for both 64-bit and 128-bit, we added new macros to check for the processor mode during translation. Signed-off-by: Frédéric

[PATCH v3 00/21] Adding partial support for 128-bit riscv target

...@linaro.org Frédéric Pétrot (21): memory: change define name for consistency memory: add a few defines for octo (128-bit) values Int128.h: addition of a few 128-bit operations target/riscv: additional macros to check instruction support target/riscv: separation of bitwise logic and aritmetic

[PATCH v3 02/21] memory: add a few defines for octo (128-bit) values

Introducing unsigned quad, signed quad, and octo accesses types to handle load and store by 128-bit processors. Signed-off-by: Frédéric Pétrot --- include/exec/memop.h | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/include/exec/memop.h b/include/exec/memop.h index

Re: [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol

ctx->ol = MXL_RV32; >>   return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl); >>   } >>     static bool trans_sraw(DisasContext *ctx, arg_sraw *a) >>   { >>   REQUIRE_64BIT(ctx); >> -    ctx->w = true; >> +    ctx->ol = MXL_RV32; >>   

Re: [PATCH 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl

tatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64); } env->mstatus = mstatus; Frédéric -- +---+ | Frédéric Pétrot, Pr. Grenoble INP-Ensimag/TIMA, Ensimag deputy director | | Mob/Pho: +33 6 74 57 99 65/+33 4 76 57 48 70 Ad augusta per angusta | | http://tima.univ-grenoble-alpes.fr frederic.pet...@univ-grenoble-alpes.fr | +---+

Re: [RFC PATCH 00/13] target/riscv: Rationalize XLEN and operand length

++-- > target/riscv/insn_trans/trans_rvb.c.inc | 140 ++- > target/riscv/insn_trans/trans_rvi.c.inc | 44 +++--- > target/riscv/insn_trans/trans_rvm.c.inc | 36 +++-- > target/riscv/insn_trans/trans_rvv.c.inc | 29 ++-- > 17 files changed, 498 inserti

[PATCH v2 24/27] target/riscv: modification of the trans_csrxx for 128-bit support

As opposed to the gen_arith and gen_shift generation helpers, the csr insns do not have a common prototype, so the choice to generate 32/64 or 128-bit helper calls is done in the trans_csrxx functions. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/insn_trans

[PATCH v2 26/27] target/riscv: adding 128-bit access functions for some csrs

Access to mstatus, mtvec, mscratch and mepc is implemented. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 111 ++-- 2 files changed, 108 insertions(+), 4 deletions(-) diff --git

[PATCH v2 27/27] target/riscv: support for 128-bit satp

for the merging of the 32-bit and 64-bit riscv versions in a single executable. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/cpu-param.h | 9 - target/riscv/cpu_bits.h | 10 + target/riscv/cpu_helper.c | 54 +++ target/riscv/csr.c

[PATCH v2 15/27] target/riscv: 128-bit support for instructions using gen_shift

Support for the base shift instructions working on 128-bit registers. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/insn_trans/trans_rvi.c.inc | 224 ++-- 1 file changed, 209 insertions(+), 15 deletions(-) diff --git a/target/riscv

[PATCH v2 22/27] target/riscv: adding high part of some csrs

Adding the high part of a minimal set of csr. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/cpu.h | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 81cbd77d09..a2d7d65efb 100644 --- a/target

[PATCH v2 25/27] target/riscv: actual functions to realize crs 128-bit insns

The csrs are accessed through function pointers: we set-up the table for the 128-bit accesses, make the stub a function that does what it should, and implement basic accesses on read-only csrs. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/cpu.h | 16

[PATCH v2 23/27] target/riscv: helper functions to wrap calls to 128-bit csr insns

function that is currently a stub. The trans_csrxx functions supporting 128-bit are yet to be implemented. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/cpu.h | 4 target/riscv/helper.h| 3 +++ target/riscv/csr.c | 7 +++ target/riscv

[PATCH v2 14/27] target/riscv: 128-bit support for instructions using gen_arith/gen_logic

-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/insn_trans/trans_rvi.c.inc | 223 +--- 1 file changed, 198 insertions(+), 25 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index ab85693364..814aa5f1b7

[PATCH v2 21/27] target/riscv: div and rem insns on 128-bit

Given the complexity of the implementation of these instructions, we call helpers to produce their behavior. From an implementation standpoint, we ended up by adding two more tcg globals to return the 128-bit result in a wrapper that itself is called by gen_arith. Signed-off-by: Frédéric Pétrot

[PATCH v2 20/27] target/riscv: addition of the 'd' insns for 128-bit mult/div/rem

All mult/div/rem instructions that work on double integers (suffixed 'd') can be tcg-generated in a few micro-ops, they are added here. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/insn32.decode | 7 ++ target/riscv/insn_trans/trans_rvm.c.inc

[PATCH v2 11/27] target/riscv: handling 128-bit part in logic/arith/shift gen helpers

The code generation helpers are now able to handle also the 128-bit functions, although no such function exists yet. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/translate.c | 102 +-- 1 file changed, 88 insertions(+), 14

[PATCH v2 17/27] target/riscv: 128-bit double word integer arithmetic instructions

The ISA adds the addid, addd and subd instructions that work on 64-bit while in 128-bit mode. Similarly to what is done for insns working on 32-bit (w suffix), we set a 'd' flag so that masking and sign extension occurs as it should when using the registers' accessors. Signed-off-by: Frédéric

[PATCH v2 19/27] target/riscv: support for 128-bit base multiplications insns

We deal here with the multiplication part of the M extension as, although a bit complex, the code is generated inline, as opposed to division and remainder that resort to helpers (to come soon). Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/insn_trans

[PATCH v2 10/27] target/riscv: adding accessors to the registers upper part

(as it should since the spec indicates that the registers size might be dynamically changeable), although it is for now only set at initialization time. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/translate.c | 45 1 file changed

[PATCH v2 16/27] target/riscv: support for 128-bit loads and store

The 128-bit ISA adds ldu, lq and sq. We provide here support for these instructions. Note that although we compute a 128-bit address, we only use the lower 64-bit to actually address memory, cowardly utilizing the existing address translation mechanism of QEMU. Signed-off-by: Frédéric Pétrot Co

[PATCH v2 07/27] target/riscv: refactoring calls to gen_arith

gen_arith now takes three functions instead of one as arguments, one for each register size. All call sites changed to use this refactored version, without yet supporting sizes other than 32 and 64. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/translate.c

[PATCH v2 18/27] target/riscv: 128-bit double word integer shift instructions

All variations of shifts on 64-bit values are available in the 128-bit ISA, so we add them now. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/insn32.decode | 10 + target/riscv/translate.c| 4 +- target/riscv/insn_trans

[PATCH v2 04/27] target/riscv: array for the 64 upper bits of 128-bit registers

The upper 64-bit of the 128-bit registers have now a place inside the cpu state structure, and are created as globals for future use. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/cpu.h | 3 +++ target/riscv/translate.c | 6 +- 2 files changed, 8

[PATCH v2 12/27] target/riscv: moving some insns close to similar insns

or, where they more logically belong. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/insn_trans/trans_rvi.c.inc | 34 - 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv

[PATCH v2 06/27] target/riscv: separation of bitwise logic and aritmetic helpers

Introduction of a gen_logic function for bitwise logic to implement instructions in which not propagation of information occurs between bits and use of this function on the bitwise instructions. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/translate.c

[PATCH v2 13/27] target/riscv: rename a few gen function helpers

Add the tl suffix to the existing integer gen_xxx functions that apply to target_long types for which a 128-bit version will also exist, so that it is immediately visible which function is for which type(s). Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv

[PATCH v2 05/27] target/riscv: additional macros to check instruction support

Given that the 128-bit version of the riscv spec adds new instructions, and that some instructions that were previously only available in 64-bit mode are now available for both 64-bit and 128-bit, we added new macros to check for the processor mode during translation. Signed-off-by: Frédéric

[PATCH v2 01/27] memory: add a few defines for octo (128-bit) values

be applied first for the rest to compile Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- include/exec/memop.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/include/exec/memop.h b/include/exec/memop.h index 04264ffd6b..9297f58a39 100644 --- a/include/exec/memop.h +++ b

[PATCH v2 08/27] target/riscv: refactoring calls to gen_shift

As for arithmetic operations, we now pass functions pointers to deal with 32, 64 and 128-bit shift operations, and to change all call sites accordingly. For now, 128-bit operations are still not handled. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/translate.c

[PATCH v2 09/27] target/riscv: setup everything so that riscv128-softmmu compiles

), it is implicitly there in '#else' statements. Most added infrastructure files are no far from being copies of the 64-bit version. Once this patch applied, adding risc128-sofmmu to --target-list produces a (no so useful yet) executable. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- configs

[PATCH v2 00/27] Adding partial support for 128-bit riscv target

on rv32 For the 128-bit, the tests are there: https://github.com/fpetrot/128-test * from hash 925e1af2c7, run the tests in unit_test_i * from hash 6d4a39f2c4, run in addition the tests in unit_test_m * from hash 864e563916, run in addition the tests unit_test_csr Frédéric Pétrot (27): memory

[PATCH v2 03/27] target/riscv: adding upper 64 bits for misa

Addition of misah, upper part of misa in the 128-bit extension. This is required for the is_64bit and is_128bit macros that we introduce in addition to the existing is_32bit one to know which register size the processor uses. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas

[PATCH v2 02/27] Int128.h: addition of a few 128-bit operations

Addition of not, xor, div and rem on 128-bit integers, used in particular within div/rem and csr helpers for computations on 128-bit registers. These will be used by the 128-bit riscv version. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- include/qemu/int128.h | 264

Re: [PATCH 0/8] RISC V partial support for 128-bit architecture

Le 31/08/2021 à 05:15, Alistair Francis a écrit : > On Tue, Aug 31, 2021 at 5:29 AM Frédéric Pétrot > wrote: >> >> This series of patches aims at adding partial 128-bit support to the riscv >> target, following the (unratified) RV128I specification, Chapter 7 of >

Re: [PATCH 1/8] target/riscv: Settings for 128-bit extension support

Hello Alistair, Le 31/08/2021 à 05:13, Alistair Francis a écrit : > On Tue, Aug 31, 2021 at 5:26 AM Frédéric Pétrot > wrote: >> >> Starting 128-bit extension support implies a few modifications in the >> existing sources because checking for 32-bit is done by checking

Re: [PATCH 3/8] target/riscv: Addition of 128-bit ldu, lq and sq instructions

Hello Richard, Le 31/08/2021 à 04:24, Richard Henderson a écrit : > On 8/30/21 10:16 AM, Frédéric Pétrot wrote: >> +#if defined(TARGET_RISCV128) >> +/* >> + * Accessing signed 64-bit or 128-bit values should be part of MemOp in >> + * include/exec/memop.h >>

Re: [PATCH 4/8] target/riscv: 128-bit arithmetic and logic instructions

Hello Philippe, Le 30/08/2021 à 23:40, Philippe Mathieu-Daudé a écrit : > On 8/30/21 11:38 PM, Philippe Mathieu-Daudé wrote: >> On 8/30/21 7:16 PM, Frédéric Pétrot wrote: >>> Adding the support for the 128-bit arithmetic and logic instructions. >>> Remember that a

[PATCH 4/8] target/riscv: 128-bit arithmetic and logic instructions

must also be modified for proper sign extension. Most algorithms taken from Hackers' delight. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/insn32.decode | 13 + target/riscv/insn_trans/trans_rvi.c.inc | 955 +++- target/riscv

[PATCH 6/8] target/riscv: Support of compiler's 128-bit integer types

128-bit mult and div helpers may now use the compiler support for 128-bit integers if it exists. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/cpu.h | 13 +++ target/riscv/m128_helper.c | 48 ++ 2 files changed

[PATCH 8/8] target/riscv: Support for 128-bit satp

bits, truncated by the implementation to 64, as it assumes the upper 64 bits of the address are zeroed for compatibility with the rest of the translation process. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/cpu-param.h | 11 - target/riscv/cpu_bits.h | 10

[PATCH 2/8] target/riscv: 128-bit registers creation and access

Addition of the upper 64 bits of the 128-bit registers, along with the setter and getter for them and creation of the corresponding global tcg values. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- slirp| 2 +- target/riscv/cpu.h | 3 +++ target

[PATCH 7/8] target/riscv: 128-bit support for some csrs

. We fallback on the 64-bit version of the csr functions, assuming the relevant information stands in the lower double-word when no 128-bit support is implemented. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/cpu.h | 52 +++-- target/riscv

[PATCH 0/8] RISC V partial support for 128-bit architecture

s are ours.) Frédéric Pétrot (8): target/riscv: Settings for 128-bit extension support target/riscv: 128-bit registers creation and access target/riscv: Addition of 128-bit ldu, lq and sq instructions target/riscv: 128-bit arithmetic and logic instructions target/riscv: 128-bit multiply

[PATCH 3/8] target/riscv: Addition of 128-bit ldu, lq and sq instructions

the existing state in QEMU has a great impact that we are not capable of fully evaluating, so we choose to pass this information into another parameter and let memop as it is for now. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- include/tcg/tcg-op.h| 1

[PATCH 5/8] target/riscv: 128-bit multiply and divide

Adding the support for the 128-bit (m) extension. Division and remainder are helpers using a simple implementation of Knuth algorithm D. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/helper.h | 8 + target/riscv/insn32.decode

[PATCH 1/8] target/riscv: Settings for 128-bit extension support

of the misa register. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- configs/devices/riscv128-softmmu/default.mak | 16 ++ configs/targets/riscv128-softmmu.mak | 5 ++ gdb-xml/riscv-128bit-cpu.xml | 48 ++ gdb-xml/riscv-128bit-virtual.xml

Re: [Qemu-devel] CFP: 1st International QEMU Users Forum

-- +-+ | Frédéric Pétrot, Pr. ENSIMAG-TIMA/SLS frederic.pet...@imag.fr | | Phone : +33 4 76 57 48 70 Fluctuat nec mergitur | | Mobile: +33 6 74 57 99 65 Ad augusta per angusta | | Fax : +33 4 76 57 49 81 Eppur si muove | +-+

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