Hi,
This series failed build test on s390x host. Please find the details below.
Type: series
Message-id: 20180209075503.16996-1-...@ozlabs.ru
Subject: [Qemu-devel] [PATCH qemu v7 0/4] vfio-pci: Allow mmap of MSIX BAR
=== TEST SCRIPT BEGIN ===
#!/bin/bash
# Testing script will be invoked under th
Hi,
This series failed docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
Type: series
Message-id: 20180209075503.16996-1-...@ozlabs.ru
Subject: [Qemu-devel] [PATCH qemu v7 0/4] vfio-pci: A
On Fri, Feb 9, 2018 at 8:33 PM, Michael Clark wrote:
>
>
> On Fri, Feb 9, 2018 at 5:35 AM, Richard Henderson <
> richard.hender...@linaro.org> wrote:
>
>> On 02/07/2018 05:28 PM, Michael Clark wrote:
>> > +++ b/hw/riscv/riscv_elf.c
>> > @@ -0,0 +1,244 @@
>> > +/*
>> > + * elf.c - A simple package
On 08.02.2018 22:41, Eduardo Habkost wrote:
> On Thu, Feb 08, 2018 at 02:59:17PM -0600, Eric Blake wrote:
>> On 02/08/2018 01:59 PM, Eduardo Habkost wrote:
>>> On Wed, Feb 07, 2018 at 12:50:13PM -0500, Luiz Capitulino wrote:
The query-cpus command has an extremely serious side effect:
it
We ignore silently the value of smp_threads when we set
the default VSMT value, and if smp_threads is greater than VSMT
kernel is going into trouble later.
Fixes: 8904e5a750
("spapr: Adjust default VSMT value for better migration compatibility")
Signed-off-by: Laurent Vivier
---
Notes:
v3:
On 02/08/2018 03:20 PM, Eric Blake wrote:
> On 02/08/2018 03:57 AM, Christian Borntraeger wrote:
>> This patch is the s390 implementation of guest crash information,
>> similar to commit d187e08dc4 ("i386/cpu: add crash-information QOM
>> property") and the related commits. We will detect several
On 08/02/2018 10:44, Wanpeng Li wrote:
> From: Wanpeng Li
>
> Add PV_DEDICATED hint cpuid feature bit.
Please add a new feature word, since this is not a PV feature but more
like a performance hint.
Thanks,
Paolo
> Cc: Paolo Bonzini
> Cc: Radim Krčmář
> Cc: Eduardo Habkost
> Signed-off-by:
On 08/02/2018 19:12, Eduardo Habkost wrote:
> On Thu, Feb 08, 2018 at 05:44:20PM +0800, Wanpeng Li wrote:
>> From: Wanpeng Li
>>
>> Add PV_DEDICATED hint cpuid feature bit.
>>
> [...]
>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>> index d70954b..cf48931 100644
>> --- a/target/i386/cpu.c
On 02/08/2018 03:14 PM, Cédric Le Goater wrote:
> On 02/08/2018 06:22 PM, Philippe Mathieu-Daudé wrote:
>> Signed-off-by: Philippe Mathieu-Daudé
>
> This looks like a good idea. (Have you actually tried it ?
> just asking)
v1 obviously not :S v2 yes!
>
> Reviewed-by: Cédric Le Goater
Thanks
(qemu) info mtree
address-space: cpu-memory-0
- (prio 0, i/o): system
-07ff (prio 0, rom): aspeed.boot_rom
1e60-1e7f (prio -1, i/o): aspeed_soc.io
- 1e784000-1e78401f (prio 0, i/o)
On 02/08/2018 09:40 PM, Andrew Jeffery wrote:
> On Thu, 2018-02-08 at 14:40 -0300, Philippe Mathieu-Daudé wrote:
>> On 02/08/2018 02:30 PM, Peter Maydell wrote:
>>> On 8 February 2018 at 17:22, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/aspeed_s
(qemu) info mtree
address-space: cpu-memory-0
- (prio 0, i/o): system
-07ff (prio 0, rom): aspeed.boot_rom
-1e60-1e7f (prio -1, i/o): aspeed_soc.io
+1e60-1e7f (prio -1000, i/
Since v1:
- corrected buggy UART base address (noticed by Peter)
- tested using openbmc-build provided by Andrew
- added Cédric R-b
tested with:
$ qemu-system-arm -M romulus-bmc -m 512 \
-drive file=image-bmc,if=mtd,format=raw -nographic
using this image:
https://openpower.xyz/job/open
https://github.com/michaeljclark/riscv-qemu/commit/17272f5c66adf8532f196d660d2a593c2178ac95
hw/core/loader.c | 18 --
include/hw/elf_ops.h | 28
include/hw/loader.h | 17 -
3 files changed, 48 insertions(+), 15 deletions(-)
On Thu, Feb 08, 2018 at 02:58:29PM +, Peter Maydell wrote:
> On 4 February 2018 at 20:41, Richard Braun wrote:
> > Consider that data is always immediately sent. As a result, keep
> > the SR_TXE and SR_TC bits always set. In addition, fix the reset value
> > of the USART status register.
>
>
From: David Hildenbrand
We have to consider all deliverable interrupts.
We now have to take care of the special scenario, where we first
inject an interrupt with a WAIT PSW, followed by a !WAIT PSW. (very
unlikely but possible)
Signed-off-by: David Hildenbrand
Message-Id: <20180129125623.21729
From: Alice Frosi
In alpine docker image the qemu-system-s390x build is broken and
it throws this error:
qemu-system-s390x: Initialization of device s390-ipl failed: could not
load bootloader 's390-ccw.img'
The grep command of busybox uses regex. This fails on binary data
(e.g. stops on every \0
From: David Hildenbrand
All blocks are 4k in size, which is only true for two of them right now.
Also some reserved fields were wrong, fix it and convert all reserved
fields to u8.
This also fixes the LPAR part output in /proc/sysinfo under TCG. (for
now, everything was indicated as 0)
While at
From: David Hildenbrand
We can directly call the right function.
Suggested-by: Cornelia Huck
Signed-off-by: David Hildenbrand
Message-Id: <20180129125623.21729-7-da...@redhat.com>
Signed-off-by: Cornelia Huck
---
hw/intc/s390_flic.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
di
From: David Hildenbrand
This makes it clearer, which device is used for which accelerator.
Reviewed-by: Christian Borntraeger
Signed-off-by: David Hildenbrand
Message-Id: <20180129125623.21729-3-da...@redhat.com>
Signed-off-by: Cornelia Huck
---
hw/intc/s390_flic.c | 7 +--
hw/
From: David Hildenbrand
We currently only support CRW machine checks. This is a preparation for
real floating interrupt support.
Get rid of the queue and handle it via the bit INTERRUPT_MCHK. We don't
rename it for now, as it will be soon gone (when moving crw machine checks
into the flic).
Ple
From: David Hildenbrand
This avoids tons of conversions when handling interrupts.
Acked-by: Christian Borntraeger
Signed-off-by: David Hildenbrand
Message-Id: <20180129125623.21729-18-da...@redhat.com>
Signed-off-by: Cornelia Huck
---
hw/intc/s390_flic_kvm.c | 21 -
1 fil
From: David Hildenbrand
Kicking all CPUs on every floating interrupt is far from efficient.
Let's optimize it at least a little bit.
Signed-off-by: David Hildenbrand
Message-Id: <20180129125623.21729-12-da...@redhat.com>
Signed-off-by: Cornelia Huck
---
hw/intc/s390_flic.c | 31 ++
From: Christian Borntraeger
commit 67915de9f038 ("s390x/event-facility: variable-length event
masks") switched the sclp receive/send mask. This broke the sclp
lm console.
Signed-off-by: Christian Borntraeger
Fixes: commit 67915de9f038 ("s390x/event-facility: variable-length event masks")
Cc: Co
From: David Hildenbrand
We can simply search for an object of our common type.
Signed-off-by: David Hildenbrand
Message-Id: <20180129125623.21729-4-da...@redhat.com>
Signed-off-by: Cornelia Huck
---
hw/intc/s390_flic.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git
From: David Hildenbrand
Let the flic device handle it internally. This will allow us to later
on store floating interrupts in the flic for the TCG case.
This now also simplifies kvm.c. All that's left is the fallback
interface for floating interrupts, which is now triggered directly via
the flic
From: David Hildenbrand
Move floating interrupt handling into the flic. Floating interrupts
will now be considered by all CPUs, not just CPU #0. While at it, convert
I/O interrupts to use a list and make sure we properly consider I/O
sub-classes in s390_cpu_has_io_int().
Signed-off-by: David Hil
The following changes since commit 008a51bbb343972dd8cf09126da8c3b87f4e1c96:
Merge remote-tracking branch 'remotes/famz/tags/staging-pull-request' into
staging (2018-02-08 14:31:51 +)
are available in the git repository at:
git://github.com/cohuck/qemu tags/s390x-20180209
From: David Hildenbrand
This is a preparation for floating interrupt support and only applies to
MTTCG, single threaded TCG works just fine. If a floating interrupt wakes
up a VCPU and the CPU thinks it can run (clearing cs->halted), at
the point where the interrupt would be delivered, already an
From: David Hildenbrand
s390x is ready. Most likely we are missing some pieces, but it should
already be in pretty good shape now.
Signed-off-by: David Hildenbrand
Message-Id: <20180129125623.21729-16-da...@redhat.com>
Signed-off-by: Cornelia Huck
---
configure | 1 +
1 file changed, 1 insert
From: David Hildenbrand
We should be pretty good in shape now. Floating interrupts are working
and atomic instructions should be atomic.
Signed-off-by: David Hildenbrand
Message-Id: <20180129125623.21729-15-da...@redhat.com>
Signed-off-by: Cornelia Huck
---
hw/s390x/s390-virtio-ccw.c | 4
From: David Hildenbrand
Now that we have access to the io interrupts, we can implement
clear_io_irq() for TCG.
Signed-off-by: David Hildenbrand
Message-Id: <20180129125623.21729-11-da...@redhat.com>
Signed-off-by: Cornelia Huck
---
hw/intc/s390_flic.c | 31 +--
1 f
From: David Hildenbrand
Use s390_cpu_virt_mem_write() so we can actually revert what we did
(re-inject the dequeued IO interrupt).
Signed-off-by: David Hildenbrand
Message-Id: <20180129125623.21729-10-da...@redhat.com>
Signed-off-by: Cornelia Huck
---
target/s390x/helper.h | 1 +
target
On s390x, pci support is implemented via a set of instructions
(no mmio). Unfortunately, none of them are documented in the
PoP; the code is based upon the existing implementation for KVM
and the Linux zpci driver.
Reviewed-by: David Hildenbrand
Signed-off-by: Cornelia Huck
---
target/s390x/hel
From: Yi Min Zhao
Current s390x PCI IOMMU code is lack of flags' checking, including:
1) protection bit
2) table length
3) table offset
4) intermediate tables' invalid bit
5) format control bit
This patch introduces a new struct named S390IOTLBEntry, and makes up
these missed checkings. At the s
AEN and AIS can be provided unconditionally, ZPCI should be turned on
manually.
With -cpu qemu,zpci=on, the guest kernel can now successfully detect
virtio-pci devices under tcg.
Also fixup the order of the MSA_EXT_{3,4} flags while at it.
Reviewed-by: David Hildenbrand
Signed-off-by: Cornelia
From: David Hildenbrand
This avoids tons of conversions when handling interrupts.
Signed-off-by: David Hildenbrand
Message-Id: <20180129125623.21729-19-da...@redhat.com>
Signed-off-by: Cornelia Huck
---
hw/intc/s390_flic.c | 13 -
hw/s390x/css.c | 10 +--
From: David Hildenbrand
Current STSI implementation is a mess, so let's rewrite it.
Problems fixed by this patch:
1) The order of exceptions/when recognized is wrong.
2) We have to store to virtual address space, not absolute.
3) Alignment check of the block is missing.
3) The SMP information is
From: David Hildenbrand
For now, the kernel does not properly indicate configured CPU subfunctions
to the guest, but simply uses the host values (as support in KVM is still
missing). That's why we missed to model the PTFF subfunctions that come
with Multiple-epoch facility.
Let's properly add th
From: David Hildenbrand
This avoids tons of conversions when handling interrupts.
Signed-off-by: David Hildenbrand
Message-Id: <20180129125623.21729-17-da...@redhat.com>
Signed-off-by: Cornelia Huck
---
hw/intc/s390_flic.c | 23 +--
include/hw/s390x/s390_flic.h |
All your mainframes are belong to me.
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Christian Borntraeger
Signed-off-by: Cornelia Huck
---
MAINTAINERS | 23 +++
1 file changed, 23 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 301b6996e1..6c675f2a7e 100644
---
Split it out from the s390-ccw-virtio machine, add Thomas as a
maintainer in addition to Christian.
Acked-by: Christian Borntraeger
Acked-by: Thomas Huth
Signed-off-by: Cornelia Huck
---
MAINTAINERS | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/MAINTAINERS b/M
From: Yi Min Zhao
The VFIO common code doesn't provide the possibility to modify a
previous mapping entry in another way than unmapping and mapping again
with new properties.
To avoid -EEXIST DMA mapping error, we introduce a GHashTable to store
S390IOTLBEntry instances in order to cache the map
From: Yi Min Zhao
When registering ioat, pba should be comprised of leftmost 52 bits and
rightmost 12 binary zeros, and pal should be comprised of leftmost 52
bits and right most 12 binary ones. The lower 12 bits of words 5 and 7
of the FIB are ignored by the facility. Let's fixup this.
Reviewed
On 09.02.2018 03:19, Fam Zheng wrote:
On Thu, 02/08 14:28, Piotr Sarna wrote:
BlockSizes structure used in block size probing has uint32_t types
for logical and physical sizes. These fields are wrongfully assigned
to uint16_t in BlockConf, which results, among other errors,
in assigning 0 instea
On Thu, Feb 08, 2018 at 03:33:32PM -0800, Alistair Francis wrote:
> >> @@ -96,12 +96,10 @@ static uint64_t stm32f2xx_usart_read(void *opaque,
> >> hwaddr addr,
> >> switch (addr) {
> >> case USART_SR:
> >> retvalue = s->usart_sr;
> >> -s->usart_sr &= ~USART_SR_TC;
>
> T
BlockSizes structure used in block size probing has uint32_t types
for logical and physical sizes. These fields are wrongfully assigned
to uint16_t in BlockConf, which results, among other errors,
in assigning 0 instead of 65536 (which will be the case in at least
future LizardFS block device drive
Acked-by: David Hildenbrand
Signed-off-by: Cornelia Huck
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e3e0b1d2f4..54feb95646 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -236,6 +236,7 @@ F: disas/ppc.c
S390
M: Richard Henderson
M: Alexa
On Fri, Feb 09, 2018 at 10:23:13AM +0100, Richard Braun wrote:
> On Thu, Feb 08, 2018 at 02:58:29PM +, Peter Maydell wrote:
> > The guest can clear the TC and TXE bits by writing to the USART_SR
> > directly, so this code should set both of them, I think ?
>
> Right, nice catch.
Although, aft
On 8 February 2018 at 16:49, Richard Henderson
wrote:
> Changes since last:
> * Fix the constant pool patch for ppc64 and sparc64 hosts.
> That's a bit of a brown-bag moment. I failed to test those
> because "clearly" they weren't affected the patches.
>
>
> r~
>
>
> The following chang
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180209092524.31348-1-coh...@redhat.com
Subject: [Qemu-devel] [PULL 00/29] s390x: assorted updates
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --one
>
> > >
> > > $ cat strace_c.sh
> > > strace -tt -p $1 -c -o result_$1.log &
> > > sleep $2
> > > pid=$(pidof strace)
> > > kill $pid
> > > cat result_$1.log
> > >
> > > Before appling this change:
> > > $ ./strace_c.sh 10528 30
> > > % time seconds usecs/call callserrors syscall
> > >
On 8 February 2018 at 19:08, Michael S. Tsirkin wrote:
> The following changes since commit 008a51bbb343972dd8cf09126da8c3b87f4e1c96:
>
> Merge remote-tracking branch 'remotes/famz/tags/staging-pull-request' into
> staging (2018-02-08 14:31:51 +)
>
> are available in the git repository at:
On Fri, Feb 09, 2018 at 01:29:12PM +0800, Fam Zheng wrote:
> v7: Tweak wording again "allowing concurrent writers" -> "allowing other QEMU
> processes to open it in write mode". [Eric, Stefan, Kevin]
> Add patch to document share-rw. [Stefan]
>
> v6: Tweak wording ("concurrent writers"). [
Hi,
This series failed build test on s390x host. Please find the details below.
Type: series
Message-id: 1518169992-19288-1-git-send-email-sa...@skytechnology.pl
Subject: [Qemu-devel] [PATCH v2] block: unify blocksize types
=== TEST SCRIPT BEGIN ===
#!/bin/bash
# Testing script will be invoked u
BlockSizes structure used in block size probing has uint32_t types
for logical and physical sizes. These fields are wrongfully assigned
to uint16_t in BlockConf, which results, among other errors,
in assigning 0 instead of 65536 (which will be the case in at least
future LizardFS block device drive
There is a race between TCG and accesses to the dirty log:
vCPU thread reader thread
--- ---
TLB check -> slow path
notdirty_mem_write
write to RAM
set dirty flag
Now that memory_region_sync_dirty_bitmap is NULL, we can unify its
loop with memory_global_dirty_log_sync's. The only difference is
that memory_region_sync_dirty_bitmap will no longer call log_sync on
FlatRanges that do have a zero dirty_log_mask, but this is okay because
video memory is always re
This is a race that can happen when migrating TCG guests under load.
It was introduced by the change to run vCPUs outside the big QEMU lock.
Paolo Bonzini (4):
memory: remove memory_region_test_and_clear_dirty
memory: hide memory_region_sync_dirty_bitmap behind
DirtyBitmapSnapshot
memory
It is unused after g364fb has been converted to use DirtyBitmapSnapshot.
Signed-off-by: Paolo Bonzini
---
include/exec/memory.h | 24 +++-
memory.c | 8
2 files changed, 3 insertions(+), 29 deletions(-)
diff --git a/include/exec/memory.h b/include/exec
Simplify the users of memory_region_snapshot_and_clear_dirty, so
that they do not have to call memory_region_sync_dirty_bitmap
explicitly.
Signed-off-by: Paolo Bonzini
---
hw/display/cg3.c | 1 -
hw/display/exynos4210_fimd.c | 1 -
hw/display/framebuffer.c | 1 -
hw/display/g3
* Wei Wang (wei.w.w...@intel.com) wrote:
> On 02/09/2018 04:15 AM, Dr. David Alan Gilbert wrote:
> > * Wei Wang (wei.w.w...@intel.com) wrote:
> > > This is the deivce part implementation to add a new feature,
> > > VIRTIO_BALLOON_F_FREE_PAGE_HINT to the virtio-balloon device. The device
> > > recei
On 02/09/2018 09:57 AM, Philippe Mathieu-Daudé wrote:
> (qemu) info mtree
> address-space: cpu-memory-0
>- (prio 0, i/o): system
> -07ff (prio 0, rom): aspeed.boot_rom
> 1e60-1e7f (prio -1, i/o): aspe
From: Andrey Smirnov
IP block found on several generations of i.MX family does not use
vanilla SDHCI implementation and it comes with a number of quirks.
Introduce i.MX SDHCI subtype of SDHCI block to add code necessary to
support unmodified Linux guest driver.
Cc: Peter Maydell
Cc: Jason Wang
l-tcg-20180208' into
staging (2018-02-08 17:41:15 +)
are available in the Git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20180209
for you to fetch changes up to bbba7757bacc9f890a3f028d328b4b429dbe78ec:
hw/core/generic-loader: Allow PC to
From: Andrey Smirnov
Add minimal code needed to allow upstream Linux guest to boot.
Cc: Peter Maydell
Cc: Jason Wang
Cc: Philippe Mathieu-Daudé
Cc: Marcel Apfelbaum
Cc: Michael S. Tsirkin
Cc: qemu-devel@nongnu.org
Cc: qemu-...@nongnu.org
Cc: yurov...@gmail.com
Reviewed-by: Philippe Mathieu-
From: Ard Biesheuvel
This implements emulation of the new SM4 instructions that have
been added as an optional extension to the ARMv8 Crypto Extensions
in ARM v8.2.
Signed-off-by: Ard Biesheuvel
Message-id: 20180207111729.15737-5-ard.biesheu...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-
From: Andrey Smirnov
Add minimal code needed to allow upstream Linux guest to boot.
Cc: Peter Maydell
Cc: Jason Wang
Cc: Philippe Mathieu-Daudé
Cc: Marcel Apfelbaum
Cc: Michael S. Tsirkin
Cc: qemu-devel@nongnu.org
Cc: qemu-...@nongnu.org
Cc: yurov...@gmail.com
Reviewed-by: Peter Maydell
Si
From: Ard Biesheuvel
This implements emulation of the new SM3 instructions that have
been added as an optional extension to the ARMv8 Crypto Extensions
in ARM v8.2.
Signed-off-by: Ard Biesheuvel
Message-id: 20180207111729.15737-4-ard.biesheu...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-
Make v7m_push_callee_stack() honour the MPU by using the
new v7m_stack_write() function. We return a flag to indicate
whether the pushes failed, which we can then use in
v7m_exception_taken() to cause us to handle the derived
exception correctly.
Signed-off-by: Peter Maydell
Reviewed-by: Richard
In order to support derived exceptions (exceptions generated in
the course of trying to take an exception), we need to be able
to handle prioritizing whether to take the original exception
or the derived exception.
We do this by introducing a new function
armv7m_nvic_set_pending_derived() which th
From: Ard Biesheuvel
Add support for the new ARMv8.2 SHA-3, SM3, SM4 and SHA-512 instructions to
AArch64 user mode emulation.
Signed-off-by: Ard Biesheuvel
Message-id: 20180207111729.15737-6-ard.biesheu...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
linux-user/elfl
From: Andrey Smirnov
Convert i.MX6 to use TYPE_IMX_USDHC since that's what real HW comes
with.
Cc: Peter Maydell
Cc: Jason Wang
Cc: Philippe Mathieu-Daudé
Cc: Marcel Apfelbaum
Cc: Michael S. Tsirkin
Cc: qemu-devel@nongnu.org
Cc: qemu-...@nongnu.org
Cc: yurov...@gmail.com
Reviewed-by: Philip
Handle possible MPU faults, SAU faults or bus errors when
popping register state off the stack during exception return.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 1517324542-6607-8-git-send-email-peter.mayd...@linaro.org
---
target/arm/helper.c | 115 +++
From: Andrey Smirnov
Add minimal code needed to allow upstream Linux guest to boot.
Cc: Peter Maydell
Cc: Jason Wang
Cc: Philippe Mathieu-Daudé
Cc: Marcel Apfelbaum
Cc: Michael S. Tsirkin
Cc: qemu-devel@nongnu.org
Cc: qemu-...@nongnu.org
Cc: yurov...@gmail.com
Reviewed-by: Peter Maydell
Si
From: Ard Biesheuvel
This implements emulation of the new SHA-512 instructions that have
been added as an optional extensions to the ARMv8 Crypto Extensions
in ARM v8.2.
Signed-off-by: Ard Biesheuvel
Message-id: 20180207111729.15737-2-ard.biesheu...@linaro.org
Reviewed-by: Peter Maydell
Signed
Make the load of the exception vector from the vector table honour
the SAU and any bus error on the load (possibly provoking a derived
exception), rather than simply aborting if the load fails.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 1517324542-6607-7-git-send-ema
From: Andrey Smirnov
Add code to emulate SNVS IP-block. Currently only the bits needed to
be able to emulate machine shutdown are implemented.
Cc: Peter Maydell
Cc: Jason Wang
Cc: Philippe Mathieu-Daudé
Cc: Marcel Apfelbaum
Cc: Michael S. Tsirkin
Cc: qemu-devel@nongnu.org
Cc: qemu-...@nongn
The memory writes done to push registers on the stack
on exception entry in M profile CPUs are supposed to
go via MPU permissions checks, which may cause us to
take a derived exception instead of the original one of
the MPU lookup fails. We were implementing these as
always-succeeds direct writes t
In the v8M architecture, if the process of taking an exception
results in a further exception this is called a derived exception
(for example, an MPU exception when writing the exception frame to
memory). If the derived exception happens while pushing the initial
stack frame, we must ignore any sub
From: Andrey Smirnov
Add minimal code needed to allow upstream Linux guest to boot.
Cc: Peter Maydell
Cc: Jason Wang
Cc: Philippe Mathieu-Daudé
Cc: Marcel Apfelbaum
Cc: Michael S. Tsirkin
Cc: qemu-devel@nongnu.org
Cc: qemu-...@nongnu.org
Cc: yurov...@gmail.com
Reviewed-by: Philippe Mathieu-
Currently armv7m_nvic_acknowledge_irq() does three things:
* make the current highest priority pending interrupt active
* return a bool indicating whether that interrupt is targeting
Secure or NonSecure state
* implicitly tell the caller which is the highest priority
pending interrupt by s
From: Richard Henderson
Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Message-id: 20180123035349.24538-3-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h | 12
1 file changed, 12 insertions(+)
diff --git a/tar
The code where we added the TT instruction was accidentally
missing a 'break', which meant that after generating the code
to execute the TT we would fall through to 'goto illegal_op'
and generate code to take an UNDEF insn.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Message
From: Andrey Smirnov
Add code to emulate Chipidea USB IP (used in i.MX SoCs). Tested to
work against:
-usb -drive if=none,id=stick,file=usb.img,format=raw -device \
usb-storage,bus=usb-bus.0,drive=stick
Cc: Peter Maydell
Cc: Jason Wang
Cc: Philippe Mathieu-Daudé
Cc: Marcel Apfelbaum
Cc: Mi
From: Richard Henderson
Define ZCR_EL[1-3].
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20180123035349.24538-5-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h| 5 ++
target/arm/helper.c | 131 +++
From: Richard Henderson
Save the high parts of the Zregs and all of the Pregs.
The ZCR_ELx registers are migrated via the CP mechanism.
Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Message-id: 20180123035349.24538-4-richard.hender...@linaro.org
Signed-o
Hi,
This series failed build test on s390x host. Please find the details below.
Type: series
Message-id: 20180209104546.29401-1-pbonz...@redhat.com
Subject: [Qemu-devel] [PATCH 0/4] tcg: fix dirty bitmap race with MTTCG
=== TEST SCRIPT BEGIN ===
#!/bin/bash
# Testing script will be invoked under
From: Ard Biesheuvel
This implements emulation of the new SHA-3 instructions that have
been added as an optional extensions to the ARMv8 Crypto Extensions
in ARM v8.2.
Signed-off-by: Ard Biesheuvel
Message-id: 20180207111729.15737-3-ard.biesheu...@linaro.org
Reviewed-by: Peter Maydell
Signed-o
Hi,
This series failed docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
Type: series
Message-id: 1518169992-19288-1-git-send-email-sa...@skytechnology.pl
Subject: [Qemu-devel] [PATCH v2]
From: Andrey Smirnov
Move virt's PSCI DT fixup code to arm/boot.c and set this fixup to
happen automatically for every board that doesn't mark "psci-conduit"
as disabled. This way emulated boards other than "virt" that rely on
PSIC for SMP could benefit from that code.
Cc: Peter Maydell
Cc: Jas
From: Richard Henderson
Change vfp.regs as a uint64_t to vfp.zregs as an ARMVectorReg.
The previous patches have made the change in representation
relatively painless.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20180123035349.24538-2-richa
From: Andrey Smirnov
Add enough code to emulate i.MX2 watchdog IP block so it would be
possible to reboot the machine running Linux Guest.
Cc: Peter Maydell
Cc: Jason Wang
Cc: Philippe Mathieu-Daudé
Cc: Marcel Apfelbaum
Cc: Michael S. Tsirkin
Cc: qemu-devel@nongnu.org
Cc: qemu-...@nongnu.or
From: Richard Henderson
Add both SVE exception state and vector length.
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20180123035349.24538-6-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h | 8
target/arm/translate.
The documentation for the generic loader claims that you can
set the PC for a CPU with an option of the form
-device loader,cpu-num=0,addr=0x1004
However if you try this QEMU complains:
cpu_num must be specified when setting a program counter
This is because we were testing against 0 rath
From: Christoffer Dall
KVM doesn't support emulating a GICv3 in userspace, only GICv2. We
currently attempt this anyway, and as a result a KVM guest doesn't
receive interrupts and the user is left wondering why. Report an error
to the user if this particular combination is requested.
Signed-of
On Fri, 9 Feb 2018 15:10:46 +0800
jiangyiwen wrote:
> Hi Eric and Greg,
>
> I encountered the similar problem with create-unlink-getattr idiom.
> I use the testcase that create-unlink-setattr idiom, and I see the
> bug is reported at https://bugs.launchpad.net/qemu/+bug/1336794.
> Then I also se
The code that reads the qcow2 snapshot table takes the offset and size
of all snapshots' L1 table without doing any kind of checks.
Although qcow2_snapshot_load_tmp() does verify that the table size is
valid, the table offset is not checked at all. On top of that there
are several other code paths
On Fri, Feb 09, 2018 at 09:41:41AM +0100, Paolo Bonzini wrote:
> On 08/02/2018 19:12, Eduardo Habkost wrote:
> > On Thu, Feb 08, 2018 at 05:44:20PM +0800, Wanpeng Li wrote:
> >> From: Wanpeng Li
> >>
> >> Add PV_DEDICATED hint cpuid feature bit.
> >>
> > [...]
> >> diff --git a/target/i386/cpu.c b
On 9 February 2018 at 05:03, Markus Armbruster wrote:
> The following changes since commit 008a51bbb343972dd8cf09126da8c3b87f4e1c96:
>
> Merge remote-tracking branch 'remotes/famz/tags/staging-pull-request' into
> staging (2018-02-08 14:31:51 +)
>
> are available in the git repository at:
>
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