Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180219024555.26467-1-s...@shealevy.com
Subject: [Qemu-devel] [PATCH v2] linux-user: Support f_flags in statfs when
available.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=b
On 17 February 2018 at 18:22, Richard Henderson
wrote:
> Signed-off-by: Richard Henderson
> ---
> target/arm/translate-sve.c | 132
> +
> target/arm/sve.decode | 22 +++-
> 2 files changed, 153 insertions(+), 1 deletion(-)
>
> diff --git a/t
From: Aleksandar Markovic
Make sure BQL is held for all interrupt requests.
For MTTCG-enabled configurations, handling soft and hard interrupts
between vCPUs must be properly locked. By acquiring BQL, make sure
all paths triggering an IRQ are synchronized.
Signed-off-by: Miodrag Dinic
Signed-o
From: Miodrag Dinic
While testing mttcg VP0 could get stuck in a loop waiting for other
VPs to come up (which never actually happens). To fix this, kick VPs
while they are being powered up by Cluster Power Controller in an
async task which is triggered once the host thread is being spawned.
Sign
From: Aleksandar Markovic
Introduce MTTCG-enabled QEMU builds for mips32, mipsn32, and mips64.
Signed-off-by: Miodrag Dinic
Signed-off-by: Aleksandar Markovic
---
configure | 3 +++
target/mips/cpu.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/configure b/configure
index ed
From: Leon Alrae
Completely rewrite conditional stores handling. Use cmpxchg.
This eliminates need for separate implementations of SC instruction
emulation for user and system emulation.
Signed-off-by: Leon Alrae
Signed-off-by: Miodrag Dinic
Signed-off-by: Aleksandar Markovic
Reviewed-by: Ri
From: Leon Alrae
Do only virtual addresses comaprisons in LL/SC sequence emulations.
Until this patch, physical addresses had been compared in SC part of
LL/SC sequence, even though such comparisons could be avoided. Getting
rid of them allows throwing away SC helpers and having common SC
implem
From: Goran Ferenc
Hold BQL whenever mips_vpe_wake() is invoked.
Without this patch, MIPS MT with MTTCG enabled triggers an abort in
tcg_handle_interrupt() due to an unlocked access to cpu_interrupt().
This patch makes sure that the BQL is held in this case.
Signed-off-by: Goran Ferenc
Signed-
From: Aleksandar Markovic
v1->v2:
- patches #3 and #4 are squashed into one to avoid bisect breaking
- improved locking features in patch #5 (formerly #6)
- commit messages reviewed and improved
- rebased to the latest code
This series introduces MTTCG feature for MIPS targets by addin
On 17 February 2018 at 18:22, Richard Henderson
wrote:
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper-sve.h| 21 +
> target/arm/helper.h| 1 +
> target/arm/sve_helper.c| 77
> ++
> target/arm/translate-sve.c
On 17 February 2018 at 18:22, Richard Henderson
wrote:
> Signed-off-by: Richard Henderson
> -void trans_PTEST(DisasContext *s, arg_PTEST *a, uint32_t insn)
> +static void trans_PTEST(DisasContext *s, arg_PTEST *a, uint32_t insn)
> {
Should this be in a previous patch?
> int nofs = pred_f
On 02/22/2018 10:18 AM, Alberto Garcia wrote:
L2 entries for compressed clusters have a field that indicates the
number of sectors used to store the data in the image.
That's however not the size of the compressed data itself, just the
number of sectors where that data is located. The actual dat
On 02/22/2018 10:23 AM, Alberto Garcia wrote:
On Thu 22 Feb 2018 04:59:22 PM CET, Eric Blake wrote:
sector_offset = coffset & 511;
csize = nb_csectors * 512 - sector_offset;
[...]
+assert(csize < 2 * s->cluster_size);
I think it should be <=
If sector
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180220180325.29818-1-peter.mayd...@linaro.org
Subject: [Qemu-devel] [PATCH 00/19] Add Cortex-M33 and mps2-an505 board model
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
On 22 February 2018 at 19:03, wrote:
> WARNING: line over 80 characters
> #530: FILE: include/hw/misc/iotkit-secctl.h:14:
> + *
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
> WARNING: line over 80 characters
> #660: FILE: include/hw/arm/iotkit.h:13:
> + *
On 02/22/2018 09:28 AM, Peter Maydell wrote:
> On 17 February 2018 at 18:22, Richard Henderson
> wrote:
>> Enable ARM_FEATURE_SVE for the generic "any" cpu.
>>
>> Signed-off-by: Richard Henderson
>> ---
>> target/arm/cpu.c | 7 +++
>> target/arm/cpu64.c | 1 +
>> 2 files changed, 8 inserti
On 02/22/2018 10:04 AM, Peter Maydell wrote:
> On 17 February 2018 at 18:22, Richard Henderson
> wrote:
>> These were the instructions that were stubbed out when
>> introducing the decode skeleton.
>>
>> Signed-off-by: Richard Henderson
>> ---
>> target/arm/translate-sve.c | 50
>> +
On 02/22/2018 06:13 AM, Christian Borntraeger wrote:
>
>
> On 02/21/2018 06:39 PM, Cornelia Huck wrote:
>> On Tue, 20 Feb 2018 16:05:54 +0100
>> David Hildenbrand wrote:
>>
>>> On 20.02.2018 15:57, Cornelia Huck wrote:
On Tue, 20 Feb 2018 13:16:37 +0100
David Hildenbrand wrote:
Hi,
This series failed build test on ppcbe host. Please find the details below.
Type: series
Message-id: 1518702707-7077-1-git-send-email-vsement...@virtuozzo.com
Subject: [Qemu-devel] [PATCH 0/9] nbd block status base:allocation
=== TEST SCRIPT BEGIN ===
#!/bin/bash
# Testing script will be inv
On 02/22/2018 10:20 AM, Peter Maydell wrote:
> On 17 February 2018 at 18:22, Richard Henderson
> wrote:
>> Signed-off-by: Richard Henderson
>> ---
>> target/arm/translate-sve.c | 132
>> +
>> target/arm/sve.decode | 22 +++-
>> 2 files chang
On 02/22/2018 10:55 AM, Peter Maydell wrote:
>> +# Three prediate operand, with governing predicate, flag setting
>
> Three what?
Feh, typo for predicate. But more verbosely,
Three operands that are predicates, plus another predicate operand which
"governs" the operation (I believe that's the l
On 02/22/2018 09:23 AM, Alex Bennée wrote:
>
> Richard Henderson writes:
>
>> On 02/08/2018 09:31 AM, Alex Bennée wrote:
>>> +maxpasses = hp ? (is_q ? 8 : 4) : (is_q ? 4 : 2);
>>
>> (8 << is_q) >> size
>>
>> ?
>
> Hmm I'm not so sure about this. While mine is longer form at least
On 02/22/2018 11:45 AM, Collin L. Walling wrote:
On 02/22/2018 10:44 AM, Christian Borntraeger wrote:
On 02/22/2018 04:40 PM, Collin L. Walling wrote:
On 02/22/2018 07:23 AM, Viktor Mihajlovski wrote:
On 22.02.2018 12:51, Christian Borntraeger wrote:
Series
Acked-by: Christian Borntraeger
On Thu, Feb 15, 2018 at 3:05 PM, Alistair Francis wrote:
> On Mon, Feb 5, 2018 at 10:44 AM, Alistair Francis
> wrote:
>> Ensure that the post write hook is called during reset. This allows us
>> to rely on the post write functions instead of having to call them from
>> the reset() function.
>>
>>
Allow write operations on behalf of the initiator. The
precursor to write is the sending of the write metadata
that consists of the ObjectInfo dataset. This patch introduces
a flag that is set when the responder is ready to receive
write data based on a previous SendObjectInfo operation by
the init
v5:
4/5,5/5: Add check for the RO bit and set response to STORE_READ_ONLY
v4:
4/5: Remove getumask and set default permissions to 0644
5/5: Remove usb_mtp_object_lookup_name out of #ifdef CONFIG_INOTIFY1
Test compilation on freebsd
v3:
3/5: Add a property that sets r/w to on/off (de
Fix a possible null dereference when deleting a folder and
its contents. An ignored event might be received for its contents
after the parent folder is deleted which will return a null object.
Signed-off-by: Bandan Das
---
hw/usb/dev-mtp.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(
The response to a SendObjectInfo consists of the storageid,
parent obejct handle and the handle reserved for the new
incoming object
Signed-off-by: Bandan Das
---
hw/usb/dev-mtp.c | 50 +++---
1 file changed, 27 insertions(+), 23 deletions(-)
diff --g
This patch implements a dummy ObjectInfo structure so that
it's easy to typecast the incoming data. If the metadata is
valid, write_pending is set. Also, the incoming filename
is utf-16, so, instead of depending on external libraries, just
implement a simple function to get the filename
Signed-off
Write of existing objects by the initiator is acheived by
making a temporary buffer with the new changes, deleting the
old file and then writing a new file with the same name.
Also, add a "readonly" property which needs to be set to false
for deletion to work.
Signed-off-by: Bandan Das
---
hw/u
On 02/22/2018 08:41 AM, Peter Maydell wrote:
> On 16 February 2018 at 21:56, Richard Henderson
> wrote:
>> Depending on the currently selected size of the SVE vector registers,
>> we can either store the data within the "standard" allocation, or we
>> may beedn to allocate additional space with an
On 02/22/2018 01:11 PM, Peter Maydell wrote:
ERROR: line over 90 characters
#54: FILE: hw/arm/mps2-tz.c:21:
+ *
https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2
Does anybody better with perl and more familiar with checkpatch's
internals feel l
Sometimes, we want to refer to really long URLs, but checkpatch
balks, and we have to manually bypass the check. URL shorterners
may be nice at reducing long links, but it's hard to guarantee the
shortened link will live as long as the real target, and it is
also nice to see the original target wi
On 02/22/2018 03:58 PM, Eric Blake wrote:
Sometimes, we want to refer to really long URLs, but checkpatch
balks, and we have to manually bypass the check. URL shorterners
s/shorterners/shorteners/
(Is it bad when I spell-check my own patches?)
may be nice at reducing long links, but it's ha
On 2018-02-21 14:53, Kevin Wolf wrote:
> This allows, given a QemuOpts for a QemuOptsList that was merged from
> multiple QemuOptsList, to only consider those options that exist in one
> specific list. Block drivers need this to separate format-layer create
> options from protocol-level options.
>
On 2018-02-21 14:53, Kevin Wolf wrote:
> Basic test for merging two QemuOptsLists.
>
> Signed-off-by: Kevin Wolf
> ---
> tests/test-qemu-opts.c | 128
> +
> 1 file changed, 128 insertions(+)
Reviewed-by: Max Reitz
signature.asc
Description: O
On 2018-02-21 14:53, Kevin Wolf wrote:
> Signed-off-by: Kevin Wolf
> ---
> tests/test-qemu-opts.c | 125
> +
> 1 file changed, 125 insertions(+)
Reviewed-by: Max Reitz
signature.asc
Description: OpenPGP digital signature
Hi,
The first patch in this series attempts to correct the slave selection when
using the striping functionality in the QSPI. The second patch in the series
updates the QIOR/QIOR4 commands to use 8 dummy cycles in the QSPI for matching
Micron (Numonyx) flashes (the default target flash type of the
Use 8 dummy cycles (4 dummy bytes) with the QIOR/QIOR4 commands in legacy mode
for matching what is expected by Micron (Numonyx) flashes (the default target
flash type of the QSPI).
Signed-off-by: Francisco Iglesias
---
hw/ssi/xilinx_spips.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Assert only the lower cs on bus 0 and upper cs on bus 1 when both buses and
chip selects are enabled (e.g reading/writing with stripe).
Signed-off-by: Francisco Iglesias
---
hw/ssi/xilinx_spips.c | 42 ++
1 file changed, 38 insertions(+), 4 deletions(-)
d
On Thu, Feb 22, 2018 at 19:31:39 +0100, Aleksandar Markovic wrote:
> From: Leon Alrae
>
> Completely rewrite conditional stores handling. Use cmpxchg.
>
> This eliminates need for separate implementations of SC instruction
> emulation for user and system emulation.
>
> Signed-off-by: Leon Alrae
On Thu, Feb 22, 2018 at 2:28 PM, Francisco Iglesias
wrote:
> Use 8 dummy cycles (4 dummy bytes) with the QIOR/QIOR4 commands in legacy mode
> for matching what is expected by Micron (Numonyx) flashes (the default target
> flash type of the QSPI).
>
> Signed-off-by: Francisco Iglesias
Tested on X
On Thu, Feb 22, 2018 at 2:28 PM, Francisco Iglesias
wrote:
> Assert only the lower cs on bus 0 and upper cs on bus 1 when both buses and
> chip selects are enabled (e.g reading/writing with stripe).
>
> Signed-off-by: Francisco Iglesias
> ---
> hw/ssi/xilinx_spips.c | 42
On Thu, Feb 22, 2018 at 17:33:27 -0500, Emilio G. Cota wrote:
> Here are some numbers I just gathered for qht-bench, feel
> free to include them in this commit's log:
>
> mipsel-linux-user tests/qht-bench -d 5 -n 1 -u 20 -g 1
> Host: AMD Opteron(tm) Processor 6376
Ob
On 2018-02-21 14:53, Kevin Wolf wrote:
> A few block drivers will need to rename .bdrv_create options for their
> QAPIfication, so let's have a helper function for that.
>
> Signed-off-by: Kevin Wolf
> ---
> include/qapi/qmp/qdict.h | 6 +++
> qobject/qdict.c | 34 ++
> t
On 2018-02-21 14:53, Kevin Wolf wrote:
> We'll use a separate source file for image creation, and we need to
> check there whether the requested driver is whitelisted.
>
> Signed-off-by: Kevin Wolf
> ---
> include/block/block.h | 1 +
> block.c | 2 +-
> 2 files changed, 2 insertio
On 2018-02-21 14:53, Kevin Wolf wrote:
> This adds a synchronous x-blockdev-create QMP command that can create
> qcow2 images on a given node name.
>
> We don't want to block while creating an image, so this is not the final
> interface in all aspects, but BlockdevCreateOptionsQcow2 and
> .bdrv_co
On 2018-02-21 14:53, Kevin Wolf wrote:
> This adds the .bdrv_co_create driver callback to gluster, which enables
> image creation over QMP.
>
> Signed-off-by: Kevin Wolf
> ---
> qapi/block-core.json | 18 ++-
> block/gluster.c | 135
> ++
On 2018-02-21 14:53, Kevin Wolf wrote:
> If we want to include the invalid option name in the error message, we
> can't free the string earlier than that.
>
> Signed-off-by: Kevin Wolf
> ---
> block/rbd.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Max Reitz
signa
On 2018-02-21 14:53, Kevin Wolf wrote:
> The code to establish an RBD connection is duplicated between open and
> create. In order to be able to share the code, factor out the code from
> qemu_rbd_open() as a first step.
>
> Signed-off-by: Kevin Wolf
> ---
> block/rbd.c | 100
>
On 02/21/2018 07:53 AM, Kevin Wolf wrote:
A few block drivers will need to rename .bdrv_create options for their
QAPIfication, so let's have a helper function for that.
Signed-off-by: Kevin Wolf
---
include/qapi/qmp/qdict.h | 6 +++
qobject/qdict.c | 34 ++
tests/che
On 2018-02-21 14:53, Kevin Wolf wrote:
> Instead of the QemuOpts in qemu_rbd_connect(), we want to use QAPI
> objects. As a preparation, fetch those options directly from the QDict
> that .bdrv_open() supports in the rbd driver and that are not in the
> schema.
>
> Signed-off-by: Kevin Wolf
> ---
On 2018-02-23 00:13, Max Reitz wrote:
> On 2018-02-21 14:53, Kevin Wolf wrote:
>> Instead of the QemuOpts in qemu_rbd_connect(), we want to use QAPI
>> objects. As a preparation, fetch those options directly from the QDict
>> that .bdrv_open() supports in the rbd driver and that are not in the
>> s
On 02/21/2018 07:53 AM, Kevin Wolf wrote:
This adds a synchronous x-blockdev-create QMP command that can create
qcow2 images on a given node name.
We don't want to block while creating an image, so this is not the final
interface in all aspects, but BlockdevCreateOptionsQcow2 and
.bdrv_co_create
On 02/21/2018 07:53 AM, Kevin Wolf wrote:
We'll use a separate source file for image creation, and we need to
check there whether the requested driver is whitelisted.
Signed-off-by: Kevin Wolf
---
include/block/block.h | 1 +
block.c | 2 +-
2 files changed, 2 insertions(+), 1
On 2018-02-21 14:53, Kevin Wolf wrote:
> With the conversion to a QAPI options object, the function is now
> prepared to be used in a .bdrv_co_create implementation.
>
> Signed-off-by: Kevin Wolf
> ---
> block/rbd.c | 102
> +++-
> 1 file
On 2018-02-21 14:53, Kevin Wolf wrote:
> This adds the .bdrv_co_create driver callback to rbd, which enables
> image creation over QMP.
>
> Signed-off-by: Kevin Wolf
> ---
> qapi/block-core.json | 19 ++-
> block/rbd.c | 146
> ++-
>
On 02/21/2018 07:53 AM, Kevin Wolf wrote:
This adds the .bdrv_co_create driver callback to file, which enables
image creation over QMP.
Signed-off-by: Kevin Wolf
Reviewed-by: Max Reitz
---
qapi/block-core.json | 20 +-
block/file-posix.c | 77 ++
I suppose the first word after the colon in your subject is supposed to
be "assign" and not what it currently is (which is something I am not
going to repeat!). :-)
On 2018-02-21 14:53, Kevin Wolf wrote:
> Now that the options are already available in qemu_rbd_open() and not
> only parsed in qemu_
On 02/21/2018 07:54 AM, Kevin Wolf wrote:
Most callers have their own checks, but something like this should also
be checked centrally. As it happens, x-blockdev-create can pass negative
image sizes to format drivers (because there is no QAPI type that would
reject negative numbers) and triggers
On 2018-02-21 14:53, Kevin Wolf wrote:
> This is almost exactly the same code. The differences are that
> qemu_rbd_connect() supports BlockdevOptionsRbd.server and that the cache
> mode is set explicitly.
>
> Supporting 'server' is a welcome new feature for image creation.
> Caching is disabled by
On 2018-02-21 14:53, Kevin Wolf wrote:
> The "redundacy" option for Sheepdog image creation is currently a string
> that can encode one or two integers depending on its format, which at
> the same time implicitly selects a mode.
>
> This patch turns it into a QAPI union and converts the string int
From: Dave Airlie
Due to a kernel bug we can never increase the size of capability
set 1, so introduce a new capability set in parallel, old userspace
will continue to use the old set, new userspace will start using
the new one when it detects a fixed kernel.
v2: don't use a define from virglren
ull-decode-20180222
for you to fetch changes up to 568ae7efae7e4b90e213049efb8b6e4e12b47ca3:
scripts: Add decodetree.py (2018-02-22 15:44:07 -0800)
Add decodetree.py
--
To be used to decode ARM SVE, but could be used for any fixed-width ISA.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
scripts/decodetree.py| 1062 ++
tests/Makefile.include |9 +-
tests/decode/check.sh|
On 2018-02-21 14:53, Kevin Wolf wrote:
> This adds the .bdrv_co_create driver callback to sheepdog, which enables
> image creation over QMP.
>
> Signed-off-by: Kevin Wolf
> ---
> qapi/block-core.json | 24 +-
> block/sheepdog.c | 240
> +++---
Hi,
This series failed docker-build@min-glib build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
Type: series
Message-id: 20180221015035.22964-1-airl...@gmail.com
Subject: [Qemu-devel] [PATCH] virtio-gpu-3d: ad
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 2018034702.15705-1-airl...@gmail.com
Subject: [Qemu-devel] [PATCH] virtio-gpu-3d: add support for second capability
set (v3)
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=
Add Michael Clark, Palmer Dabbelt, Sagar Karandikar and Bastian
Koppelmann as RISC-V Maintainers.
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Signed-off-by: Michael Clark
---
MAINTAINERS | 11 +++
1 file changed, 11 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
Define RISC-V ELF machine EM_RISCV 243
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Signed-off-by: Michael Clark
---
include/elf.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index e8a515c..8e457fc 100644
--- a/include/elf.h
+++ b/include
Add CPU state header, CPU definitions and initialization routines
Reviewed-by: Richard Henderson
Signed-off-by: Michael Clark
---
target/riscv/cpu.c | 391 +
target/riscv/cpu.h | 256 +
target/riscv/cpu_bits.h | 4
Helper routines for FPU instructions and NaN definitions.
Reviewed-by: Richard Henderson
Signed-off-by: Michael Clark
---
fpu/softfloat-specialize.h | 7 +-
target/riscv/fpu_helper.c | 375 +
2 files changed, 379 insertions(+), 3 deletions(-)
crea
Implements the physical memory protection extension as specified in
Privileged ISA Version 1.10.
PMP (Physical Memory Protection) is as-of-yet unused and needs testing.
The SiFive verification team have PMP test cases that will be run.
Nothing currently depends on PMP support. It would be prefera
GDB Register read and write routines.
Reviewed-by: Richard Henderson
Signed-off-by: Michael Clark
---
target/riscv/gdbstub.c | 64 ++
1 file changed, 64 insertions(+)
create mode 100644 target/riscv/gdbstub.c
diff --git a/target/riscv/gdbstub.c
This adds RISC-V into the build system enabling the following targets:
- riscv32-softmmu
- riscv64-softmmu
- riscv32-linux-user
- riscv64-linux-user
This adds defaults configs for RISC-V, enables the build for the RISC-V
CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh'
scri
The RISC-V HTIF (Host Target Interface) console device requires access
to the symbol table to locate the 'tohost' and 'fromhost' symbols.
Signed-off-by: Michael Clark
---
hw/core/loader.c | 18 --
include/hw/elf_ops.h | 34 +-
include/hw/loader
QEMU RISC-V Emulation Support (RV64GC, RV32GC)
This is hopefully the "fix remaining issues in-tree" release.
This version the RISC-V patch series contains cleanups and adds locking to
the interrupt handling code and enables MTTCG. Fedora have been performing
MTTCG-enabled SMP package builds using
Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate
register reads made by the SDK BSP.
Signed-off-by: Michael Clark
---
hw/riscv/sifive_prci.c | 95 ++
include/hw/riscv/sifive_prci.h | 43 +++
2 files changed, 138
This provides a RISC-V Board compatible with the the SiFive U500 SDK.
The following machine is implemented:
- 'sifive_u500'; CLINT, PLIC, UART, device-tree
Signed-off-by: Michael Clark
---
hw/riscv/sifive_u500.c | 339 +
include/hw/riscv/sifive_u5
Implementation of linux user emulation for RISC-V.
Reviewed-by: Richard Henderson
Signed-off-by: Michael Clark
---
linux-user/elfload.c | 22 +++
linux-user/main.c | 99 +
linux-user/riscv/syscall_nr.h | 287 ++
Holds the state of a heterogenous array of RISC-V hardware threads.
Reviewed-by: Richard Henderson
Signed-off-by: Michael Clark
---
hw/riscv/riscv_hart.c | 95 +++
include/hw/riscv/riscv_hart.h | 45
2 files changed, 140 inser
TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU
RISC-V code generator has complete coverage for the Base ISA v2.2,
Privileged ISA v1.9.1 and Privileged ISA v1.10:
- RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
- RISC-V Instruction Set Manual Volume II: Privile
RISC-V machine with device-tree, 16550a UART and VirtIO MMIO.
The following machine is implemented:
- 'virt'; CLINT, PLIC, 16550A UART, VirtIO MMIO, device-tree
Signed-off-by: Michael Clark
---
hw/riscv/virt.c | 376
include/hw/riscv/virt
RISC-V machines compatble with Spike aka riscv-isa-sim, the RISC-V
Instruction Set Simulator. The following machines are implemented:
- 'spike_v1.9'; HTIF console, config-string, Privileged ISA Version 1.9.1
- 'spike_v1.10'; HTIF console, device-tree, Privileged ISA Version 1.10
Signed-off-by: Mi
Privileged control and status register helpers and page fault handling.
Reviewed-by: Richard Henderson
Signed-off-by: Michael Clark
---
target/riscv/helper.c| 504
target/riscv/helper.h| 78 ++
target/riscv/op_helper.c | 656
Test finisher memory mapped device used to exit simulation.
Signed-off-by: Michael Clark
---
hw/riscv/sifive_test.c | 99 ++
include/hw/riscv/sifive_test.h | 48
2 files changed, 147 insertions(+)
create mode 100644 hw/riscv/s
The RISC-V disassembler has no dependencies outside of the 'disas'
directory so it can be applied independently. The majority of the
disassembler is machine-generated from instruction set metadata:
- https://github.com/michaeljclark/riscv-meta
Expected checkpatch errors for consistency and brevit
HTIF (Host Target Interface) provides console emulation for QEMU. HTIF
allows identical copies of BBL (Berkeley Boot Loader) and linux to run
on both Spike and QEMU. BBL provides HTIF console access via the
SBI (Supervisor Binary Interface) and the linux kernel SBI console.
The HTIT chardev implem
The CLINT (Core Local Interruptor) device provides real-time clock, timer
and interprocessor interrupts based on SiFive's CLINT specification.
Signed-off-by: Michael Clark
---
hw/riscv/sifive_clint.c | 260
include/hw/riscv/sifive_clint.h | 56 ++
QEMU model of the UART on the SiFive E300 and U500 series SOCs.
BBL supports the SiFive UART for early console access via the SBI
(Supervisor Binary Interface) and the linux kernel SBI console.
The SiFive UART implements the pre qom legacy interface consistent
with the 16550a UART in 'hw/char/seri
The PLIC (Platform Level Interrupt Controller) device provides a
parameterizable interrupt controller based on SiFive's PLIC specification.
Signed-off-by: Michael Clark
---
hw/riscv/sifive_plic.c | 511 +
include/hw/riscv/sifive_plic.h | 91 ++
This provides a RISC-V Board compatible with the the SiFive E300 SDK.
The following machine is implemented:
- 'sifive_e300'; CLINT, PLIC, UART, AON, GPIO, QSPI, PWM
Signed-off-by: Michael Clark
---
hw/riscv/sifive_e300.c | 233 +
include/hw/riscv/
When porting our RTOS from QEMU 2.8 to 2.10/2.11, I ran into a problem
where 16-bit writes to the "bochs dispi interface" were being reported
differently depending on whether or not "-icount" was given to QEMU.
For example, info mtree:
...
11000500-11000515 (prio 0, i/o): bochs dispi interface
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1519344729-73482-1-git-send-email-...@sifive.com
Subject: [Qemu-devel] [PATCH v6 00/23] RISC-V QEMU Port Submission
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total
From: Dave Airlie
Due to a kernel bug we can never increase the size of capability
set 1, so introduce a new capability set in parallel, old userspace
will continue to use the old set, new userspace will start using
the new one when it detects a fixed kernel.
v2: don't use a define from virglren
On 2018.02.22 10:30:55 +0100, Gerd Hoffmann wrote:
> Hi,
>
> > Nice! Seems to be the last missing gap for local spice with cursor
> > dmabuf support, we'll do more testing on that for sure. Btw, another
> > method might be to add direct cursor dmabuf passing for spice as gl
> > output, is that c
On Thu, Feb 22, 2018 at 03:50:47PM +, Daniel P. Berrangé wrote:
> On Thu, Feb 22, 2018 at 06:01:19PM +0800, Peter Xu wrote:
> > On Wed, Feb 21, 2018 at 04:00:07PM +, Stefan Hajnoczi wrote:
> > > On Wed, Jan 24, 2018 at 01:39:43PM +0800, Peter Xu wrote:
> > > > @@ -4034,12 +4044,29 @@ static
On Thu, 02/22 10:18, Shea Levy wrote:
> Hello,
>
> These tabs match the existing style of linux-user/syscall.h, should I
> remove them?
>
In practice, following the style of the surrounding code is usually preferred,
and we ignore these errors in such cases.
Fam
On 2018.02.22 09:59:17 -0700, Alex Williamson wrote:
> On Thu, 22 Feb 2018 15:46:17 +
> Peter Maydell wrote:
>
> > On 22 February 2018 at 15:37, Gerd Hoffmann wrote:
> > > On Mon, Feb 19, 2018 at 12:14:55PM +0100, Gerd Hoffmann wrote:
> > >> vfio display support wants disable hotplug for c
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180222195740.12726-1-...@redhat.com
Subject: [Qemu-devel] [PATCH v5 0/5] Initial write support for MTP objects
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(
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