[added Markus to Cc for his view on options]
vandersonmr writes:
> Added -execfreq to enable execution frequency counting and dump
> all the TB's addresses and their execution frequency at the end
> of the execution.
>
> Signed-off-by: vandersonmr
This works well enough but we are going to
Philippe Mathieu-Daudé writes:
> Group Aarch64 objects together, TCG related ones at the bottom.
> This will help when restricting TCG-only objects.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
> ---
> target/arm/Makefile.objs | 5 +++--
> 1 file changed, 3
Philippe Mathieu-Daudé writes:
> Since commit 8c06fbdf36b checkpatch.pl enforce a new multiline
> comment syntax. Since we'll move this code around, fix its style
> first.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
> ---
> target/arm/helper.c| 213
Philippe Mathieu-Daudé writes:
> Group SOFTMMU objects together.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
> ---
> target/arm/Makefile.objs | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target/arm/Makefile.objs
On Thu, 30 May 2019 10:33:16 +0200
Igor Mammedov wrote:
> Changes since v3:
> - simplify series by dropping idea of showing property values in
> "qom-list-properties"
> and use MachineInfo in QAPI schema instead
>
> Changes since v2:
> - taking in account previous review, implement a
The SIOCGSTAMP symbol was previously defined in the
asm-generic/sockios.h header file. QEMU sees that header
indirectly via sys/socket.h
In linux kernel commit 0768e17073dc527ccd18ed5f96ce85f9985e9115
the asm-generic/sockios.h header no longer defines SIOCGSTAMP.
Instead it provides only
Commit 9fb6eb7ca50c added the declaration of xics_spapr_connect(), which
has no implementation and no users.
This is a leftover from a previous iteration of this patch. Drop it.
Signed-off-by: Greg Kurz
---
include/hw/ppc/xics_spapr.h |1 -
1 file changed, 1 deletion(-)
diff --git
Switch to using the connect/disconnect terminology like we already do for
XIVE.
Signed-off-by: Greg Kurz
---
hw/intc/xics_kvm.c |2 +-
hw/ppc/spapr_irq.c |2 +-
include/hw/ppc/xics_spapr.h |2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git
Philippe Mathieu-Daudé writes:
> While it might be normal to disable PSCI on KVM, I doubt the
> VFP helpers are correct ;)
>
> Anyway this allow to link the binary and run a KVM guest.
But also:
/home/alex/lsrc/qemu.git/target/arm/helper.c: In function ‘S1_ptw_translate’:
On Mon, Jun 17, 2019 at 01:48:59PM +, Roman Kagan wrote:
> On Sat, Jun 15, 2019 at 05:05:05PM -0300, Eduardo Habkost wrote:
> > The current default value for hv-spinlocks is 0x (meaning
> > "never retry"). However, the value is stored as a signed
> > integer, making the getter of the
Stop using cpu_F0s for the Neon f32/s32 VCVT operations.
Since this is the last user of cpu_F0s in the Neon 2rm-op
loop, we can remove the handling code for it too.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
Message-id:
Stop using cpu_F0s in the Neon VCVT fixed-point operations.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
Message-id: 20190613163917.28589-10-peter.mayd...@linaro.org
---
target/arm/translate.c | 62 +++---
1
In several places cut and paste errors meant we were using the wrong
type for the 'arg' struct in trans_ functions called by the
decodetree decoder, because we were using the _sp version of the
struct in the _dp function. These were harmless, because the two
structs were identical and so
Hi,
I finally came around to port TriCore to the "new" translate_loop
infrastructure. This is neccessary such that TriCore can be used in the upcoming
plugin API [1].
Cheers,
Bastian
[1] (https://lists.gnu.org/archive/html/qemu-devel/2019-06/msg03165.html)
Bastian Koppelmann (3):
The GICv3 specification says that the GICD_TYPER.SecurityExtn bit
is RAZ if GICD_CTLR.DS is 1. We were incorrectly making it RAZ
if the security extension is unsupported. "Security extension
unsupported" always implies GICD_CTLR.DS == 1, but the guest can
also set DS on a GIC which does support
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 117 +++--
1 file changed, 74 insertions(+), 43 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index b4e332777a..f3b297639a 100644
---
* Peng Tao (tao.p...@linux.alibaba.com) wrote:
> By removing the share ram check, qemu is able to migrate
> to private destination ram when x-ignore-shared capability
> is on. Then we can create multiple destination VMs based
> on the same source VM.
>
> This changes the x-ignore-shared migration
Hi Connie,
On 6/17/19 12:10 PM, Cornelia Huck wrote:
> Use the new helper.
>
> Signed-off-by: Cornelia Huck
Reviewed-by: Eric Auger
Thanks
Eric
> ---
> v1->v2:
> - Don't go overboard with deleting, and keep the get_irq_info part.
> ---
> hw/vfio/ccw.c | 51
On 6/17/19 6:10 AM, Cornelia Huck wrote:
> Use the new helper.
>
> Signed-off-by: Cornelia Huck
Nice simplification!
Reviewed-by: Eric Farman
> ---
> v1->v2:
> - Don't go overboard with deleting, and keep the get_irq_info part.
(Sorry about that. :)
> ---
> hw/vfio/ccw.c | 51
On Mon, 17 Jun 2019 12:10:36 +0200
Cornelia Huck wrote:
> Use the new helper.
>
> Signed-off-by: Cornelia Huck
> ---
> v1->v2:
> - Don't go overboard with deleting, and keep the get_irq_info part.
> ---
> hw/vfio/ccw.c | 51 +--
> 1 file
On Mon, 2019-06-10 at 19:18 +0530, Aarushi Mehta wrote:
> Aborts when sqe fails to be set as sqes cannot be returned to the ring.
>
> Signed-off-by: Aarushi Mehta
> ---
> MAINTAINERS | 7 +
> block/Makefile.objs | 3 +
> block/io_uring.c| 314
On Mon, 2019-06-10 at 19:18 +0530, Aarushi Mehta wrote:
> Signed-off-by: Aarushi Mehta
> Reviewed-by: Stefan Hajnoczi
> ---
> MAINTAINERS | 1 +
> stubs/Makefile.objs | 1 +
> stubs/io_uring.c| 32
> 3 files changed, 34 insertions(+)
> create mode
On Sun, 16 Jun 2019 at 23:05, Richard Henderson
wrote:
>
> Check page flags before letting an invalid pc cause a SIGSEGV.
>
> Prepare for eventially validating PROT_EXEC. The current wrinkle being
> that we have a problem with our implementation of signals. We should
> be using a vdso like the
On Sat, Jun 15, 2019 at 05:05:05PM -0300, Eduardo Habkost wrote:
> The current default value for hv-spinlocks is 0x (meaning
> "never retry"). However, the value is stored as a signed
> integer, making the getter of the hv-spinlocks QOM property
> return -1 instead of 0x.
>
> Fix
Make xics_kvm_disconnect() able to undo the changes of a partial execution
of xics_kvm_connect() and use it to perform rollback.
Note that kvmppc_define_rtas_kernel_token(0) never fails, no matter the
RTAS call has been defined or not.
Signed-off-by: Greg Kurz
---
hw/intc/xics_kvm.c | 11
Philippe Mathieu-Daudé writes:
> In the next commit we will move exception handling routines to
> v7m_helper, so this function will be called from 2 different
> files. Declare it inlined in the "internals.h" header.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
> ---
>
at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20190617
for you to fetch changes up to 1120827fa182f0e76226df7ffe7a86598d1df54f:
target/arm: Only implement doubles if the FPU supports them (2019-06-17
15:15:06 +0100
On Mon, Jun 17, 2019 at 3:11 PM Daniel P. Berrangé wrote:
>
> The SIOCGSTAMP symbol was previously defined in the
> asm-generic/sockios.h header file. QEMU sees that header
> indirectly via sys/socket.h
>
> In linux kernel commit 0768e17073dc527ccd18ed5f96ce85f9985e9115
> the
The architecture permits FPUs which have only single-precision
support, not double-precision; Cortex-M4 and Cortex-M33 are
both like that. Add the necessary checks on the MVFR0 FPDP
field so that we UNDEF any double-precision instructions on
CPUs like this.
Note that even if FPDP==0 the insns
On Mon, Jun 17, 2019 at 07:09:59AM +0200, Philippe Mathieu-Daudé wrote:
[...]
>
> We get cpu names with suffix:
>
> $ arm-softmmu/qemu-system-arm -M netduino2 -cpu arm926
> qemu-system-arm: Invalid CPU type: arm926-arm-cpu
> The valid types are: cortex-m3-arm-cpu, cortex-m4-arm-cpu
>
> I
We want to use vfp_expand_imm() in the AArch32 VFP decode;
move it from the a64-only header/source file to the
AArch32 one (which is always compiled even for AArch64).
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
Message-id:
On 6.6.19. 18:46, Richard Henderson wrote:
On 6/6/19 5:15 AM, Stefan Brankovic wrote:
+tcg_gen_addi_i64(result, sh, 7);
+for (i = 7; i >= 1; i--) {
+tcg_gen_shli_i64(tmp, sh, i * 8);
+tcg_gen_or_i64(result, result, tmp);
+tcg_gen_addi_i64(sh, sh, 1);
+}
On 6.6.19. 19:13, Richard Henderson wrote:
On 6/6/19 5:15 AM, Stefan Brankovic wrote:
Stefan Brankovic (8):
target/ppc: Optimize emulation of lvsl and lvsr instructions
target/ppc: Optimize emulation of vsl and vsr instructions
target/ppc: Optimize emulation of vpkpx instruction
Am 11.06.2019 um 20:02 hat Andrey Shinkevich geschrieben:
> The Valgrind tool reports about an uninitialised memory usage when the
> initialization is actually not needed. For example, the buffer 'buf'
> instantiated on a stack of the function guess_disk_lchs().
I would be careful with calling
Commit cd219eb1e55 added the read-zeroes option for the null-co and
null-aio block driver, but forgot to add them to the QAPI schema.
Therefore, this option wasn't available in -blockdev and blockdev-add
until now.
Add the missing option in the schema to make it available there, too.
Le 17/06/2019 à 13:40, Daniel P. Berrangé a écrit :
> The SIOCGSTAMP symbol was previously defined in the
> asm-generic/sockios.h header file. QEMU sees that header
> indirectly via
>
>sys/socket.h
> -> bits/socket.h
> -> asm/socket.h
> -> asm-generic/socket.h
>
On 6/17/19 7:09 AM, Kevin Wolf wrote:
>>>
>>> Hmm, don't you think that blk_co_pcache sends NBD_CMD_CACHE if called on
>>> nbd driver?
>>> I didn't implement it. But may be I should..
>>>
>>> May aim was only to avoid extra allocation and unnecessary reads. But if we
>>> implement
>>>
vandersonmr writes:
> This is the first series of patches related to the TCGCodeQuality GSoC project
> More at https://wiki.qemu.org/Features/TCGCodeQuality
>
> It adds an option to instrument TBs and collects their execution frequency.
> The execution frequency is then store/accumulated in an
On 17/06/2019 15:25, Greg Kurz wrote:
> kvm_kernel_irqchip is set by xics_kvm_init() which is always called after
> icp_realize() since commit 3f777abc7107 "spapr/irq: add KVM support to the
> 'dual' machine".
I think we still need it for CPU hotplug.
C.
> This is thus dead code. Drop it.
>
>
On Mon, 17 Jun 2019 15:46:14 +0200
Cédric Le Goater wrote:
> On 17/06/2019 15:25, Greg Kurz wrote:
> > kvm_kernel_irqchip is set by xics_kvm_init() which is always called after
> > icp_realize() since commit 3f777abc7107 "spapr/irq: add KVM support to the
> > 'dual' machine".
>
> I think we
Philippe Mathieu-Daudé writes:
> This function is now only called within op_helper.c.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
(although if we move the tlb related bits that might be different)
> ---
> target/arm/internals.h | 3 ---
> target/arm/op_helper.c | 5
On 17/06/2019 15:46, Greg Kurz wrote:
> Switch to using the connect/disconnect terminology like we already do for
> XIVE.
>
> Signed-off-by: Greg Kurz
Reviewed-by: Cédric Le Goater
Thanks,
C.
> ---
> hw/intc/xics_kvm.c |2 +-
> hw/ppc/spapr_irq.c |2 +-
>
Philippe Mathieu-Daudé writes:
> Since we'll move this code around, fix its style first.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
> ---
> target/arm/translate.c | 11 ++-
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git
On 17/06/2019 15:46, Greg Kurz wrote:
> There is no need to rollback anything at this point, so just return an
> error.
>
> Signed-off-by: Greg Kurz
Reviewed-by: Cédric Le Goater
Thanks,
C.
> ---
> hw/intc/xics_kvm.c |2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff
On Mon, Jun 17, 2019 at 10:36:54AM +0300, Sam Eiderman wrote:
> So overall, WDYT?
> Keep it extendible for a low price of ABI + “bootdevices” name.
> Or go strict and rename to “bios-geometries”?
If we add another qemu to firmware interface I think the interface
should be documented. I also
14.06.2019 23:03, Max Reitz wrote:
> On 14.06.19 18:22, Vladimir Sementsov-Ogievskiy wrote:
>> 14.06.2019 15:57, Max Reitz wrote:
>>> On 14.06.19 11:04, Vladimir Sementsov-Ogievskiy wrote:
13.06.2019 18:57, Max Reitz wrote:
> On 29.05.19 17:46, Vladimir Sementsov-Ogievskiy wrote:
>>
Am 13.06.2019 um 11:52 hat Vladimir Sementsov-Ogievskiy geschrieben:
> 11.06.2019 21:02, Andrey Shinkevich wrote:
> > The Valgrind uses the exported variable TMPDIR and fails if the
> > directory does not exist. Let us exclude such a test case from
> > being run under the Valgrind.
> >
> >
Philippe Mathieu-Daudé writes:
> Group KVM objects together.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
> ---
> target/arm/Makefile.objs | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/target/arm/Makefile.objs
On 6.6.19. 22:43, Richard Henderson wrote:
On 6/6/19 5:15 AM, Stefan Brankovic wrote:
+/*
+ * We use this macro if one instruction is realized with direct
+ * translation, and second one with helper.
+ */
+#define GEN_VXFORM_TRANS_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1)\
+static void
On 6/17/19 1:42 PM, Alex Bennée wrote:
> Philippe Mathieu-Daudé writes:
>
>> From: Samuel Ortiz
>>
>> In preparation for supporting TCG disablement on ARM, we move most
>> of TCG related v7m helpers and APIs into their own file.
>>
>> Signed-off-by: Samuel Ortiz
>> [PMD: Patch rewritten]
>>
On 6.6.19. 20:34, Richard Henderson wrote:
On 6/6/19 5:15 AM, Stefan Brankovic wrote:
+for (i = 0; i < 2; i++) {
+if (i == 0) {
+/* Get high doubleword element of vB in avr. */
+get_avr64(avr, VB, true);
+} else {
+/* Get low doubleword
On 17.06.19 13:57, Kevin Wolf wrote:
> Commit cd219eb1e55 added the read-zeroes option for the null-co and
> null-aio block driver, but forgot to add them to the QAPI schema.
> Therefore, this option wasn't available in -blockdev and blockdev-add
> until now.
>
> Add the missing option in the
On Mon, 17 Jun 2019 21:12:05 +1000
David Gibson wrote:
> On Mon, Jun 17, 2019 at 10:25:10AM +0200, Greg Kurz wrote:
> 65;5603;1c> On Wed, 12 Jun 2019 12:07:23 +1000
> > Alexey Kardashevskiy wrote:
> >
> > > At the moment the rtas's Makefile uses generic QEMU rules which means
> > > that when
On Mon, 2019-06-10 at 19:19 +0530, Aarushi Mehta wrote:
> Signed-off-by: Aarushi Mehta
> Reviewed-by: Stefan Hajnoczi
> ---
> blockdev.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/blockdev.c b/blockdev.c
> index 3f44b891eb..a2a5b32604 100644
> --- a/blockdev.c
Philippe Mathieu-Daudé writes:
> The Security State helpers are now only called within v7m_helper.c.
> Remove them from "internals.h".
>
> Signed-off-by: Philippe Mathieu-Daudé
This does seem a little round the houses, but whatever:
Reviewed-by: Alex Bennée
> ---
>
Patchew URL: https://patchew.org/QEMU/20190617131103.1413-1-berra...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v2] linux-user: fix to handle variably sized
SIOCGSTAMP with new kernels
Type: series
The SSE-200 hardware has configurable integration settings which
determine whether its two CPUs have the FPU and DSP:
* CPU0_FPU (default 0)
* CPU0_DSP (default 0)
* CPU1_FPU (default 1)
* CPU1_DSP (default 1)
Similarly, the IoTKit has settings for its single CPU:
* CPU0_FPU (default 1)
*
Remove some old constructs from NEON_2RM_VCVT_F16_F32 code:
* don't use cpu_F0s
* don't use tcg_gen_ld_f32
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
Message-id: 20190613163917.28589-11-peter.mayd...@linaro.org
---
target/arm/translate.c |
On 6/16/19 1:41 PM, Hongbo Zhang wrote:
> On Mon, 3 Jun 2019 at 18:54, Philippe Mathieu-Daudé wrote:
>>
>> Hi Hongbo, Ard.
>>
>> On 4/18/19 6:04 AM, Hongbo Zhang wrote:
>>> Following the previous patch, this patch adds peripheral devices to the
>>> newly introduced SBSA-ref machine.
>>>
>>>
08.06.2019 1:26, John Snow wrote:
>
>
> On 6/3/19 8:00 AM, Vladimir Sementsov-Ogievskiy wrote:
>> Hi all!
>>
>> Here is block-dirty-bitmap-remove transaction action.
>>
>> It is used to do transactional movement of the bitmap (which is
>> possible in conjunction with merge command).
Am 17.06.2019 um 13:20 hat Vladimir Sementsov-Ogievskiy geschrieben:
> 06.06.2019 17:07, Vladimir Sementsov-Ogievskiy wrote:
> > 06.06.2019 16:55, Eric Blake wrote:
> >> On 6/6/19 8:48 AM, Vladimir Sementsov-Ogievskiy wrote:
> >>> Hi all!
> >>>
> >>> Here is small new io API: blk_co_pcache, which
On Thu, Jun 13, 2019 at 12:47:21PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> 11.06.2019 21:02, Andrey Shinkevich wrote:
> > The Valgrind tool fails to manage its termination when QEMU raises the
> > signal SIGKILL. Lets exclude such test cases from running under the
> > Valgrind because there
On Tue, Jun 11, 2019 at 09:02:10PM +0300, Andrey Shinkevich wrote:
> Processes are dying harder under the Valgring. It results in counting
> the dying process as a newborn one. Make it sure that old NBD job get
> finished before starting a new one.
I think this log message is confusing.
The
Am 17.06.2019 um 15:09 hat Eric Blake geschrieben:
> On 6/17/19 7:09 AM, Kevin Wolf wrote:
>
> >>>
> >>> Hmm, don't you think that blk_co_pcache sends NBD_CMD_CACHE if called on
> >>> nbd driver?
> >>> I didn't implement it. But may be I should..
> >>>
> >>> May aim was only to avoid extra
On Mon, Jun 17, 2019 at 02:53:55PM +0200, Kevin Wolf wrote:
> Am 17.06.2019 um 14:18 hat Roman Kagan geschrieben:
> > On Mon, Jun 17, 2019 at 01:15:04PM +0200, Kevin Wolf wrote:
> > > Am 11.06.2019 um 20:02 hat Andrey Shinkevich geschrieben:
> > > > The Valgrind tool fails to manage its
This allows errors happening there to be propagated up to spapr_irq,
just like XIVE already does.
Signed-off-by: Greg Kurz
---
hw/intc/xics.c| 39 ++-
hw/intc/xics_kvm.c| 37 ++---
include/hw/ppc/xics.h |6
On Tue, 2019-06-11 at 10:51 +0100, Stefan Hajnoczi wrote:
> On Mon, Jun 10, 2019 at 07:19:03PM +0530, Aarushi Mehta wrote:
> > +static bool qemu_luring_poll_cb(void *opaque)
> > +{
> > +LuringState *s = opaque;
> > +struct io_uring_cqe *cqes;
> > +
> > +if (io_uring_peek_cqe(>ring, )
On 17/06/2019 16:10, Greg Kurz wrote:
> So that no one is tempted to drop that code, which is never called
> for cold plugged CPUs.
>
> Signed-off-by: Greg Kurz
Reviewed-by: Cédric Le Goater
Thanks,
C.
On 17/06/2019 15:46, Greg Kurz wrote:
> Commit 9fb6eb7ca50c added the declaration of xics_spapr_connect(), which
> has no implementation and no users.
>
> This is a leftover from a previous iteration of this patch. Drop it.
>
> Signed-off-by: Greg Kurz
Reviewed-by: Cédric Le Goater
Thanks,
Allow the DSP extension to be disabled via a CPU property for
M-profile CPUs. (A and R-profile CPUs don't have this extension
as a defined separate optional architecture extension, so
they don't need the property.)
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by:
The AArch32 VMOV (immediate) instruction uses the same VFP encoded
immediate format we already handle in vfp_expand_imm(). Use that
function rather than hand-decoding it.
Suggested-by: Richard Henderson
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Tested-by: Philippe
this gets rid of the copied fields of TriCore's DisasContext and now
uses the shared DisasContextBase, which is necessary for the conversion
to translate_loop.
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 98 +-
1 file changed, 44
The GIC ID registers cover an area 0x30 bytes in size
(12 registers, 4 bytes each). We were incorrectly decoding
only the first 0x20 bytes.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20190524124248.28394-2-peter.mayd...@linaro.org
---
hw/intc/arm_gicv3_dist.c
On 6.6.19. 22:38, Richard Henderson wrote:
On 6/6/19 5:15 AM, Stefan Brankovic wrote:
Optimize Altivec instruction vclzh (Vector Count Leading Zeros Halfword).
This instruction counts the number of leading zeros of each halfword element
in source register and places result in the appropriate
17.06.2019 15:09, Kevin Wolf wrote:
> Am 17.06.2019 um 13:20 hat Vladimir Sementsov-Ogievskiy geschrieben:
>> 06.06.2019 17:07, Vladimir Sementsov-Ogievskiy wrote:
>>> 06.06.2019 16:55, Eric Blake wrote:
On 6/6/19 8:48 AM, Vladimir Sementsov-Ogievskiy wrote:
> Hi all!
>
> Here is
On Sun, 16 Jun 2019 at 22:36, Michael S. Tsirkin wrote:
>
> The following changes since commit f3d0bec9f80e4ed7796fffa834ba0a53f2094f7f:
>
> Merge remote-tracking branch 'remotes/maxreitz/tags/pull-block-2019-06-14'
> into staging (2019-06-14 14:46:13 +0100)
>
> are available in the Git
On Mon, Jun 17, 2019 at 01:47:48PM +0200, Laurent Vivier wrote:
> Le 17/06/2019 à 13:40, Daniel P. Berrangé a écrit :
> > The SIOCGSTAMP symbol was previously defined in the
> > asm-generic/sockios.h header file. QEMU sees that header
> > indirectly via
> >
> >sys/socket.h
> > ->
There is no need to rollback anything at this point, so just return an
error.
Signed-off-by: Greg Kurz
---
hw/intc/xics_kvm.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/intc/xics_kvm.c b/hw/intc/xics_kvm.c
index 534515143ea8..377ff88701c2 100644
---
Remove the now unused TCG globals cpu_F0s, cpu_F0d, cpu_F1s, cpu_F1d.
cpu_M0 is still used by the iwmmxt code, and cpu_V0 and
cpu_V1 are used by both iwmmxt and Neon.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
Message-id:
In the Arm kernel/initrd loading code, in some places we make the
incorrect assumption that info->ram_size can be treated as the
address of the end of RAM, as for instance when we calculate the
available space for the initrd using "info->ram_size - info->initrd_start".
This is wrong, because many
On 6/17/19 4:41 PM, Alex Bennée wrote:
>
> Philippe Mathieu-Daudé writes:
>
>> From: Samuel Ortiz
>>
>> They're not TCG specific and should be living the generic helper file
>> instead.
>>
>> Signed-off-by: Samuel Ortiz
>> Reviewed-by: Robert Bradford
>> [PMD: Rebased]
>> Signed-off-by:
Philippe Mathieu-Daudé writes:
> From: Samuel Ortiz
>
> do_interrupt, do_unaligned_access, do_transaction_failed and debug_excp
> are only relevant in the TCG context, so we should not define them
> when TCG is disabled.
>
> Signed-off-by: Samuel Ortiz
> Reviewed-by: Philippe Mathieu-Daudé
On Fri, 14 Jun 2019 at 21:25, Laszlo Ersek wrote:
>
> The following changes since commit f3d0bec9f80e4ed7796fffa834ba0a53f2094f7f:
>
> Merge remote-tracking branch 'remotes/maxreitz/tags/pull-block-2019-06-14'
> into staging (2019-06-14 14:46:13 +0100)
>
> are available in the Git repository
06.06.2019 17:07, Vladimir Sementsov-Ogievskiy wrote:
> 06.06.2019 16:55, Eric Blake wrote:
>> On 6/6/19 8:48 AM, Vladimir Sementsov-Ogievskiy wrote:
>>> Hi all!
>>>
>>> Here is small new io API: blk_co_pcache, which does copy-on-read without
>>> extra buffer for read data. This means that only
The sem_timedwait function has been annotated as requiring
non-null args in latest header files from GCC snapshot
representing the future 2.30 release.
This causes configure to fail when -Werror is used:
config-temp/qemu-conf.c: In function ‘main’:
config-temp/qemu-conf.c:2:25: error: null
On Thu, Jun 13, 2019 at 12:59:53PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> 11.06.2019 21:02, Andrey Shinkevich wrote:
> > Processes are dying harder under the Valgring. It results in counting
> > the dying process as a newborn one. Make it sure that old NBD job get
> > finished before
Am 17.06.2019 um 14:18 hat Roman Kagan geschrieben:
> On Mon, Jun 17, 2019 at 01:15:04PM +0200, Kevin Wolf wrote:
> > Am 11.06.2019 um 20:02 hat Andrey Shinkevich geschrieben:
> > > The Valgrind tool fails to manage its termination when QEMU raises the
> > > signal SIGKILL. Lets exclude such test
Passing both errp and _err to functions is a recipe for messing
things up.
Since we must use _err for icp_kvm_realize(), use _err
everywhere where rollback must happen and have a single call to
error_propagate() them all. While here, add errno to the error
message.
Signed-off-by: Greg Kurz
---
In case XICS KVM setup fails, depending on the in-kernel irqchip being
required or not, QEMU used to exit or fall back to emulated XICS, and
never try to setup XICS KVM again for the machine lifetime.
This is no longer the case with the "dual" interrupt controller mode of
the spapr machine: QEMU
Philippe Mathieu-Daudé writes:
> From: Samuel Ortiz
>
> Those helpers are a software implementation of the ARM v8 memory zeroing
> op code. They should be moved to the op helper file, which is going to
> eventually be built only when TCG is enabled.
>
> Signed-off-by: Samuel Ortiz
>
Philippe Mathieu-Daudé writes:
> From: Samuel Ortiz
>
> It's only used in op_helper.c, it does not need to be exported and
> moreover it should only be build when TCG is enabled.
>
> Signed-off-by: Samuel Ortiz
> [PMD: Rebased]
> Signed-off-by: Philippe Mathieu-Daudé
> ---
>
Since Linux v3.17, the kernel's Image header includes a field image_size,
which gives the total size of the kernel including unpopulated data
sections such as the BSS). If this is present, then return it from
load_aarch64_image() as the true size of the kernel rather than
just using the size of
Switch NEON_2RM_VRINT* away from using cpu_F0s.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
Message-id: 20190613163917.28589-6-peter.mayd...@linaro.org
---
target/arm/translate.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
On Thu, 13 Jun 2019 at 22:17, Richard Henderson
wrote:
>
> On 6/13/19 7:37 AM, Peter Maydell wrote:
> > The AArch32 VTRN instruction is specified to give an UNKNOWN
> > result if Vd and Vm are the same register; avoid generating
> > this in risu output, as we already do for VUZP and VZIP.
> >
> >
Philippe Mathieu-Daudé writes:
> From: Samuel Ortiz
>
> They're not TCG specific and should be living the generic helper file
> instead.
>
> Signed-off-by: Samuel Ortiz
> Reviewed-by: Robert Bradford
> [PMD: Rebased]
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/arm/helper.c
From: Jagannathan Raman
Adds the handler to process message from QEMU,
Initialize remote process main loop, handles SYNC_SYSMEM
message by updating its "system_memory" container using
shared file descriptors received from QEMU.
Signed-off-by: John G Johnson
Signed-off-by: Elena Ufimtseva
From: Jagannathan Raman
Add memory-listener object which is used to keep the view of the RAM
in sync between QEMU and remote process.
A MemoryListener is registered for system-memory AddressSpace. The
listener sends SYNC_SYSMEM message to the remote process when memory
listener commits the
From: Elena Ufimtseva
Add a signal handler for launched remote processes and set up
the heartbit timer for remote processes.
Signed-off-by: John G Johnson
Signed-off-by: Elena Ufimtseva
Signed-off-by: Jagannathan Raman
---
hw/proxy/qemu-proxy.c | 101
From: Jagannathan Raman
Extend block_resize QMP/HMP commands to resize block devices on a remote
process.
Signed-off-by: John G Johnson
Signed-off-by: Jagannathan Raman
Signed-off-by: Elena Ufimtseva
---
Changes in v2:
- removed separate QMP/HMP command.
- extended existing QMP command
From: Elena Ufimtseva
Signed-off-by: Elena Ufimtseva
Signed-off-by: Jagannathan Raman
Signed-off-by: John G Johnson
---
Changes in v2:
- since the changes were made to use existing device/drive options,
the document was modified to reflect this.
---
docs/qemu-multiprocess.txt | 59
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