On Mon, 12 Oct 2020, Joelle van Dyne wrote:
From: osy
On iOS, we cannot allocate RWX pages without special entitlements. As a
workaround, we can a RX region and then mirror map it to a separate RX
Missing a verb here: "we can a RX region"
region. Then we can write to one region and execute
On 10/13/20 4:38 PM, Marc-André Lureau wrote:
Hi
On Tue, Oct 13, 2020 at 5:34 PM Philippe Mathieu-Daudé
mailto:phi...@redhat.com>> wrote:
On 10/13/20 1:29 AM, Joelle van Dyne wrote:
> From: osy mailto:os...@users.noreply.github.com>>
>
> We cannot access /etc/resolv.conf
Thanks for providing the link.
I'm not sure what license that is/if it is compatible with GPLv2. Can
someone provide guidance on what to update in QEMU's license? I am not
too familiar with all this license stuff.
Regarding building for iOS, as Balaton said it is possible with an OSX
host.
Copy bootinfo.h and bootinfo-mac.h from arch/m68k/include/uapi/asm/
to include/standard-headers/asm-m68k/
Imported from linx v5.9 but didn't change since v4.14 (header update)
and since v4.10 (content update).
Signed-off-by: Laurent Vivier
---
hw/m68k/bootinfo.h|
On Fri, Oct 2, 2020 at 8:35 AM Alistair Francis
wrote:
>
> Currently we log interrupts and exceptions using the trace backend in
> riscv_cpu_do_interrupt(). We also log exceptions using the interrupt log
> mask (-d int) in riscv_raise_exception().
>
> This patch converts riscv_cpu_do_interrupt()
On Fri, Oct 9, 2020 at 3:29 AM Bin Meng wrote:
>
> On Fri, Oct 2, 2020 at 11:55 PM Alistair Francis
> wrote:
>
> Please put some commit message to explain why the changes are necessary.
I have added a commit message.
>
> >
> > Signed-off-by: Alistair Francis
> > ---
> >
Hello,
Not related to this patch but while you're at it could you please take
those patches that are already reviewed by you from this series as well?
http://patchwork.ozlabs.org/project/qemu-devel/list/?series=186439
That would help cleaning up my tree and see which patches still need
On Tue, Oct 13, 2020 at 01:46:11PM -0400, Eduardo Habkost wrote:
> On Sun, Oct 11, 2020 at 11:18:59PM -0400, Cleber Rosa wrote:
> > On Sat, Oct 10, 2020 at 09:54:16AM +0200, Philippe Mathieu-Daudé wrote:
> > > On 10/9/20 10:29 PM, Eduardo Habkost wrote:
> > > > Add a simple test case that will run
On Tue, 13 Oct 2020, Stefan Hajnoczi wrote:
On Mon, Oct 12, 2020 at 04:29:35PM -0700, Joelle van Dyne wrote:
From: osy
iOS does not support ucontext natively for aarch64 and the sigaltstack is
also unsupported (even worse, it fails silently, see:
https://openradar.appspot.com/13002712 )
As a
The APIs link correctly but are NOPs on Intel machines. I think full
testing would require Apple Silicon or emulation. Is there precedent
for any other platform/feature that requires hardware specific
features?
-j
On Tue, Oct 13, 2020 at 7:09 AM Peter Maydell wrote:
>
> On Tue, 13 Oct 2020 at
On 10/12/20 8:37 AM, Peter Maydell wrote:
> Generate a "break" instead, so that decode flow behaves
> as required for this nested group case.
>
> Suggested-by: Richard Henderson
> Signed-off-by: Peter Maydell
> ---
> scripts/decodetree.py | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
The mac_via device does not currently follow the rules for init() and realize()
in
regard to the mos6522 child devices. These child devices must be initialised
using
object_initialize_child() within the mac_via init() function and then realized
as
part of the mac_via realize() function. Move
On Tue, 13 Oct 2020, Daniel P. Berrangé wrote:
On Tue, Oct 13, 2020 at 08:16:46AM -0700, Joelle van Dyne wrote:
I will start a separate conversation of UTM's license compatibility.
Regarding the patch, would some sort of warning message in configure
(if building as a shared library) regarding
On 10/12/20 8:37 AM, Peter Maydell wrote:
> The BLX immediate insn in the Thumb encoding always performs
> a switch from Thumb to Arm state. This would be totally useless
> in M-profile which has no Arm decoder, and so the instruction
> does not exist at all there. Make the encoding UNDEF for
On 10/12/20 8:37 AM, Peter Maydell wrote:
> The t32 decode has a group which represents a set of insns
> which overlap with B_cond_thumb because they have [25:23]=111
> (which is an invalid condition code field for the branch insn).
> This group is currently defined using the {} overlap-OK syntax,
On 13/10/20 16:38, Claudio Fontana wrote:
> +void bdrv_bh_schedule_oneshot(AioContext *ctx, QEMUBHFunc *cb, void *opaque)
> +{
> +if (replay_events_enabled()) {
> +replay_bh_schedule_oneshot_event(ctx, cb, opaque);
> +} else {
> +aio_bh_schedule_oneshot(ctx, cb, opaque);
>
On 13/10/20 19:17, Claudio Fontana wrote:
>> This is definitely better, but I'll defer to Kevin with respect to the
>> naming of the function; having a bdrv_* function that has nothing to do
>> with the block layer is still smelly of a sub-optimal API, and I'm not
>> sure why the API change
From: Klaus Jensen
This adds support for reporting the Deallocated or Unwritten Logical
Block error (DULBE). This requires tracking the allocated/deallocated
status of all logical blocks.
Introduce a bitmap that does this. The bitmap is always intialized to
all ones (aka, all blocks are
On 6/29/20 8:55 PM, BALATON Zoltan wrote:
Half of the occurances already use get_system_memory() directly
instead of sysmem variable, convert the two other uses to
get_system_memory() too which seems to be more common and drop the
variable.
Signed-off-by: BALATON Zoltan
Reviewed-by: Mark
On Tue, Oct 13, 2020 at 04:41:06PM +0200, BALATON Zoltan wrote:
> On Tue, 13 Oct 2020, Daniel P. Berrangé wrote:
> > On Mon, Oct 12, 2020 at 04:29:33PM -0700, Joelle van Dyne wrote:
> > > From: osy
> > >
> > > On iOS, we cannot fork() new processes, so the best way to load QEMU into
> > > an
>
On Sat, Oct 10, 2020 at 12:31:28PM -0500, Richard Henderson wrote:
> The linux microblaze port only implements rt signal handing,
> not the old style. This allows our linux-test to pass for mb,
> if you have a cross-compiler available for the build.
Tested-by: Edgar E. Iglesias
Reviewed-by:
On 10/13/20 6:26 PM, Mark Cave-Ayland wrote:
The mac_via device does not currently follow the rules for init() and realize()
in
regard to the mos6522 child devices. These child devices must be initialised
using
object_initialize_child() within the mac_via init() function and then realized
as
There is a slight performance penalty for using "bulletproof JIT".
Since that is not required if you have the proper entitlements (only
if you're Apple or jailbroken on iOS; available to regular developers
on Apple Silicon macOS), we want the flexibility to disable it.
-j
On Tue, Oct 13, 2020 at
On Sun, Oct 11, 2020 at 11:18:59PM -0400, Cleber Rosa wrote:
> On Sat, Oct 10, 2020 at 09:54:16AM +0200, Philippe Mathieu-Daudé wrote:
> > On 10/9/20 10:29 PM, Eduardo Habkost wrote:
> > > Add a simple test case that will run QEMU directly (without QMP)
> > > just to check for crashes when using
On 13.10.20 14:33, Chen Qun wrote:
> A default value is provided for the variable 'bitmap_name' to avoid compiler
> warning.
>
> The compiler show warning:
> migration/block-dirty-bitmap.c:1090:13: warning: ‘bitmap_name’
> may be used uninitialized in this function [-Wmaybe-uninitialized]
>
Generic watchdog device model has been implemented as per ARM BSAv0.9
Signed-off-by: Shashi Mallela
---
hw/arm/Kconfig | 1 +
hw/watchdog/Kconfig | 4 +
hw/watchdog/meson.build | 1 +
hw/watchdog/wdt_sbsa_gwdt.c | 346
This patch series adds watchdog timer support for SbsaQemu platform.
The watchdog timer has been implemented first based on the generic
watchdog timer specifications from ARM BSA v0.9 and then used
in the SbsaQemu reference platform
Changes in v5:
- updated irq number of gwdt in sbsa-ref since
Included the newly implemented SBSA generic watchdog device model into
SBSA platform
Signed-off-by: Shashi Mallela
---
hw/arm/sbsa-ref.c | 50 +++
1 file changed, 50 insertions(+)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index
On 10/12/20 8:37 AM, Peter Maydell wrote:
> v8.1M brings four new insns to M-profile:
> * CSEL : Rd = cond ? Rn : Rm
> * CSINC : Rd = cond ? Rn : Rm+1
> * CSINV : Rd = cond ? Rn : ~Rm
> * CSNEG : Rd = cond ? Rn : -Rm
>
> Implement these.
>
> Signed-off-by: Peter Maydell
> ---
>
On 10/13/20 5:15 AM, Bin Meng wrote:
On Sat, Oct 10, 2020 at 1:54 AM John Snow wrote:
Formalize the options used for checking the python library. You can run
mypy from the directory that mypy.ini is in by typing `mypy qemu/`.
Signed-off-by: John Snow
---
python/mypy.ini | 4
1 file
On Tue, 13 Oct 2020 at 18:10, Richard Henderson
wrote:
>
> On 10/12/20 12:56 PM, Peter Maydell wrote:
> > On Mon, 12 Oct 2020 at 16:37, Peter Maydell
> > wrote:
> > This turns out not to work, because gen_jmp() always generates
> > a goto-tb for tb exit 0, and we hit the assert() that exit 0
>
On 10/13/20 10:12 AM, Peter Maydell wrote:
> On Tue, 13 Oct 2020 at 18:10, Richard Henderson
> wrote:
>>
>> On 10/12/20 12:56 PM, Peter Maydell wrote:
>>> On Mon, 12 Oct 2020 at 16:37, Peter Maydell
>>> wrote:
>>> This turns out not to work, because gen_jmp() always generates
>>> a goto-tb for
The hstatus.GVA bit was not set if the faulting guest virtual address
was zero.
Signed-off-by: Georg Kotheimer
---
target/riscv/cpu_helper.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 904899054d..c5852ce1b7
On Tue, Oct 13, 2020 at 12:11:20PM +, Zengtao (B) wrote:
> Cc valentin
>
> > -Original Message-
> > From: Qemu-devel
> > [mailto:qemu-devel-bounces+prime.zeng=hisilicon@nongnu.org]
> > On Behalf Of Ying Fang
> > Sent: Thursday, September 17, 2020 11:20 AM
> > To:
On Oct 13 10:48, Keith Busch wrote:
> On Tue, Oct 13, 2020 at 11:04:01AM +0200, Klaus Jensen wrote:
> > On Sep 30 15:04, Keith Busch wrote:
> > > After going through the zns enabling, I notice the controller enabling
> > > is not correct. Then I just continued maked more stuff. The series, I
> > >
Signed-off-by: Laurent Vivier
---
include/hw/char/goldfish_tty.h | 36 +
hw/char/goldfish_tty.c | 265 +
hw/char/Kconfig| 3 +
hw/char/meson.build| 2 +
hw/char/trace-events | 9 ++
5 files changed, 315
The Quadra 800 machine is very limited to run linux, it manages
only 1 GiB of memory and only some specific interfaces.
The Virtual M68k Machine is based on Goldfish interfaces defined by Google
for Android simulator. It uses Goldfish-rtc (timer and RTC),
Goldfish-pic (PIC) and Goldfish-tty (for
Signed-off-by: Laurent Vivier
---
include/hw/intc/goldfish_pic.h | 28 ++
hw/intc/goldfish_pic.c | 178 +
hw/intc/Kconfig| 3 +
hw/intc/meson.build| 1 +
hw/intc/trace-events | 8 ++
5 files changed, 218
On 13/10/2020 14:38, BALATON Zoltan via wrote:
On Tue, 13 Oct 2020, Mark Cave-Ayland wrote:
Currently an object link property is used to pass a reference to the OpenPIC
into the PCI host bridge so that pci_unin_init_irqs() can connect the PCI
IRQs to the PIC itself.
This can be simplified by
On 10/12/20 8:37 AM, Peter Maydell wrote:
> v8.1M implements a new 'branch future' feature, which is a
> set of instructions that request the CPU to perform a branch
> "in the future", when it reaches a particular execution address.
> In hardware, the expected implementation is that the
On Tue, Oct 13, 2020 at 11:04:01AM +0200, Klaus Jensen wrote:
> On Sep 30 15:04, Keith Busch wrote:
> > After going through the zns enabling, I notice the controller enabling
> > is not correct. Then I just continued maked more stuff. The series, I
> > think, contains some of the less
On 6/29/20 8:55 PM, BALATON Zoltan wrote:
Fall back to load binary ROM image if loading ELF fails. This also
moves PROM_BASE and PROM_SIZE defines to board as these are matching
the ROM size and address on this board and removes the now unused
PROM_ADDR and BIOS_SIZE defines from common mac.h.
On 6/29/20 8:55 PM, BALATON Zoltan wrote:
Values not used frequently enough may not worth putting in a local
variable, especially with names almost as long as the original value
because that does not improve readability, to the contrary it makes it
harder to see what value is used. Drop a few
Hi Philippe,
On Wed, Oct 7, 2020 at 5:31 AM Philippe Mathieu-Daudé wrote:
>
> Hi Cupertino, Claudiu,
>
> On 9/30/20 10:46 PM, cupertinomira...@gmail.com wrote:
> > From: Claudiu Zissulescu
> >
> > Add the Synopsys ARC boards, arc_sim for testing, sim-hs main emulation
> > board using standard
On Fri, Oct 2, 2020 at 9:04 AM Alistair Francis
wrote:
>
> This patch fixes CID 1432800 by removing an unnecessary check.
>
> Signed-off-by: Alistair Francis
Ping!
Alistair
> ---
> hw/core/register.c | 4
> 1 file changed, 4 deletions(-)
>
> diff --git a/hw/core/register.c
On Tue, Oct 13, 2020 at 05:50:37PM +0100, Darren Kenny wrote:
> Hi Alex,
>
> This mentions the use of atexit() to perform some cleanup, but I'm not
> seeing that being added here, should it be?
The reference to atexit is strange, because it says the only way to
kill the fuzzer is SIGKILL, and
On Tue, Oct 13, 2020 at 06:47:42PM +0200, Claudio Fontana wrote:
> On 10/13/20 4:55 PM, Philippe Mathieu-Daudé wrote:
> > On 10/13/20 4:38 PM, Claudio Fontana wrote:
> >> This series now unbreaks current non-tcg builds
> >> (!CONFIG_TCG).
> >>
> >> tests Makefiles need to avoid relying on all
On 13/10/20 16:05, Jason Andryuk wrote:
> Xen was left behind when CpusAccel became mandatory and fails the assert
> in qemu_init_vcpu(). It relied on the same dummy cpu threads as qtest.
> Move the qtest cpu functions to a common location and reuse them for
> Xen.
>
> v2:
> New patch "accel:
On 10/13/20 7:12 PM, Paolo Bonzini wrote:
> On 13/10/20 16:38, Claudio Fontana wrote:
>> +void bdrv_bh_schedule_oneshot(AioContext *ctx, QEMUBHFunc *cb, void *opaque)
>> +{
>> +if (replay_events_enabled()) {
>> +replay_bh_schedule_oneshot_event(ctx, cb, opaque);
>> +} else {
>> +
xen-save-devices-state doesn't currently generate a vmdesc, so restore
always triggers "Expected vmdescription section, but got 0". This is
not a problem when restore comes from a file. However, when QEMU runs
in a linux stubdom and comes over a console, EOF is not received. This
causes a delay
this fixes non-TCG builds broken recently by replay reverse debugging.
stub the needed functions in stub/, including errors for hmp and qmp.
This includes duplicating some code in replay/, and puts the logic
for non-replay related events in the replay/ module (+ the stubs),
so this should be
From: Paolo Bonzini
remove dependency of check-block from non-native archs
Signed-off-by: Claudio Fontana
---
tests/Makefile.include | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/Makefile.include b/tests/Makefile.include
index 5aca98e60c..4037490b69 100644
---
On 10/13/20 4:38 PM, Claudio Fontana wrote:
This series now unbreaks current non-tcg builds
(!CONFIG_TCG).
tests Makefiles need to avoid relying on all non-native
archs binaries to be present,
bios-tables-test needs to skip tests that are tcg-only,
and notably the replay framework needs to
Hi Philippe,
Thank you for your time reviewing our patches.
My apologies for reacting to it so late. :-(
Once we decided to make this port we noticed that Michael Rolnik had
submitt a port for ARC700 to QEMU mailinglist.
As we tested it, we decided to use his directory structure, and for
that
I will start a separate conversation of UTM's license compatibility.
Regarding the patch, would some sort of warning message in configure
(if building as a shared library) regarding the license be wise? Or
would it pollute the output logs?
-j
On Tue, Oct 13, 2020 at 7:46 AM Daniel P. Berrangé
On 201007 1647, Dima Stepanov wrote:
> The virtio-blk fuzz target sets up and fuzzes the available virtio-blk
> queues. The implementation is based on two files:
> - tests/qtest/fuzz/virtio_scsi_fuzz.c
> - tests/qtest/virtio_blk_test.c
>
> Signed-off-by: Dima Stepanov
> ---
>
With the fuzzer, we never call main_loop_should_exit, since we manually
call main_loop_wait. This means that the only way to terminate the
fuzzer is with SIGKILL. Disable the signal handlers, so there are
reasonable ways to terminate the fuzzer and use atexit() to clean-up
after the fuzzer.
On Tue, Oct 13, 2020 at 08:16:46AM -0700, Joelle van Dyne wrote:
> I will start a separate conversation of UTM's license compatibility.
>
> Regarding the patch, would some sort of warning message in configure
> (if building as a shared library) regarding the license be wise? Or
> would it pollute
On 10/13/20 4:55 PM, Philippe Mathieu-Daudé wrote:
> On 10/13/20 4:38 PM, Claudio Fontana wrote:
>> This series now unbreaks current non-tcg builds
>> (!CONFIG_TCG).
>>
>> tests Makefiles need to avoid relying on all non-native
>> archs binaries to be present,
>>
>> bios-tables-test needs to skip
On 201013 1750, Darren Kenny wrote:
> Hi Alex,
>
> This mentions the use of atexit() to perform some cleanup, but I'm not
> seeing that being added here, should it be?
>
That sentence was not clear.. I meant that the developer can
(optionally) use atexit when writing a new fuzz-target to
On 10/12/20 12:56 PM, Peter Maydell wrote:
> On Mon, 12 Oct 2020 at 16:37, Peter Maydell wrote:
>>
>> v8.1M's "low-overhead-loop" extension has three instructions
>> for looping:
>> * DLS (start of a do-loop)
>> * WLS (start of a while-loop)
>> * LE (end of a loop)
>>
>> +static bool
On 10/13/20 7:25 PM, Paolo Bonzini wrote:
> On 13/10/20 19:17, Claudio Fontana wrote:
>>> This is definitely better, but I'll defer to Kevin with respect to the
>>> naming of the function; having a bdrv_* function that has nothing to do
>>> with the block layer is still smelly of a sub-optimal
On 10/13/20 5:51 PM, Laurent Vivier wrote:
The machine is based on Goldfish interfaces defined by Google
for Android simulator. It uses Goldfish-rtc (timer and RTC),
Goldfish-pic (PIC) and Goldfish-tty (for serial port and early tty).
The machine is created with 128 virtio-mmio bus, and they
On 10/13/20 6:59 AM, Mark Cave-Ayland wrote:
During my latest OpenBIOS boot tests I've noticed the following IDE
diagnostics failure message appearing in dmesg at Linux boot time when
booting from CDROM on both SPARC64 and PPC:
Sorry for the inconvenience.
[ 9.347342] scsi host0:
On 10/12/20 8:37 AM, Peter Maydell wrote:
> In arm_cpu_realizefn(), if the CPU has VFP or Neon disabled then we
> squash the ID register fields so that we don't advertise it to the
> guest. This code was written for A-profile and needs some tweaks to
> work correctly on M-profile:
>
> *
This series now unbreaks current non-tcg builds
(!CONFIG_TCG).
tests Makefiles need to avoid relying on all non-native
archs binaries to be present,
bios-tables-test needs to skip tests that are tcg-only,
and notably the replay framework needs to consider that
it might not be functional (or its
the tests assume TCG is available, thus breaking
for TCG-only tests, where only the TCG accelerator option
is passed to the QEMU binary.
Suggested-by: Paolo Bonzini
Acked-by: Paolo Bonzini
Signed-off-by: Claudio Fontana
---
tests/qtest/bios-tables-test.c | 10 ++
1 file changed, 10
When trapping from virt into HS mode, hstatus.SPVP was set to
the value of sstatus.SPP, as according to the specification both
flags should be set to the same value.
However, the assignment of SPVP takes place before SPP itself is
updated, which results in SPVP having an outdated value.
On Tue, 13 Oct 2020, Daniel P. Berrangé wrote:
On Tue, Oct 13, 2020 at 04:41:06PM +0200, BALATON Zoltan wrote:
On Tue, 13 Oct 2020, Daniel P. Berrangé wrote:
On Mon, Oct 12, 2020 at 04:29:33PM -0700, Joelle van Dyne wrote:
From: osy
On iOS, we cannot fork() new processes, so the best way to
The machine is based on Goldfish interfaces defined by Google
for Android simulator. It uses Goldfish-rtc (timer and RTC),
Goldfish-pic (PIC) and Goldfish-tty (for serial port and early tty).
The machine is created with 128 virtio-mmio bus, and they can
be used to use serial console, GPU, disk,
On Tue, Oct 13, 2020 at 04:49:26PM +0200, BALATON Zoltan via wrote:
> On Tue, 13 Oct 2020, Stefan Hajnoczi wrote:
> > On Mon, Oct 12, 2020 at 04:29:35PM -0700, Joelle van Dyne wrote:
> > > From: osy
> > >
> > > iOS does not support ucontext natively for aarch64 and the sigaltstack is
> > > also
Hi Alex,
This mentions the use of atexit() to perform some cleanup, but I'm not
seeing that being added here, should it be?
Thanks,
Darren.
On Tuesday, 2020-10-13 at 11:29:20 -04, Alexander Bulekov wrote:
> With the fuzzer, we never call main_loop_should_exit, since we manually
> call
On 13/10/2020 14:37, Philippe Mathieu-Daudé wrote:
On 10/13/20 1:49 PM, Mark Cave-Ayland wrote:
Currently an object link property is used to pass a reference to the Heathrow
PIC into the PCI host bridge so that grackle_init_irqs() can connect the PCI
IRQs to the PIC itself.
This can be
On Tue, 13 Oct 2020, Mark Cave-Ayland wrote:
On 13/10/2020 14:38, BALATON Zoltan via wrote:
On Tue, 13 Oct 2020, Mark Cave-Ayland wrote:
Currently an object link property is used to pass a reference to the
OpenPIC
into the PCI host bridge so that pci_unin_init_irqs() can connect the PCI
IRQs
The HLVX.WU instruction is supposed to read a machine word,
but prior to this change it read a byte instead.
Signed-off-by: Georg Kotheimer
---
target/riscv/op_helper.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
Le 13/10/2020 à 19:56, Philippe Mathieu-Daudé a écrit :
> On 10/13/20 5:51 PM, Laurent Vivier wrote:
>> The machine is based on Goldfish interfaces defined by Google
>> for Android simulator. It uses Goldfish-rtc (timer and RTC),
>> Goldfish-pic (PIC) and Goldfish-tty (for serial port and early
On 10/13/20 7:22 PM, Georg Kotheimer wrote:
The HLVX.WU instruction is supposed to read a machine word,
but prior to this change it read a byte instead.
Fixes: 8c5362acb57 ("target/riscv: Allow generating hlv/hlvx/hsv
instructions")
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by:
On 10/13/20 5:26 AM, Peter Maydell wrote:
> When using -icount, it's useful for the CPU_LOG_EXEC logging
> to include information about when cpu_io_recompile() was
> called, because it alerts the reader of the log that the
> tracing of a previous TB execution may not actually
> correspond to an
On Tue, Oct 13, 2020 at 01:19:30PM +0800, Yang Weijiang wrote:
> With more components in XSS being developed on Intel platform,
> it's necessary to clean up existing XSAVE related feature words to
> make the name clearer. It's to prepare for adding CET related support
> in following patches.
>
>
Instead of returning the unused entry address from riscv_load_firmware()
instead return the end address. Also return the end address from
riscv_find_and_load_firmware().
This tells the caller if a firmware was loaded and how big it is. This
can be used to determine the load address of the next
Allow the user to specify the main application CPU for the sifive_u
machine.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
---
include/hw/riscv/sifive_u.h | 1 +
hw/riscv/sifive_u.c | 18 +-
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git
This series allows loading a noMMU kernel using the -kernel option.
Currently if using -kernel QEMU assumes you also have firmware and loads
the kernel at a hardcoded offset. This series changes that so we only
load the kernel at an offset if a firmware (-bios) was loaded.
This series also adds a
On Mon, Oct 12, 2020 at 8:45 AM Peter Maydell wrote:
>
> The netduino2 and netduinoplus2 boards forgot to set the system_clock_scale
> global, which meant that if guest code used the systick timer in "use
> the processor clock" mode it would hang because time never advances.
>
> Set the global to
On 10/13/20 3:35 AM, Peter Maydell wrote:
> For AArch32, unlike the VCVT of integer to float, which honours the
> rounding mode specified by the FPSCR, VCVT of fixed-point to float is
> always round-to-nearest. (AArch64 fixed-point-to-float conversions
> always honour the FPCR rounding mode.)
>
>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/misc/mac_via.c | 18 +-
1 file changed, 1 insertion(+), 17 deletions(-)
diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c
index 9e64c2521fc..54088b6625a 100644
--- a/hw/misc/mac_via.c
+++ b/hw/misc/mac_via.c
@@ -362,22 +362,6 @@
On 10/13/20 1:38 PM, Peter Maydell wrote:
> * has short-vector support (eg Cortex-A9)
> * v8A, can implement FPSCR.{Stride,Len} as RAZ/WI
> * no short-vector support, Stride/Len can be written
>but the only effect is that some insns must UNDEF
>(eg Cortex-A7)
Yep.
The other thing I
v5 -> v6
- Remove zoned state persistence code. Replace position-independent
zone lists with QTAILQs.
- Close all open zones upon clearing of the controller. This is
a similar procedure to the one previously performed upon powering
up with zone persistence.
- Squash NS Types and
From: Niklas Cassel
Define the structures and constants required to implement
Namespace Types support.
Namespace Types introduce a new command set, "I/O Command Sets",
that allows the host to retrieve the command sets associated with
a namespace. Introduce support for the command set and enable
This log page becomes necessary to implement to allow checking for
Zone Append command support in Zoned Namespace Command Set.
This commit adds the code to report this log page for NVM Command
Set only. The parts that are specific to zoned operation will be
added later in the series.
All
We can easily register allocate the entire extended basic block
(in this case, the set of blocks connected by fallthru), simply
by not discarding the register state at the branch.
This does not help blocks starting with a label, as they are
reached via a taken branch, and that would require
Changes v1 -> v2:
* Rewrite documentation, with suggestions from Markus
* Try to reduce churn and keep the existing default_cpu_version
static variable
* Replace x86_cpu_class_get_alias_of() with x86_cpu_model_resolve_alias()
Link to v1:
Instead of calling x86_cpu_class_get_alias_of(), just save the
actual CPU model name in X86CPUModel and use it in `-cpu help`.
Signed-off-by: Eduardo Habkost
---
target/i386/cpu.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/target/i386/cpu.c
The QMP code was never called by *-user, and we will add
machine-type-specific code there, so add #ifdefs to make it safe.
Signed-off-by: Eduardo Habkost
---
target/i386/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
Move find_machine() from vl.c to core/machine.c and rename it to
machine_find_class(), so it can be reused by other code.
The function won't reuse the results of the previous
object_class_get_list() call like it did in vl.c, but this
shouldn't be a problem because the function is expected to be
On 10/13/20 6:25 AM, Philippe Mathieu-Daudé wrote:
> Yocto developers have expressed interest in running MIPS32
> CPU with custom number of TLB:
> https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html
>
> Help them by making the number of TLB entries a CPU property,
> keeping our
Signed-off-by: Alistair Francis
---
include/hw/riscv/boot.h | 2 ++
hw/riscv/boot.c | 9 +
2 files changed, 11 insertions(+)
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index 0acbd8aa6e..2975ed1a31 100644
--- a/include/hw/riscv/boot.h
+++
Instead of loading the kernel at a hardcoded start address, let's load
the kernel at the next alligned address after the end of the firmware.
This should have no impact for current users of OpenSBI, but will
allow loading a noMMU kernel at the start of memory.
Signed-off-by: Alistair Francis
On Tue, 13 Oct 2020 at 18:30, Richard Henderson
wrote:
> Well, the only further comment is that, in the followup, only WLS gains the IT
> block check. While I understand that's required to avoid an abort in QEMU for
> this case, all three of the insns have that case as CONSTRAINED UNPREDICTABLE.
On Tue, 13 Oct 2020 at 21:06, Richard Henderson
wrote:
> I think these two sets of masking are confusing.
> Perhaps usefully rearranged as
>
> if (!fp16) {
> val &= ~fz16;
> }
> vfp_set_fpscr_to_host(env, val);
>
> if (!m-profile) {
> vec_len = extract32(val, 16,
On 10/12/20 9:05 AM, Philippe Mathieu-Daudé wrote:
> Philippe Mathieu-Daudé (2):
> hw/mips/malta: Move gt64120 related code together
> hw/mips/malta: Use clearer qdev style
Reviewed-by: Richard Henderson
r~
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