On 8/1/22 10:10, Cédric Le Goater wrote:
Drop the use of ppc4xx_init() and duplicate a bit of code related to
clocks in the SoC realize routine. We will clean that up in the
following patches.
ppc_dcr_init simply allocates default DCR handlers for the CPU. Maybe
this could be done in model
On Mon, Aug 01, 2022 at 07:40:32AM -0700, Dave Hansen wrote:
> This patch does not belong in this series. It's not a patch to the
> kernel. This is a kernel series.
You are right.
>
> It would be much more appropriate to put a link to a separately posted
> manpage patch in the cover letter.
* Alberto Faria (afa...@redhat.com) wrote:
> Make non-void static functions whose return values are ignored by
> all callers return void instead.
>
> These functions were found by static-analyzer.py.
>
> Not all occurrences of this problem were fixed.
>
> Signed-off-by: Alberto Faria
> diff
From: "Lucas Mateus Castro (alqotel)"
Change fdiv in the same way of fadd/fsub to handle overflow/underflow if
OE/UE is set (i.e. function that receives a value to add/subtract from
the exponent if an overflow/underflow occurs).
Signed-off-by: Lucas Mateus Castro (alqotel)
---
fpu/softfloat.c
On 03/08/2022 09:25, Atish Patra wrote:
stimecmp allows the supervisor mode to update stimecmp CSR directly
to program the next timer interrupt. This CSR is part of the Sstc
extension which was ratified recently.
Signed-off-by: Atish Patra
---
target/riscv/cpu.c | 12 +
On Wed, 3 Aug 2022, Cédric Le Goater wrote:
On 8/2/22 21:18, Daniel Henrique Barboza wrote:
On 8/1/22 10:10, Cédric Le Goater wrote:
This moves all the code previously done in the ppc405ep_init() routine
under ppc405_soc_realize().
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405.h
Hi David,
On Wed, Aug 03, 2022 at 01:55:21PM +0200, David Hildenbrand wrote:
> On 02.08.22 21:00, Jason A. Donenfeld wrote:
> > In order to fully support MSA_EXT_5, we have to also support the SHA-512
> > special instructions. So implement those.
> >
> > The implementation began as something
On Wed, 3 Aug 2022 at 12:44, Daniel P. Berrangé wrote:
> Inconsistent return value checking is designed-in behaviour for
> QEMU's current Error handling coding pattern with error_abort/fatal.
Yes; I habitually mark as false-positive Coverity reports about
missing error checks where it has not
It has been deprecated since 7.0.
Signed-off-by: Cédric Le Goater
---
docs/about/deprecated.rst | 9 --
docs/about/removed-features.rst | 6 +
docs/system/ppc/embedded.rst| 1 -
hw/ppc/ppc405_boards.c | 232
MAINTAINERS
This moves all the code previously done in the ppc405ep_init() routine
under ppc405_soc_realize(). We can also adjust the number of banks now
that we have control on ppc4xx_sdram_init().
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405.h| 16 ++---
hw/ppc/ppc405_boards.c | 12 ++--
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405_boards.c | 55 +-
1 file changed, 38 insertions(+), 17 deletions(-)
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 82b51cc457fa..2900c267b7ac
Having an explicit I2C model object will help if one day we want to
add I2C devices on the bus.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405.h| 2 ++
hw/ppc/ppc405_uc.c | 10 --
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git
On 8/1/22 10:10, Cédric Le Goater wrote:
Since all clock settings are now handled at the CPC level, this changes
the SoC "sys-clk" property to be an alias on the same property in the
CPC model.
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405.h| 39 +++-
On Tue, Aug 02, 2022 at 04:38:55PM +, Sean Christopherson wrote:
> On Tue, Aug 02, 2022, Sean Christopherson wrote:
> > I think we should avoid UNMAPPABLE even on the KVM side of things for the
> > core
> > memslots functionality and instead be very literal, e.g.
> >
> >
On 8/1/22 10:10, Cédric Le Goater wrote:
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
hw/ppc/ppc405.h | 1 +
include/hw/ppc/ppc4xx.h | 28 ++
hw/ppc/ppc405_uc.c | 20 +--
hw/ppc/ppc4xx_devs.c| 120
On Wed, 3 Aug 2022, Daniel Henrique Barboza wrote:
On 8/1/22 10:10, Cédric Le Goater wrote:
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405.h| 14 ++
hw/ppc/ppc405_uc.c | 67 +-
2 files changed, 62 insertions(+), 19 deletions(-)
On Wed, Aug 03, 2022 at 12:15:20PM +0100, Richard W.M. Jones wrote:
> On Wed, Aug 03, 2022 at 12:07:19PM +0100, Alberto Faria wrote:
> > On Wed, Aug 3, 2022 at 11:46 AM Dr. David Alan Gilbert
> > wrote:
> > >
> > > * Alberto Faria (afa...@redhat.com) wrote:
> > > > Make non-void static functions
In order to fully support MSA_EXT_5, we have to also support the SHA-512
special instructions. So implement those.
The implementation began as something TweetNacl-like, and then was
adjusted to be useful here. It's not very beautiful, but it is quite
short and compact, which is what we're going
Normally, riscv_csrrw_check is called when executing Zicsr instructions.
And we can only do access control for existed CSRs. So the priority of
CSR related check, from highest to lowest, should be as follows:
1) check whether Zicsr is supported: raise RISCV_EXCP_ILLEGAL_INST if not
2) check
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405.h| 21 +++
hw/ppc/ppc405_uc.c | 50 +-
2 files changed, 44 insertions(+), 27 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index
For default root ports we have a way of accessing chassis and slot,
before root_port_realize(), via pnv_phb_attach_root_port(). For the
future user created root ports this won't be the case: we can't use
this helper because we don't have access to the PHB phb-id/chip-id
values.
In earlier patches
On 8/1/22 10:10, Cédric Le Goater wrote:
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
hw/ppc/ppc405.h| 14 +++
hw/ppc/ppc405_uc.c | 58 +++---
2 files changed, 53 insertions(+), 19 deletions(-)
diff
On 8/1/22 10:10, Cédric Le Goater wrote:
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
hw/ppc/ppc405_boards.c | 55 +-
1 file changed, 38 insertions(+), 17 deletions(-)
diff --git a/hw/ppc/ppc405_boards.c
From: "Lucas Mateus Castro (alqotel)"
As mentioned in the functions float_overflow_excp and
float_underflow_excp, the result should be adjusted as mentioned in the
ISA (subtracted 192/1536 from the exponent of the intermediate result if
an overflow occurs with OE set and added 192/1536 to the
It is an initial model to start QOMification of the PPC405 board.
QOM'ified devices will be reintroduced one by one. Start with the
memory regions, which name prefix is changed to "ppc405".
Also, initialize only one RAM bank. The second bank is a dummy one
(zero size) which is here to match the
The same rationale provided in the PHB3 bus case applies here.
Note: we could have merged both buses in a single object, like we did
with the root ports, and spare some boilerplate. The reason we opted to
preserve both buses objects is twofold:
- there's not user side advantage in doing so.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405.h| 3 ++-
hw/ppc/ppc405_uc.c | 26 +-
2 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 7d585a244d18..d29f738cd2d0 100644
We rely on the phb-id and chip-id, which are PHB properties, to assign
chassis and slot to the root port. For default devices this is no big
deal: the root port is being created under pnv_phb_realize() and the
values are being passed on via the 'index' and 'chip-id' of the
Am 03.08.2022 um 14:25 hat Peter Krempa geschrieben:
> On Wed, Jul 27, 2022 at 21:33:40 +0200, Kevin Wolf wrote:
> > Am 08.07.2022 um 06:17 hat Stefan Hajnoczi geschrieben:
> > > libblkio (https://gitlab.com/libblkio/libblkio/) is a library for
> > > high-performance disk I/O. It currently
Given that powernv9 and powernv10 uses the same pnv-phb backend, the
logic to allow user created pnv-phbs for powernv10 is already in place.
Let's flip the switch.
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/pnv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/ppc/pnv.c
Hi,
This is a rebase on top of ppc-7.2 of the previous patches sent
here:
https://lists.gnu.org/archive/html/qemu-devel/2022-07/msg01542.html
Now that we have the pnv-phb rework in the tree.
As a recap, the changes introduced in this series compared to what we've
done in "[PATCH v2 00/16]
The function assumes that we're always dealing with a PNV9_CHIP()
object. This is not the case when the pnv-phb device belongs to a
powernv10 machine.
Change pnv_phb4_get_pec() to be able to work with PNV10_CHIP() if
necessary.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb.c |
pnv_parent_qom_fixup() and pnv_parent_bus_fixup() are versions of the
helpers that were reverted by commit 9c10d86fee "ppc/pnv: Remove
user-created PHB{3,4,5} devices". They are needed to amend the QOM and
bus hierarchies of user created pnv-phbs, matching them with default
pnv-phbs.
A new helper
Just like qcow2, qed invokes its open function in its
.bdrv_co_invalidate_cache() implementation. Therefore, just like done
for qcow2 in HEAD^, update auto_backing_file only if the backing file
string in the image header differs from the one we have read before.
Signed-off-by: Hanna Reitz
---
On 8/1/22 10:10, Cédric Le Goater wrote:
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
hw/ppc/ppc405.h| 22
hw/ppc/ppc405_uc.c | 90 +++---
2 files changed, 67 insertions(+), 45 deletions(-)
diff
CC'ing Florian to get the POV of a glibc maintainer on what we've
had to do to work around this compatibility brekage.
On Tue, Aug 02, 2022 at 12:41:34PM -0400, Daniel P. Berrangé wrote:
> The latest glibc 2.36 has extended sys/mount.h so that it
> defines the FSCONFIG_* enum constants. These are
On 8/1/22 10:10, Cédric Le Goater wrote:
Signed-off-by: Cédric Le Goater
---
With the compile fix that you mentioned fixed up:
Reviewed-by: Daniel Henrique Barboza
hw/ppc/ppc405.h| 3 ++-
hw/ppc/ppc405_uc.c | 27 ++-
2 files changed, 16 insertions(+),
On Wed, Aug 03, 2022 at 11:02:50AM +0200, Cornelia Huck wrote:
> Make the links render correctly.
>
> Signed-off-by: Cornelia Huck
> ---
> README.rst | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Daniel P. Berrangé
With regards,
Daniel
--
|: https://berrange.com
Hi Eric,
On 8/3/22 6:44 PM, Eric Auger wrote:
On 8/3/22 05:01, Gavin Shan wrote:
On 8/2/22 7:41 PM, Eric Auger wrote:
On 8/2/22 08:45, Gavin Shan wrote:
There are 3 highmem IO regions as below. They can be disabled in
two situations: (a) The specific region is disabled by user. (b)
The
On Wed, Jul 27, 2022 at 21:33:40 +0200, Kevin Wolf wrote:
> Am 08.07.2022 um 06:17 hat Stefan Hajnoczi geschrieben:
> > libblkio (https://gitlab.com/libblkio/libblkio/) is a library for
> > high-performance disk I/O. It currently supports io_uring and
> > virtio-blk-vhost-vdpa with additional
On 8/3/22 13:59, BALATON Zoltan wrote:
On Wed, 3 Aug 2022, Cédric Le Goater wrote:
On 8/2/22 21:18, Daniel Henrique Barboza wrote:
On 8/1/22 10:10, Cédric Le Goater wrote:
This moves all the code previously done in the ppc405ep_init() routine
under ppc405_soc_realize().
Signed-off-by: Cédric
On Wed, Aug 03, 2022 at 02:14:58PM +0200, Jason A. Donenfeld wrote:
> s.even = (unsigned long)src;
> s.odd = (unsigned long)src_len;
> asm volatile(
> " lgr 0,%[fc]\n"
> " lgr 1,%[pba]\n"
> "0: .insn
While forcing the CPU to unrealize by hand does trigger the clean-up
code we never fully free resources because refcount never reaches
zero. This is because QOM automatically added objects without an
explicit parent to /unattached/, incrementing the refcount.
Instead of manually triggering
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc4xx_devs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 0e97347e2839..c168b4c6484a 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -175,7 +175,7 @@ static void
Add a new test to see what happens when you migrate a VM with a backing
chain that has json:{} backing file strings, which, when opened, will be
resolved to plain filenames.
Signed-off-by: Hanna Reitz
---
.../tests/backing-file-invalidation | 152 ++
qcow2_do_open() is used by qcow2_co_invalidate_cache(), i.e. may be run
on an image that has been opened before. When reading the backing file
string from the image header, compare it against the existing
bs->backing_file, and update bs->auto_backing_file only if they differ.
auto_backing_file
On 8/1/22 10:10, Cédric Le Goater wrote:
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
hw/ppc/ppc405.h| 18
hw/ppc/ppc405_uc.c | 73 --
2 files changed, 63 insertions(+), 28 deletions(-)
diff
On 8/2/22 18:24, BALATON Zoltan wrote:
On Tue, 2 Aug 2022, Daniel Henrique Barboza wrote:
On 8/1/22 10:10, Cédric Le Goater wrote:
This moves all the code previously done in the ppc405ep_init() routine
under ppc405_soc_realize().
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405.h
On 8/1/22 10:10, Cédric Le Goater wrote:
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
hw/ppc/ppc405.h| 12
hw/ppc/ppc405_uc.c | 47 +++---
2 files changed, 40 insertions(+), 19 deletions(-)
diff
Match most appropriate base platform string based on insn_flags.
Logic is aligned with aligned with set_isa() from
arch/mips/kernel/cpu-probe.c in Linux kernel.
Signed-off-by: Jiaxun Yang
Reviewed-by: Philippe Mathieu-Daudé
---
linux-user/elfload.c | 31 +++
1 file
We will use this machine as a base to define the ref405ep and possibly
the PPC405 hotfoot board as found in the Linux kernel.
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405_boards.c | 31 ---
1 file changed, 28 insertions(+), 3 deletions(-)
diff --git
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405.h| 23 +
hw/ppc/ppc405_uc.c | 80 +-
2 files changed, 73 insertions(+), 30 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405.h| 16 +++
hw/ppc/ppc405_uc.c | 71 +++---
2 files changed, 64 insertions(+), 23 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index
On Wed, Aug 03, 2022, Chao Peng wrote:
> On Fri, Jul 29, 2022 at 07:51:29PM +, Sean Christopherson wrote:
> > On Wed, Jul 06, 2022, Chao Peng wrote:
> > > @@ -1332,9 +1332,18 @@ yet and must be cleared on entry.
> > > __u64 userspace_addr; /* start of the userspace allocated memory */
> > >
On 8/1/22 10:10, Cédric Le Goater wrote:
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
hw/ppc/ppc405.h| 21 +++
hw/ppc/ppc405_uc.c | 50 +-
2 files changed, 44 insertions(+), 27 deletions(-)
On 8/3/22 11:14, Daniel Henrique Barboza wrote:
ppc_dcr_init(env, NULL, NULL);
/* CPU control */
- ppc405ep_cpc_init(env, clk_setup, s->sysclk);
+ object_property_set_link(OBJECT(>cpc), "cpu", OBJECT(>cpu),
+ _abort);
+ if
On Fri, Jul 29, 2022 at 08:58:41PM +, Sean Christopherson wrote:
> On Wed, Jul 06, 2022, Chao Peng wrote:
> > A page fault can carry the private/shared information for
> > KVM_MEM_PRIVATE memslot, this can be filled by architecture code(like
> > TDX code). To handle page fault for such access,
Hi all,
This series properly filled AT_BASE_PLATFORM of MIPS.
There is a checkpatch error about braces after if statement,
I intentionally left it for style consistency.
v2: Commit meesage rewording (philmd)
Thanks.
- Jiaxun
Jiaxun Yang (2):
linux-user: Introduce stubs for ELF
On Wed, Aug 03, 2022 at 12:07:19PM +0100, Alberto Faria wrote:
> On Wed, Aug 3, 2022 at 11:46 AM Dr. David Alan Gilbert
> wrote:
> >
> > * Alberto Faria (afa...@redhat.com) wrote:
> > > Make non-void static functions whose return values are ignored by
> > > all callers return void instead.
> > >
Marc-André Lureau writes:
> Hi
>
> On Tue, Aug 2, 2022 at 5:28 PM Markus Armbruster wrote:
>
>> Marc-André Lureau writes:
>>
>> > Hi
>> >
>> >
>> > On Tue, Jun 21, 2022 at 6:14 PM Markus Armbruster
>> > wrote:
[...]
>> >> The option name --include doesn't really tell me what it is about.
From: "Lucas Mateus Castro (alqotel)"
DO NOT MERGE
This patch adds a test to check if the add/sub of the intermediate
result when an overflow or underflow exception with the corresponding
enabling bit being set (i.e. OE/UE), but linux-user currently can't
disable MSR.FE0 and MSR.FE1 so it will
On Fri, 29 Jul 2022 at 14:09, Alberto Faria wrote:
>
> Make non-void static functions whose return values are ignored by
> all callers return void instead.
>
> These functions were found by static-analyzer.py.
>
> Not all occurrences of this problem were fixed.
>
> Signed-off-by: Alberto Faria
Hi,
On 8/3/22 15:02, Gavin Shan wrote:
> Hi Marc,
>
> On 8/3/22 5:01 PM, Marc Zyngier wrote:
>> On Wed, 03 Aug 2022 04:01:04 +0100,
>> Gavin Shan wrote:
>>> On 8/2/22 7:41 PM, Eric Auger wrote:
On 8/2/22 08:45, Gavin Shan wrote:
> There are 3 highmem IO regions as below. They can be
On Wed, Aug 03, 2022 at 01:25:34PM +0100, Peter Maydell wrote:
> On Wed, 3 Aug 2022 at 12:44, Daniel P. Berrangé wrote:
> > Inconsistent return value checking is designed-in behaviour for
> > QEMU's current Error handling coding pattern with error_abort/fatal.
>
> Yes; I habitually mark as
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405.h| 18
hw/ppc/ppc405_uc.c | 73 --
2 files changed, 63 insertions(+), 28 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405.h| 22
hw/ppc/ppc405_uc.c | 90 +++---
2 files changed, 67 insertions(+), 45 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405.h| 14 ++
hw/ppc/ppc405_uc.c | 67 +-
2 files changed, 62 insertions(+), 19 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index
On Tue, Aug 02, 2022 at 05:13:26PM +0200, Jason A. Donenfeld wrote:
> Hi Xiaoyao,
>
> On Tue, Aug 2, 2022 at 5:06 PM Jason A. Donenfeld wrote:
> >
> > Hi Xiaoyao,
> >
> > On Tue, Aug 02, 2022 at 10:53:07PM +0800, Xiaoyao Li wrote:
> > > yes, with >= 7.1, pcmc->legacy_no_rng_seed = false by
On Wed, Aug 3, 2022 at 11:46 AM Dr. David Alan Gilbert
wrote:
>
> * Alberto Faria (afa...@redhat.com) wrote:
> > Make non-void static functions whose return values are ignored by
> > all callers return void instead.
> >
> > These functions were found by static-analyzer.py.
> >
> > Not all
From: "Lucas Mateus Castro (alqotel)"
Change fmul in the same way of fadd/fsub to handle overflow/underflow if
OE/UE is set (i.e. function that receives a value to add/subtract from
the exponent if an overflow/underflow occurs).
Signed-off-by: Lucas Mateus Castro (alqotel)
---
fpu/softfloat.c
Hi Daniel,
On Wed, Aug 03, 2022 at 11:52:25AM +0100, Daniel P. Berrangé wrote:
> On Tue, Aug 02, 2022 at 05:13:26PM +0200, Jason A. Donenfeld wrote:
> > Hi Xiaoyao,
> >
> > On Tue, Aug 2, 2022 at 5:06 PM Jason A. Donenfeld wrote:
> > >
> > > Hi Xiaoyao,
> > >
> > > On Tue, Aug 02, 2022 at
Introduce a QOM property "cpu" to initialize the DCR handlers. This is
a pattern that we will reuse for the all other 405 devices needing it.
Now that all clock settings are handled at the CPC level, change the
SoC "sys-clk" property to be an alias on the same property in the CPC
model.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405.h | 1 +
include/hw/ppc/ppc4xx.h | 28 ++
hw/ppc/ppc405_uc.c | 20 +--
hw/ppc/ppc4xx_devs.c| 120 +---
4 files changed, 118 insertions(+),
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405.h| 14 +++
hw/ppc/ppc405_uc.c | 58 +++---
2 files changed, 53 insertions(+), 19 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index
Drop the use of ppc4xx_init() and duplicate a bit of code related to
clocks in the SoC realize routine. We will clean that up in the
following patches.
ppc_dcr_init() simply allocates default DCR handlers for the CPU. Maybe
this could be done in model initializer of the CPU families needing it.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405.h| 12
hw/ppc/ppc405_uc.c | 47 +++---
2 files changed, 40 insertions(+), 19 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index
Enable pnv-phb user created devices for powernv9 now that we have
everything in place.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb.c | 2 +-
hw/pci-host/pnv_phb4_pec.c | 6 --
hw/ppc/pnv.c | 2 ++
3 files changed, 7 insertions(+), 3 deletions(-)
diff
The PHB4 backend relies on a link with the corresponding PEC element.
This is trivial to do during machine_init() time for default devices,
but not so much for user created ones.
pnv_phb4_get_pec() is a small variation of the function that was
reverted by commit 9c10d86fee "ppc/pnv: Remove
On Wed, Aug 03, 2022 at 03:11:48PM +0200, Jason A. Donenfeld wrote:
> Thanks for the info. Very helpful. Looking into it now.
So interestingly, this is not a new issue. If you pass any type of setup
data, OVMF appears to be doing something unusual and passing 0x
for all the entries,
When enabling user created PHBs (a change reverted by commit 9c10d86fee)
we were handling PHBs created by default versus by the user in different
manners. The only difference between these PHBs is that one will have a
valid phb3->chip that is assigned during pnv_chip_power8_realize(),
while the
The bulk of the work was already done by previous patches.
Use defaults_enabled() to determine whether we need to create the
default devices or not.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb.c | 9 +++--
hw/ppc/pnv.c | 6 ++
2 files changed, 13
On 8/1/22 10:10, Cédric Le Goater wrote:
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
hw/ppc/ppc405.h| 23 +
hw/ppc/ppc405_uc.c | 80 +-
2 files changed, 73 insertions(+), 30 deletions(-)
diff
On 8/1/22 10:10, Cédric Le Goater wrote:
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
hw/ppc/ppc405.h| 16 +++
hw/ppc/ppc405_uc.c | 71 +++---
2 files changed, 64 insertions(+), 23 deletions(-)
diff
On 8/1/22 10:10, Cédric Le Goater wrote:
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405.h| 14 ++
hw/ppc/ppc405_uc.c | 67 +-
2 files changed, 62 insertions(+), 19 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
On 8/1/22 10:10, Cédric Le Goater wrote:
Having an explicit I2C model object will help if one day we want to
add I2C devices on the bus.
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
hw/ppc/ppc405.h| 2 ++
hw/ppc/ppc405_uc.c | 10 --
2 files
On Fri, Jul 29, 2022 at 07:02:12PM +, Sean Christopherson wrote:
> On Wed, Jul 06, 2022, Chao Peng wrote:
> > The sync mechanism between mmu_notifier and page fault handler employs
> > fields mmu_notifier_seq/count and mmu_notifier_range_start/end. For the
> > to be added private memory, there
On Fri, Jul 29, 2022 at 07:51:29PM +, Sean Christopherson wrote:
> On Wed, Jul 06, 2022, Chao Peng wrote:
> > @@ -1332,9 +1332,18 @@ yet and must be cleared on entry.
> > __u64 userspace_addr; /* start of the userspace allocated memory */
> >};
> >
> > + struct
AT_BASE_PLATFORM is a elf auxiliary vector pointing to a string
to pass some architecture information.
See getauxval(3) man-page.
Signed-off-by: Jiaxun Yang
Reviewed-by: Philippe Mathieu-Daudé
---
linux-user/elfload.c | 29 +++--
1 file changed, 27 insertions(+), 2
Hi Marc,
On 8/3/22 5:01 PM, Marc Zyngier wrote:
On Wed, 03 Aug 2022 04:01:04 +0100,
Gavin Shan wrote:
On 8/2/22 7:41 PM, Eric Auger wrote:
On 8/2/22 08:45, Gavin Shan wrote:
There are 3 highmem IO regions as below. They can be disabled in
two situations: (a) The specific region is disabled
On Wed, Aug 03, 2022 at 11:46:26AM +0100, Dr. David Alan Gilbert wrote:
> * Alberto Faria (afa...@redhat.com) wrote:
> > Make non-void static functions whose return values are ignored by
> > all callers return void instead.
> >
> > These functions were found by static-analyzer.py.
> >
> > Not
On 02.08.22 21:00, Jason A. Donenfeld wrote:
> In order to fully support MSA_EXT_5, we have to also support the SHA-512
> special instructions. So implement those.
>
> The implementation began as something TweetNacl-like, and then was
> adjusted to be useful here. It's not very beautiful, but it
In order for hosts running inside of TCG to initialize the kernel's
random number generator, we should support the PRNO_TRNG instruction,
backed in the usual way with the qemu_guest_getrandom helper. This is
confirmed working on Linux 5.19.
Cc: Thomas Huth
Cc: David Hildenbrand
Cc: Christian
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405_boards.c | 31 +++
1 file changed, 19 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 4c269b6526a5..24ec948d22a4 100644
---
Hello,
Here is large series QOM'ifying the PPC405 board. It introduces a new
generic machine and SoC models, converts the current device models to
QOM and populates the SoC. The process is quite mechanical without too
much issues to handle. The noisy part is the initial patch introducing
the SoC
Hi,
I'm trying to find out how I can get the free PCI slots in a qtest code.
I want to assign a PCI device to a qtest-mode VM. If I assign this device
to an unavailable address in the qemu process, I get this assertion: *PCI: slot
x function y not available for z.*
However, I couldn't find a
On Wed, Aug 03, 2022 at 01:25:14AM -0700, Atish Patra wrote:
> Historically, The mtime/mtimecmp has been part of the CPU because
> they are per hart entities. However, they actually belong to aclint
> which is a MMIO device.
>
> Move them to the ACLINT device. This also emulates the real hardware
Hi,
https://gitlab.com/qemu-project/qemu/-/issues/1117 reports the following
issue:
Say you have a VM with a backing chain of images where the image
metadata contains json:{} backing file strings, which however will be
resolved to simple plain filenames when opened[1].
So when these images are
From: Babis Chalios
VM generation ID exposes a GUID inside the VM which changes every time a
VM restore is happening. Typically, this GUID is used by the guest
kernel to re-seed its internal PRNG. As a result, this value cannot be
exposed in guest user-space as a notification mechanism for VM
From: Peter Maydell
The flatload loader sets the end_code field in the image_info struct
incorrectly, due to a typo.
This is a very long-standing bug (dating all the way back to when
the bFLT loader was added in 2006), but has gone unnoticed because
(a) most people don't use bFLT binaries
(b)
On Wed, Aug 03, 2022, Chao Peng wrote:
> On Tue, Aug 02, 2022 at 04:38:55PM +, Sean Christopherson wrote:
> > On Tue, Aug 02, 2022, Sean Christopherson wrote:
> > > I think we should avoid UNMAPPABLE even on the KVM side of things for the
> > > core
> > > memslots functionality and instead be
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