On Wed, Mar 16, 2022 at 2:44 PM Mahmoud Abumandour
wrote:
>
>
> On Wed, Mar 16, 2022 at 2:40 PM Christoph Muellner
> wrote:
>
>> QEMU plugins can be loaded via command line arguments or via
>> the QEMU_PLUGIN environment variable. Currently, only the first method
>> is documented. Let's
On Wed, Mar 16, 2022 at 4:01 PM Alex Bennée wrote:
>
> Christoph Muellner writes:
>
> > QEMU plugins can be loaded via command line arguments or via
> > the QEMU_PLUGIN environment variable. Currently, only the first method
> > is documented. Let's document QEMU_PLUGIN.
> >
> > Signed-off-by:
On Fri, Feb 11, 2022 at 3:41 AM Weiwei Li wrote:
>
> 在 2022/2/11 上午12:34, Christoph Muellner 写道:
> > The RISC-V base cache management operation ISA extension has been
> > ratified [1]. This patch adds support for the defined instructions.
> >
> > The cmo.prefetch instructions are nops for QEMU
On Thu, Feb 17, 2022 at 3:15 AM Weiwei Li wrote:
>
> 在 2022/2/16 下午11:48, Christoph Muellner 写道:
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 39ffb883fc..04500fe352 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -764,6 +764,10 @@ static Property
Resend from the correct email address to get accepted by Mailman.
On Tue, Jan 18, 2022 at 4:12 PM Christoph Muellner wrote:
>
> If LQ has func3==010 and is located in the MISC-MEM opcodes,
> then it conflicts with the CBO opcode space.
> However, since LQ is specified as: "LQ is added to the
Resend from the correct email address to get accepted by Mailman.
On Tue, Jan 18, 2022 at 4:14 PM Christoph Muellner wrote:
>
> The RISC-V base cache management operation ISA extension has been
> ratified [1]. This patch adds support for the defined instructions
> and CSRs.
>
> [1]
On Tue, Jan 18, 2022 at 9:31 PM Atish Patra wrote:
>
> On Tue, Jan 18, 2022 at 8:48 AM Christoph Muellner
> wrote:
> >
> > The RISC-V base cache management operation ISA extension has been
> > ratified [1]. This patch adds support for the defined instructions
> > and CSRs.
> >
> > [1]
Hi Frédéric,
you are right, I misunderstood the "LQ is added to the MISC-MEM major
opcode" part of the spec.
I saw the encoding conflict with the CBO instructions and thought of a
bug in qemu's LQ encoding.
Philipp already highlighted that cbo.* instructions are actually LQ with rd=0.
Thanks,
On Fri, Jan 21, 2022 at 12:16 AM Atish Patra wrote:
> Virt machine uses privileged specification version 1.12 now.
> All other machine continue to use the default one defined for that
> machine unless changed to 1.12 by the user explicitly.
>
> Signed-off-by: Atish Patra
> ---
>
On Fri, Sep 29, 2023 at 2:37 PM Thomas Huth wrote:
>
> There are a bunch of RISC-V files that are currently not covered
> by the "get_maintainers.pl" script. Add them to the right sections
> in MAINTAINERS to fix this problem.
>
> Signed-off-by: Thomas Huth
Acked-by
On Thu, Jun 2, 2022 at 5:07 PM Richard Henderson
wrote:
>
> On 6/2/22 06:40, Christoph Muellner wrote:
> > diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc
> > b/target/riscv/insn_trans/trans_rvzawrs.c.inc
> > new file mode 100644
> > index 00..38b71d0085
> > --- /dev/null
> >
djustments according to a specification change
> > * Inline REQUIRE_ZAWRS() since it has only one user
> >
> > Changes since v1:
> > * Adding zawrs to the ISA string that is passed to the kernel
> >
> > Signed-off-by: Christoph Müllner
> > ---
On Thu, Sep 8, 2022 at 9:45 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 9/6/22 13:22, Christoph Muellner wrote:
> > @@ -732,6 +733,7 @@ static int ex_rvc_shifti(DisasContext *ctx, int imm)
> > #include "decode-xtheadbs.c.inc"
> > #include "decode-xtheadcmo.c.inc"
> >
On Thu, Sep 8, 2022 at 9:30 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 9/6/22 13:22, Christoph Muellner wrote:
> > +NOP_PRIVCHECK(th_sfence_vmas, REQUIRE_PRIV_MHS)
> > +NOP_PRIVCHECK(th_sync, REQUIRE_PRIV_MHSU)
> > +NOP_PRIVCHECK(th_sync_i, REQUIRE_PRIV_MHSU)
> >
On Thu, Sep 8, 2022 at 9:46 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 9/6/22 13:22, Christoph Muellner wrote:
> > +DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906,
> rv64_thead_c906_cpu_init),
> > +DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C910,
> rv64_thead_c906_cpu_init),
>
> Why
On Thu, Sep 8, 2022 at 10:56 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 9/8/22 09:23, Christoph Müllner wrote:
> >
> >
> > On Thu, Sep 8, 2022 at 9:46 AM Richard Henderson <
> richard.hender...@linaro.org
> > <mailto:richard.hender
On Tue, Jan 24, 2023 at 12:49 AM Alistair Francis
wrote:
> On Sat, Dec 24, 2022 at 4:04 AM Christoph Muellner
> wrote:
> >
> > From: Christoph Müllner
> >
> > This patch adds support for the T-Head specific extended memory
> > attributes. Similar like Svp
On Mon, Jan 23, 2023 at 11:50 PM Alistair Francis
wrote:
> On Sat, Dec 24, 2022 at 4:09 AM Christoph Muellner
> wrote:
> >
> > From: Christoph Müllner
> >
> > This patch adds support for the XTheadCmo ISA extension.
> > To avoid interfering with standard
On Tue, Jan 24, 2023 at 6:31 PM Christoph Müllner <
christoph.muell...@vrull.eu> wrote:
>
>
> On Mon, Jan 23, 2023 at 11:50 PM Alistair Francis
> wrote:
>
>> On Sat, Dec 24, 2022 at 4:09 AM Christoph Muellner
>> wrote:
>> >
>> > From: C
On Sun, Jan 29, 2023 at 11:40 PM Alistair Francis wrote:
>
> On Wed, Jan 25, 2023 at 5:51 AM Christoph Müllner
> wrote:
> >
> >
> >
> > On Tue, Jan 24, 2023 at 6:31 PM Christoph Müllner
> > wrote:
> >>
> >>
> >>
&
On Tue, Jan 24, 2023 at 9:21 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 1/24/23 09:59, Christoph Muellner wrote:
> > +static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas
> *a)
> > +{
> > +(void) a;
> > +REQUIRE_XTHEADSYNC(ctx);
> > +
> > +#ifndef
On Tue, Jan 24, 2023 at 10:26 PM Richard Henderson
wrote:
>
> On 1/24/23 09:59, Christoph Muellner wrote:
> > +++ b/target/riscv/cpu.h
> > @@ -27,6 +27,7 @@
> > #include "qom/object.h"
> > #include "qemu/int128.h"
> > #include "cpu_bits.h"
> > +#include "cpu_vendorid.h"
>
> I don't see that
On Tue, Jan 24, 2023 at 10:21 PM Richard Henderson
wrote:
>
> On 1/24/23 09:59, Christoph Muellner wrote:
> > +/* XTheadMemIdx */
> > +
> > +/*
> > + * Load with memop from indexed address and add (imm5 << imm2) to rs1.
> > + * If !preinc, then the load address is rs1.
> > + * If preinc, then
On Tue, Jan 24, 2023 at 9:44 PM Richard Henderson
wrote:
>
> On 1/24/23 09:59, Christoph Muellner wrote:
> > +static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop,
> > +int shamt)
> > +{
> > +TCGv rd1 = dest_gpr(ctx, a->rd1);
> > +TCGv rd2
On Thu, Mar 23, 2023 at 12:34 PM Lawrence Hunter
wrote:
>
> On 21/03/2023 12:02, Christoph Müllner wrote:
> > On Fri, Mar 10, 2023 at 10:16 AM Lawrence Hunter
> > wrote:
> >>
> >> This patchset provides an implementation for Zvkb, Zvkned, Zvknh,
> >>
On Fri, Mar 10, 2023 at 10:16 AM Lawrence Hunter
wrote:
>
> This patchset provides an implementation for Zvkb, Zvkned, Zvknh, Zvksh,
> Zvkg, and Zvksed of the draft RISC-V vector cryptography extensions as per
> the 20230303 version of the specification(1) (1fcbb30). Please note that the
>
On Fri, Mar 10, 2023 at 5:06 PM Lawrence Hunter
wrote:
>
> From: Kiran Ostrolenk
>
> Summary of refactoring:
>
> * take some functions/macros out of `vector_helper` and put them in a
> new module called `vector_internals`
>
> * factor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into
>
On Mon, Mar 27, 2023 at 7:18 PM Richard Henderson
wrote:
>
> On 3/27/23 01:00, Christoph Muellner wrote:
> > +uint64_t helper_fminm_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
> > +{
> > +float32 frs1 = check_nanbox_s(env, rs1);
> > +float32 frs2 = check_nanbox_s(env, rs2);
> > +
>
On Mon, Mar 27, 2023 at 10:42 AM liweiwei wrote:
>
>
> On 2023/3/27 16:00, Christoph Muellner wrote:
> > From: Christoph Müllner
> >
> > This patch introduces the RISC-V Zfa extension, which introduces
> > additional floating-point extensions:
> >
On Fri, Mar 31, 2023 at 11:39 PM Richard Henderson
wrote:
>
> On 3/31/23 11:22, Christoph Müllner wrote:
> > On Mon, Mar 27, 2023 at 7:18 PM Richard Henderson
> > wrote:
> >>
> >> On 3/27/23 01:00, Christoph Muellner wrote:
> >>> +uint64_t
".
On Mon, Apr 10, 2023 at 3:23 PM LIU Zhiwei wrote:
>
>
> On 2023/4/1 2:28, Christoph Muellner wrote:
> > From: Christoph Müllner
> >
> > This patch introduces the RISC-V Zfa extension, which introduces
> > additional floating-point extensions:
>
On Tue, Jan 31, 2023 at 7:23 PM Richard Henderson
wrote:
>
> On 1/31/23 08:01, Christoph Muellner wrote:
> > +if ((memop & MO_SIZE) == MO_64) {
> > +addr2 = get_address(ctx, a->rs, 8 + (a->sh2 << shamt));
> > +} else {
> > +addr2 = get_address(ctx, a->rs, 4 + (a->sh2 <<
On Mon, Jun 12, 2023 at 12:01 PM LIU Zhiwei wrote:
>
>
> On 2023/6/12 17:47, Christoph Müllner wrote:
> > On Mon, Jun 12, 2023 at 8:25 AM LIU Zhiwei wrote:
> >>
> >> On 2023/5/30 21:18, Christoph Muellner wrote:
> >>> From: Christoph Müllner
>
On Thu, Jun 8, 2023 at 3:05 PM LIU Zhiwei wrote:
>
>
> On 2023/5/30 21:18, Christoph Muellner wrote:
> > From: Christoph Müllner
> >
> > A previous patch provides a pointer to the RISCVCPUConfig data.
> > Let's use this to add the necessary code for vendo
>
>
> Put me in the CC when you re-send and I'll review it asap. Thanks,
>
>
> Daniel
>
> On 5/30/23 10:18, Christoph Muellner wrote:
> > From: Christoph Müllner
> >
> > This series adds vendor extension support to the QEMU disassembler
> > for RISC-V
On Mon, Jun 12, 2023 at 8:25 AM LIU Zhiwei wrote:
>
>
> On 2023/5/30 21:18, Christoph Muellner wrote:
> > From: Christoph Müllner
> >
> > The disassembler needs the available extensions in order
> > to properly decode instructions in case of overlapping
> >
On Mon, Jul 3, 2023 at 5:58 AM Alistair Francis wrote:
>
> On Sat, Jul 1, 2023 at 3:04 AM Christoph Muellner
> wrote:
> >
> > From: Christoph Müllner
> >
> > This patch introduces the RISC-V Zfa extension, which introduces
> > additional floating-point
On Mon, Jul 3, 2023 at 12:07 PM Richard Henderson
wrote:
>
> Use a shared driver and backends for i386, aarch64, ppc64, riscv64.
>
> Acked-by: Alex Bennée
> Signed-off-by: Richard Henderson
> ---
> tests/tcg/aarch64/test-aes.c| 58
> tests/tcg/i386/test-aes.c
On Mon, Jul 10, 2023 at 2:58 AM Alistair Francis wrote:
>
> On Mon, Jul 3, 2023 at 4:27 PM Christoph Muellner
> wrote:
> >
> > From: Christoph Müllner
> >
> > This patch introduces the RISC-V Zfa extension, which introduces
> > additional floating-point
On Thu, Jun 15, 2023 at 8:53 AM Weiwei Li wrote:
>
>
> On 2023/6/12 19:10, Christoph Muellner wrote:
> > From: Christoph Müllner
> >
> > Support for emulating XThead* instruction has been added recently.
> > This patch adds support for these instructions to th
On Fri, Jun 30, 2023 at 11:46 AM Richard Henderson
wrote:
>
> On 6/30/23 11:13, Christoph Muellner wrote:
> > From: Christoph Müllner
> >
> > This patch introduces a test for Zfa's fcvtmod.w.d instruction.
> > The test cases test for correct results and flag beh
On Fri, Jun 30, 2023 at 11:22 AM Richard Henderson
wrote:
>
> On 6/30/23 11:13, Christoph Muellner wrote:
> > From: Christoph Müllner
> >
> > For the most part we can use the new generic routine,
> > though exceptions need some post-processing.
> >
On Fri, Jun 30, 2023 at 11:53 AM Richard Henderson
wrote:
>
> On 6/30/23 11:13, Christoph Muellner wrote:
> > +static bool trans_fli_h(DisasContext *ctx, arg_fli_h *a)
> > +{
> > +REQUIRE_FPU;
> > +REQUIRE_ZFA(ctx);
> > +REQUIRE_ZFH(ctx);
> > +
> > +/* Values below are NaN-boxed
On Sat, May 27, 2023 at 4:19 PM Richard Henderson
wrote:
>
> Extract some common code from Alpha and Arm, and which will
> shortly also be required by the RISC-V Zfa extension.
> Added a new test for Alpha; I already had a RISU test for Arm.
Thank you for providing a generic implementation of
On Fri, Jun 30, 2023 at 4:03 PM Richard Henderson
wrote:
>
> On 6/30/23 13:52, Christoph Muellner wrote:
> > +bool trans_fmvh_x_d(DisasContext *ctx, arg_fmvh_x_d *a)
> > +{
> > +REQUIRE_FPU;
> > +REQUIRE_ZFA(ctx);
> > +REQUIRE_EXT(ctx, RVD);
> > +REQUIRE_32BIT(ctx);
> > +
> > +
On Mon, Feb 5, 2024 at 3:42 AM Alistair Francis wrote:
>
> On Sun, Feb 4, 2024 at 3:44 PM LIU Zhiwei
> wrote:
> >
> > This patch set fix the regression on kernel pointed by Björn Töpel in
> > https://www.mail-archive.com/qemu-devel@nongnu.org/msg1018232.html.
> >
> > thead-c906 uses some flags
.
These fences are placed in the RISC-V backend rather than TCG as is
planned for x86-on-arm64 because RISC-V allows heterogeneous (and
likely soon dynamic) hart memory models.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Palmer Dabbelt
Signed-off-by: Christoph Müllner
---
target/riscv/cpu.c
).
This series can also be found here:
https://github.com/cmuellner/qemu/tree/ztso
Christoph Müllner (1):
linux-user/riscv: Add Ztso extension to hwprobe
Palmer Dabbelt (1):
RISC-V: Add support for Ztso
linux-user/syscall.c| 3 +++
target/riscv/cpu.c
This patch implements the prctl calls to set and get the current memory
consistency model. This patch does not implement any real functionality
but just defines the relevant hooks, where target code take over.
Signed-off-by: Christoph Müllner
---
linux-user/syscall.c | 17 +
1
also be found in this GitHub branch:
https://github.com/cmuellner/qemu/tree/ssdtso-v2
A Linux implementation of DTSO can be found in this GitHub branch:
https://github.com/cmuellner/linux/tree/ssdtso-v2
Christoph Müllner (4):
RISC-V: Add support for Ssdtso
linux-user/riscv: Add Ssdtso
).
Signed-off-by: Christoph Müllner
---
target/riscv/cpu.c | 8 ++--
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_cfg.h | 1 +
target/riscv/csr.c | 14 +++---
target/riscv/translate.c | 2 +-
5 files changed, 22 insertions(+), 6 deletions(-)
diff --git
This patch implements the dynamic memory consistency model prctl calls
for RISC-V. The implementation introduces a single boolean variable to
keep the DTSO state.
Signed-off-by: Christoph Müllner
---
linux-user/riscv/target_prctl.h | 76 -
target/riscv/cpu.c
This patch exposes Ssdtso via hwprobe in QEMU's user space emulator.
Signed-off-by: Christoph Müllner
---
linux-user/syscall.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 24fa11d946..bf0d66b8a8 100644
--- a/linux-user/syscall.c
+++ b
On Wed, Feb 14, 2024 at 2:35 PM Daniel Henrique Barboza
wrote:
>
>
>
> On 2/7/24 09:22, Christoph Müllner wrote:
> > The first patch of this series picks up an earlier v2 Ztso patch from
> > Palmer,
> > which can be found here:
> >
> > https://pat
On Wed, Feb 14, 2024 at 5:25 PM Andrew Jones wrote:
>
> On Wed, Feb 14, 2024 at 02:38:34PM +0100, Christoph Müllner wrote:
> > On Wed, Feb 14, 2024 at 2:35 PM Daniel Henrique Barboza
> > wrote:
> > >
> > >
> > >
> > > On 2/7/24 0
On Wed, Dec 6, 2023 at 1:57 AM Alistair Francis wrote:
>
> On Mon, Nov 27, 2023 at 12:37 AM Christoph Muellner
> wrote:
> >
> > From: Christoph Müllner
> >
> > Upstream Linux recently added RISC-V Zicboz support to the hwprobe API.
> > This patch introdu
This series syncs the hwprobe keys with those available in the upstream
kernel repository with the exception of Ztso, which is not supported in
QEMU as of now.
The first patch is a resend (sent on Nov 27), as it should have been
picked up on Dec 6, but seems to got lost.
Christoph Müllner (2
Upstream Linux recently added many additional keys to the hwprobe API.
This patch adds support for all of them with the exception of Ztso,
which is currently not supported in QEMU.
Signed-off-by: Christoph Müllner
---
linux-user/syscall.c | 98
1
Upstream Linux recently added RISC-V Zicboz support to the hwprobe API.
This patch introduces this for QEMU's user space emulator.
Signed-off-by: Christoph Müllner
---
linux-user/syscall.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index
This patch exposes Ztso via hwprobe in QEMU's user space emulator.
Signed-off-by: Christoph Müllner
---
linux-user/syscall.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 3ba20f99ad..24fa11d946 100644
--- a/linux-user/syscall.c
+++ b
On Fri, Dec 8, 2023 at 10:44 AM LIU Zhiwei wrote:
>
> According to the specification, the th.dcache.cvall1 can be executed
> under all priviledges.
> The specification about xtheadcmo located in,
> https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadcmo/dcache_cval1.adoc
>
>
On Thu, Nov 23, 2023 at 7:01 PM Christoph Muellner
wrote:
>
> From: Christoph Müllner
>
> Upstream Linux recently added RISC-V Zicboz support to the hwprobe API.
> This patch introduces this for QEMU's user space emulator.
>
> Signed-off-by: Christoph Müllner
> ---
>
On Fri, Nov 24, 2023 at 5:59 PM Andrew Jones wrote:
>
> On Thu, Nov 23, 2023 at 07:12:59PM +0100, Christoph Muellner wrote:
> > From: Christoph Müllner
> >
> > Upstream Linux recently added RISC-V Zicboz support to the hwprobe API.
> > This patch introduces this
On Tue, Jan 30, 2024 at 12:12 PM LIU Zhiwei
wrote:
>
> thead-c906 uses some flags in pte [60-63] bits. It has history reasons that
> SVPBMT didn't exist when thead-c906 came to world.
>
> We named this feature as xtheadmaee. this feature is controlled by an custom
> CSR named mxstatus, whose maee
Running test-fcvtmod triggers the following deprecation warning:
warning: CPU property 'Zfa' is deprecated. Please use 'zfa' instead
Let's fix that.
Signed-off-by: Christoph Müllner
---
tests/tcg/riscv64/Makefile.target | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests
On Thu, Mar 7, 2024 at 9:35 PM Richard Henderson
wrote:
>
> >>> -for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
> >>> -if (decoders[i].guard_func(ctx->cfg_ptr) &&
> >>> -decoders[i].decode_func(ctx, opcode32)) {
> >>> +for (size_t i = 0; i <
On Fri, Mar 8, 2024 at 5:23 AM Alistair Francis wrote:
>
> On Wed, Feb 7, 2024 at 10:00 PM Christoph Müllner
> wrote:
> >
> > Upstream Linux recently added many additional keys to the hwprobe API.
> > This patch adds support for all of them with the exception of Z
-by: Christoph Müllner
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 3 ++
target/riscv/meson.build | 1 +
target/riscv/th_csr.c| 76
4 files changed, 81 insertions(+)
create mode 100644 target/riscv/th_csr.c
diff --git a/target/riscv/cpu.c b
hu, Feb 15, 2024 at 02:24:02PM +1000, Alistair Francis wrote:
> > > On Mon, Feb 5, 2024 at 6:37 PM Christoph Müllner
> > > wrote:
> > > > On Mon, Feb 5, 2024 at 3:42 AM Alistair Francis
> > > > wrote:
> > > > > On Sun, Feb 4, 2024 at
-by: Christoph Müllner
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 3 ++
target/riscv/meson.build | 1 +
target/riscv/th_csr.c| 78
4 files changed, 83 insertions(+)
create mode 100644 target/riscv/th_csr.c
diff --git a/target/riscv/cpu.c b
On Fri, Apr 5, 2024 at 3:36 AM LIU Zhiwei wrote:
>
>
> On 2024/3/29 20:04, Christoph Müllner wrote:
> > The th.sxstatus CSR can be used to identify available custom extension
> > on T-Head CPUs. The CSR is documented here:
> >https://github.com/T-head-Semi/t
Reviewed-by: LIU Zhiwei
Signed-off-by: Christoph Müllner
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 4 +++
target/riscv/csr.c | 2 +-
target/riscv/meson.build | 1 +
target/riscv/th_csr.c| 68
5 files changed, 75
On Mon, Apr 22, 2024 at 5:29 AM Alistair Francis wrote:
>
> On Thu, Apr 18, 2024 at 8:55 AM Christoph Müllner
> wrote:
> >
> > The th.sxstatus CSR can be used to identify available custom extension
> > on T-Head CPUs. The CSR is documented here:
> >
> &g
Reviewed-by: LIU Zhiwei
Signed-off-by: Christoph Müllner
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 3 ++
target/riscv/meson.build | 1 +
target/riscv/th_csr.c| 77
4 files changed, 82 insertions(+)
create mode 100644 target
On Mon, Apr 29, 2024 at 5:29 AM Alistair Francis wrote:
>
> On Mon, Apr 22, 2024 at 4:53 PM Christoph Müllner
> wrote:
> >
> > The th.sxstatus CSR can be used to identify available custom extension
> > on T-Head CPUs. The CSR is documented here:
> >
> &g
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Christoph Müllner
---
MAINTAINERS | 1 +
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 3 ++
target/riscv/meson.build | 1 +
target/riscv/th_csr.c| 79
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