add aer support.
Signed-off-by: Isaku Yamahata
---
Changes v8 -> v9
- error path in initialization.
---
hw/xio3130_upstream.c | 33 -
1 files changed, 24 insertions(+), 9 deletions(-)
diff --git a/hw/xio3130_upstream.c b/hw/xio3130_upstream.c
index d9d6
e.[ch] into pcie_regs.h, pcie.[ch] and pcie_aer.[ch]
- pcie, aer: many changes by following reviews.
changes v1 -> v2:
- update msi
- dropped already pushed out patches.
- added msix patches.
Isaku Yamahata (8):
pci: revise pci command register initialization
pci: fix accesses to pci status
This patch cleans up command register initialization with
comments. It also fixes the initialization of io/memory bit of command register.
Those bits for type 1 device is RW.
Those bits for type 0 device is
RO = 0 if it has no io/memory BAR
RW if it has io/memory BAR
Signed-off-by: Isaku
pci status register is 16 bit, not 8 bit.
So use helper function to manipulate status register.
Signed-off-by: Isaku Yamahata
---
hw/pci.c | 21 +
1 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 2fc8ab1..52fe655 100644
--- a/hw
This patch implements helper functions for pcie aer capability
which will be used later.
Signed-off-by: Isaku Yamahata
---
Changes v8 -> v9:
- make pcie_aer_init() return error
Changes v7 -> v8:
- various changes to follow the review.
- s/TLP_PRESENT/TLP_PREFIX_PRESENT/g
Changes v6
add aer support.
Signed-off-by: Isaku Yamahata
---
Changes v8 -> v9:
- error path in initialization
---
hw/xio3130_downstream.c | 43 +--
1 files changed, 33 insertions(+), 10 deletions(-)
diff --git a/hw/xio3130_downstream.c b/hw/xio3130_downstrea
Add aer support.
Signed-off-by: Isaku Yamahata
---
Changes v8 -> v9:
- error path in initialization
---
hw/ioh3420.c | 80 ++---
1 files changed, 70 insertions(+), 10 deletions(-)
diff --git a/hw/ioh3420.c b/hw/ioh3420.c
index 3cc1
remove unnecessary sizeof.
Signed-off-by: Isaku Yamahata
---
hw/pcie_regs.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/hw/pcie_regs.h b/hw/pcie_regs.h
index 3461a1b..4d123d9 100644
--- a/hw/pcie_regs.h
+++ b/hw/pcie_regs.h
@@ -94,7 +94,9 @@
#define
On Tue, Nov 16, 2010 at 12:50:19PM +0200, Michael S. Tsirkin wrote:
> On Tue, Nov 16, 2010 at 05:26:05PM +0900, Isaku Yamahata wrote:
> > This patch cleans up command register initialization with
> > comments. It also fixes the initialization of io/memory bit of command
> >
On Tue, Nov 16, 2010 at 10:57:59AM -0800, Etienne Martineau wrote:
>
> On Tue, 2010-11-16 at 17:26 +0900, Isaku Yamahata wrote:
> > add aer support.
> >
> > Signed-off-by: Isaku Yamahata
>
> I'm actually working on a scheme to provide support to handle PCI
&
On Tue, Nov 16, 2010 at 12:52:31PM +0200, Michael S. Tsirkin wrote:
> On Tue, Nov 16, 2010 at 05:26:06PM +0900, Isaku Yamahata wrote:
> > pci status register is 16 bit, not 8 bit.
> > So use helper function to manipulate status register.
> >
> > Signed-off-by: Isaku
ported
from the following repo.
git://repo.or.cz/qemu/aliguori.git qdev-refactor
Anthony Liguori (2):
qbus: add functions to walk both devices and busses
qdev: reset qdev along with qdev tree
Isaku Yamahata (5):
qdev: introduce reset call back for qbus level
qdev: introduce a helper function
Each pci devices should know the behavior on reset.
So make each reset functions call pci default reset function.
Signed-off-by: Isaku Yamahata
Signed-off-by: Anthony Liguori
---
hw/e1000.c |1 +
hw/lsi53c895a.c |2 ++
hw/pci.c|8 +---
hw/pcnet.c |1 +
hw
with a positive
value that's returned as the qbus_walk_children's result.
Signed-off-by: Isaku Yamahata
Signed-off-by: Anthony Liguori
---
hw/qdev.c | 46 ++
hw/qdev.h |9 +
2 files changed, 55 insertions(+), 0 deletions(-)
Emulates secondary bus reset when secondary bus reset bit
is written from 0 to 1.
Signed-off-by: Isaku Yamahata
Signed-off-by: Anthony Liguori
---
hw/pci_bridge.c | 12 +++-
1 files changed, 11 insertions(+), 1 deletions(-)
diff --git a/hw/pci_bridge.c b/hw/pci_bridge.c
index
implicit system bus because we have various hacks
that result in an implicit system bus existing. Instead, we ought to have an
explicitly created system bus that we can trigger reset from. That's a topic
for a future patch though.
Signed-off-by: Anthony Liguori
Signed-off-by: Isaku Yam
Signed-off-by: Isaku Yamahata
Signed-off-by: Anthony Liguori
---
hw/qdev.c |5 +
hw/qdev.h |1 +
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/hw/qdev.c b/hw/qdev.c
index b76da07..b65b63e 100644
--- a/hw/qdev.c
+++ b/hw/qdev.c
@@ -322,6 +322,11 @@ static int
and make it called via qbus_reset_all().
The qbus reset callback will be used by pci bus reset.
Signed-off-by: Isaku Yamahata
Signed-off-by: Anthony Liguori
---
hw/qdev.c | 10 +-
hw/qdev.h |2 ++
2 files changed, 11 insertions(+), 1 deletions(-)
diff --git a/hw/qdev.c b/hw
Signed-off-by: Isaku Yamahata
Signed-off-by: Anthony Liguori
---
hw/pci.c | 38 ++
hw/pci.h |3 +++
2 files changed, 37 insertions(+), 4 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 962886e..b6f58de 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -43,12
On Wed, Nov 17, 2010 at 02:02:00PM +0200, Michael S. Tsirkin wrote:
> > > Another bug is that migrating from qemu where a bit is writeable to one
> > > where it's RO creates a situation where a RW bit becomes RO, or the
> > > reverse, which might confuse guests. So we will need a compatibility
> >
On Tue, Nov 16, 2010 at 09:31:28PM -0800, Etienne Martineau wrote:
>
> On Wed, 17 Nov 2010, Isaku Yamahata wrote:
>
> > > Because of such it seems like the only way to maintain consistency
> > > between
> > > the assigned device and it's cor
te:
> > Hi,
> >
> > Can you elaborate what you mean by bridge support? I would really like to go
> > to 256 interfaces.
> >
> > Anjali
>
> Isaku Yamahata wrote most of it, I'll let him comment.
>
> --
> MST
>
--
yamahata
On Wed, Nov 17, 2010 at 09:41:03PM -0800, Wei Xu wrote:
> Could you explain more on irq routing in dsdt and related code in qemu? I
> encountered a problem: emulated user networking (-net nic -net user) cannot
> work in my qemu-kvm+q35+pcie code. Your original q35 (pure qemu) works fine.
The relat
On Thu, Nov 18, 2010 at 08:46:43AM +0200, Michael S. Tsirkin wrote:
> > What is missing for multiple pci buses is
> > - a new PC machine description which has multiple pci buses
> > My Q35 chipset patch will provide this.
>
> IMHO, what we really need is a way to specify bridges
> through qdev.
On Thu, Nov 18, 2010 at 09:15:19AM +0200, Michael S. Tsirkin wrote:
> On Thu, Nov 18, 2010 at 04:09:34PM +0900, Isaku Yamahata wrote:
> > On Thu, Nov 18, 2010 at 08:46:43AM +0200, Michael S. Tsirkin wrote:
> > > > What is missing for multiple pci buses is
> > > &g
On Thu, Nov 18, 2010 at 09:05:30AM +0200, Michael S. Tsirkin wrote:
> On Wed, Nov 17, 2010 at 01:50:27PM +0900, Isaku Yamahata wrote:
> > Emulates secondary bus reset when secondary bus reset bit
> > is written from 0 to 1.
> >
> > Signed-off-by: Isaku Yamahata
> &g
On Wed, Nov 17, 2010 at 04:06:38PM +0200, Michael S. Tsirkin wrote:
> On Tue, Nov 16, 2010 at 05:26:09PM +0900, Isaku Yamahata wrote:
> > This patch implements helper functions for pcie aer capability
> > which will be used later.
> >
> > Signed-off-by: Isaku Yamahata
On Thu, Nov 18, 2010 at 09:02:35AM +0200, Michael S. Tsirkin wrote:
> > +/*
> > + * TODO:
> > + * each device should know what to do on RST#.
> > + * move pci_device_reset_default() into each callback.
> > + */
>
> Is this doing anything besides give devices
On Thu, Nov 18, 2010 at 12:54:29PM +0100, Gerd Hoffmann wrote:
> Hi,
>
>> What is missing for multiple pci buses is
>
>> - a simple P2P bridge emulator for pc architecture
>> - seabios support
>>- DSDT for a new machine which has multi pci buses(IRQ routing)
>
> Is this really needed?
Q35 IR
On Thu, Nov 18, 2010 at 10:46:25AM +0200, Michael S. Tsirkin wrote:
> On Thu, Nov 18, 2010 at 04:29:10PM +0900, Isaku Yamahata wrote:
> > On Thu, Nov 18, 2010 at 09:05:30AM +0200, Michael S. Tsirkin wrote:
> > > On Wed, Nov 17, 2010 at 01:50:27PM +0900, Isaku Yamahata wrote
On Wed, Nov 17, 2010 at 04:06:38PM +0200, Michael S. Tsirkin wrote:
> Please, try to address the TODO: I think the case of
> PCIE device behind a pci bridge is not covered properly.
Right, pci-to-pcie bridge case isn't covered.
Although SERR bit can be set, the error can't be propagated up further
Signed-off-by: Isaku Yamahata
Signed-off-by: Anthony Liguori
---
hw/qdev.c |5 +
hw/qdev.h |1 +
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/hw/qdev.c b/hw/qdev.c
index b76da07..b65b63e 100644
--- a/hw/qdev.c
+++ b/hw/qdev.c
@@ -322,6 +322,11 @@ static int
implicit system bus because we have various hacks
that result in an implicit system bus existing. Instead, we ought to have an
explicitly created system bus that we can trigger reset from. That's a topic
for a future patch though.
Signed-off-by: Anthony Liguori
Signed-off-by: Isaku Yam
Emulates secondary bus reset when secondary bus reset bit
is written from 0 to 1.
Signed-off-by: Isaku Yamahata
Signed-off-by: Anthony Liguori
---
hw/pci_bridge.c | 12 +++-
1 files changed, 11 insertions(+), 1 deletions(-)
diff --git a/hw/pci_bridge.c b/hw/pci_bridge.c
index
with a positive
value that's returned as the qbus_walk_children's result.
Signed-off-by: Isaku Yamahata
Signed-off-by: Anthony Liguori
---
Changes v1 -> v2:
- update comments to match the implementation
---
hw/qdev.c | 46 ++
set qdev along with qdev tree
Isaku Yamahata (4):
qdev: introduce reset call back for qbus level
qdev: introduce a helper function which triggers reset from a given
device
pci: make use of qdev reset frame work to pci bus reset.
pci bridge: implement secondary bus reset
hw/pc
Signed-off-by: Isaku Yamahata
Signed-off-by: Anthony Liguori
---
hw/pci.c | 33 +
hw/pci.h |3 +++
2 files changed, 32 insertions(+), 4 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 962886e..51b7857 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -43,12
and make it called via qbus_reset_all().
The qbus reset callback will be used by pci bus reset.
Signed-off-by: Isaku Yamahata
Signed-off-by: Anthony Liguori
---
hw/qdev.c | 10 +-
hw/qdev.h |2 ++
2 files changed, 11 insertions(+), 1 deletions(-)
diff --git a/hw/qdev.c b/hw
On Mon, Nov 22, 2010 at 09:54:02AM +0200, Michael S. Tsirkin wrote:
> On Fri, Nov 19, 2010 at 06:55:57PM +0900, Isaku Yamahata wrote:
> > Here is v2. I updated the comments, and dropped the pci qdev reset patch.
> >
> > Patch description:
> > The goal of this p
On Tue, Nov 23, 2010 at 08:10:26PM +0200, Michael S. Tsirkin wrote:
> On Tue, Nov 23, 2010 at 12:53:12AM +0200, Michael S. Tsirkin wrote:
> > On Mon, Nov 22, 2010 at 07:43:37PM +0900, Isaku Yamahata wrote:
> > > On Mon, Nov 22, 2010 at 09:54:02AM +0200, Michael S. Tsirkin wro
On Wed, Nov 24, 2010 at 07:27:58AM +0200, Michael S. Tsirkin wrote:
> Right. So let's add an inline helper to avoid code duplication here?
>
> pci: fix bus walk under secondary bus reset
>
> Take into account secondary bus reset bit for
> bus walk: devices behind a reset bus should not
> respond
On Wed, Nov 24, 2010 at 12:59:43PM +0200, Michael S. Tsirkin wrote:
> > > @@ -1552,20 +1562,21 @@ PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
> > > return bus;
> > > }
> > >
> > > +/* Consider all bus numbers in range for the host pci bridge. */
> > > +if (bus->parent_dev
On Thu, Nov 25, 2010 at 08:07:39AM +0100, Alexander Graf wrote:
> +static int pci_ahci_init(PCIDevice *dev)
> +{
> +struct AHCIPCIState *d;
> +d = DO_UPCAST(struct AHCIPCIState, card, dev);
> +
> +pci_config_set_vendor_id(d->card.config, PCI_VENDOR_ID_INTEL);
> +pci_config_set_devic
On Wed, Nov 24, 2010 at 02:08:16PM +, adq wrote:
> > Interesting. I was also thinking that maybe we can leverage overriding
> > mechanisms that are already available. Maybe it's possible to squeeze the
> > HPET node into an SSDT. Maybe we need to override the whole DSDT from the
> > command
pcie aer wants SERR bit to be writable.
So make it writable. For compatibility, introduce compat global property
command_serr_enable and don't make it writable when pre 0.14 pc machine.
Signed-off-by: Isaku Yamahata
---
This patch depends on b1d6dd8ce83e1430b7b0e98c898499a966464227
which
On Thu, Nov 25, 2010 at 08:18:45PM +, adq wrote:
> On 25 November 2010 11:28, Isaku Yamahata wrote:
> > On Wed, Nov 24, 2010 at 02:08:16PM +, adq wrote:
> >> > Interesting. I was also thinking that maybe we can leverage overriding
> >> > mechanisms that
On Thu, Nov 25, 2010 at 08:18:45PM +, adq wrote:
> On 25 November 2010 11:28, Isaku Yamahata wrote:
> > On Wed, Nov 24, 2010 at 02:08:16PM +, adq wrote:
> >> > Interesting. I was also thinking that maybe we can leverage overriding
> >> > mechanisms that
On Sat, Nov 27, 2010 at 11:30:52AM +, Paul Brook wrote:
> ---
> Makefile.objs |3 +-
> default-configs/pci.mak |1 +
> default-configs/sparc-softmmu.mak |1 +
> hw/pcnet.c| 311
> +
> hw/p
On Thu, Dec 02, 2010 at 09:32:12PM +0200, Michael S. Tsirkin wrote:
> On Fri, Nov 26, 2010 at 09:01:41PM +0900, Isaku Yamahata wrote:
> > pcie aer wants SERR bit to be writable.
> > So make it writable. For compatibility, introduce compat global property
> > command_serr_ena
On Fri, Dec 03, 2010 at 12:54:33AM +0200, Michael S. Tsirkin wrote:
> diff --git a/hw/pcie_aer.c b/hw/pcie_aer.c
> index 235ac53..18bbd5a 100644
> --- a/hw/pcie_aer.c
> +++ b/hw/pcie_aer.c
> @@ -339,10 +339,10 @@ static bool pcie_aer_msg_root_port(PCIDevice *dev,
> const PCIEAERMsg *msg)
>
>
Looks good.
On Fri, Dec 03, 2010 at 12:54:43AM +0200, Michael S. Tsirkin wrote:
> config write handling for aer seems broken:
> For example, it won't clear a level interrupt
> when command register is set to 0.
>
> Make it match the spec: level should equal
> the logical or of enabled bits, msi o
On Fri, Dec 03, 2010 at 01:02:35AM +0200, Michael S. Tsirkin wrote:
> Also, the code has many cases that look like:
>
> if (root_cmd & PCI_ERR_ROOT_CMD_COR_EN) {
> }
> If the intent is to add some code later, pls put a TODO here.
> Otherwise please remove these or replace w
Looks good.
Maybe assert(0) should be replaced by abort().
Anyway this patch removes it, though.
On Fri, Dec 03, 2010 at 12:54:47AM +0200, Michael S. Tsirkin wrote:
> Same logic is used to assert interrupts
> and send msix messages, so add a static functin for this.
>
> Signed-off-by: Michael S.
The eventual result looks okay.
But if-clauses that surrounds msi_trigger = true should be eliminated
at the same time.
1/6, 3/6 and, 4/6 could be reordered for bisectability.
thanks,
On Fri, Dec 03, 2010 at 12:54:37AM +0200, Michael S. Tsirkin wrote:
> Remove some unused variables and return val
QLIST_FOREACH_SAFE?
On Thu, Nov 25, 2010 at 03:06:45PM +0900, Yoshiaki Tamura wrote:
> By copying the next entry to a tmp pointer,
> qemu_del_vm_change_state_handler() can be called in the handler.
>
> Signed-off-by: Yoshiaki Tamura
> ---
> vl.c |5 +++--
> 1 files changed, 3 insertions(+),
chael S. Tsirkin
Signed-off-by: Isaku Yamahata
---
- reorder
- abort() instead of assert(0)
---
hw/pcie_aer.c | 46 +-
1 files changed, 17 insertions(+), 29 deletions(-)
diff --git a/hw/pcie_aer.c b/hw/pcie_aer.c
index bc98da0..389e9d5 100644
---
From: Michael S. Tsirkin
Possible now that pci is not depending on these.
Signed-off-by: Michael S. Tsirkin
---
Makefile.objs |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/Makefile.objs b/Makefile.objs
index 04625eb..d1e63ce 100644
--- a/Makefile.objs
+++ b/Makefil
From: Michael S. Tsirkin
Same logic is used to assert interrupts
and send msix messages, so add a static functin for this.
Signed-off-by: Michael S. Tsirkin
---
hw/pcie_aer.c | 27 +--
1 files changed, 13 insertions(+), 14 deletions(-)
diff --git a/hw/pcie_aer.c b/hw
: Isaku Yamahata
---
Changes v1 -> v2:
- reorder
---
hw/pcie_aer.c | 51 +++
1 files changed, 35 insertions(+), 16 deletions(-)
diff --git a/hw/pcie_aer.c b/hw/pcie_aer.c
index 80cc438..bc98da0 100644
--- a/hw/pcie_aer.c
+++ b/hw/pcie_aer.c
@@ -25
I respined the patch series by mst for bisectability.
Changes v1 -> v2:
- reorder patches for bisectability
- s/assert/trigger/ to avoid name conflict
- abort() instead of assert(0)
Original patch description:
Here are a bunch of fixes and cleanups to aer interrupt injection.
Compile tested only,
From: Michael S. Tsirkin
Remove some unused variables and return values.
Signed-off-by: Michael S. Tsirkin
Signed-off-by: Isaku Yamahata
---
changes v1 -> v2:
- reorder
---
hw/pcie_aer.c | 25 ++---
1 files changed, 2 insertions(+), 23 deletions(-)
diff --git a
Signed-off-by: Isaku Yamahata
---
Changes v1 -> v2:
- s/assert/trigger/g
variable name, assert, would conflict with assert.h
- msi_trigger
---
hw/pci.c | 19 ---
hw/pci.h |3 ---
hw/pcie.c |8 +---
hw/pcie_aer.c | 24
4 fi
What is the reason to duplicate cpu_{in,out}[bwl]() instead of
ioport-user.c?
On Wed, Dec 08, 2010 at 01:49:11PM +0100, Paolo Bonzini wrote:
> Signed-off-by: Paolo Bonzini
> ---
> I had this patch lying around but I don't think I ever got
> qruncom to work completely.
>
> Makefi
On Mon, Dec 13, 2010 at 03:43:44PM -0700, Cam Macdonell wrote:
> Do not call pci_update_mappings on the lower 32-bits of a 64-bit bar. Wait
> for the upper 32 or else Qemu will try to map on just the lower 32 which is
> probably going to corrupt memory.
>
> I was encountering crashes when mappi
On Wed, Dec 15, 2010 at 08:27:49AM -0700, Alex Williamson wrote:
> On Wed, 2010-12-15 at 11:56 +0200, Michael S. Tsirkin wrote:
> > On Tue, Dec 14, 2010 at 11:34:53AM -0700, Alex Williamson wrote:
> > > On Tue, 2010-12-14 at 14:26 +0200, Michael S. Tsirkin wrote:
> > > > On Mon, Dec 13, 2010 at 10:
On Tue, Dec 14, 2010 at 10:42:43AM -0700, Cam Macdonell wrote:
> On Mon, Dec 13, 2010 at 8:00 PM, Isaku Yamahata
> wrote:
> > On Mon, Dec 13, 2010 at 03:43:44PM -0700, Cam Macdonell wrote:
> >> Do not call pci_update_mappings on the lower 32-bits of a 64-bit bar.
> >
On Thu, Dec 16, 2010 at 08:31:21PM +0100, Stefan Weil wrote:
> The second regression also occurs with MIPS malta.
> Networking no longer works with the default pcnet nic.
>
> This is caused because the reset function for pcnet is no
> longer called during system boot. The result in an invalid
> mac
On Fri, Dec 17, 2010 at 01:29:42PM +0900, Isaku Yamahata wrote:
> On Thu, Dec 16, 2010 at 08:31:21PM +0100, Stefan Weil wrote:
> > The second regression also occurs with MIPS malta.
> > Networking no longer works with the default pcnet nic.
> >
> > This is caused bec
be moved under bus controller
device which is qdev. But it's not done yet.
So register qbus reset handler for qbus whose parent is NULL.
Reported-by: Stefan Weil
Signed-off-by: Isaku Yamahata
Tested-by: Stefan Weil
---
hw/qdev.c |5 -
vl.c |2 ++
2 files changed, 6 insertions(
On Sun, Dec 19, 2010 at 03:24:32PM +0200, Michael S. Tsirkin wrote:
> On Sun, Dec 19, 2010 at 03:19:22PM +0200, Michael S. Tsirkin wrote:
> > On Sun, Dec 19, 2010 at 10:22:50AM +0900, Isaku Yamahata wrote:
> > > Stefan Weil reported the re
be moved under bus controller
device which is qdev. But it's not done yet.
So register qbus reset handler for qbus whose parent is NULL.
Reported-by: Stefan Weil
Signed-off-by: "Michael S. Tsirkin"
Signed-off-by: Isaku Yamahata
---
Changes v1 -> v2:
- unregister reset handler i
On Mon, Dec 20, 2010 at 08:35:24AM +0200, Michael S. Tsirkin wrote:
> > diff --git a/hw/qdev.h b/hw/qdev.h
> > index aaaf55a..b239bb4 100644
> > --- a/hw/qdev.h
> > +++ b/hw/qdev.h
> > @@ -199,6 +199,8 @@ int qdev_walk_children(DeviceState *dev, qdev_walkerfn
> > *devfn,
> >
On Thu, Dec 16, 2010 at 10:36:08AM +0200, Michael S. Tsirkin wrote:
> On Thu, Dec 16, 2010 at 04:08:16PM +0900, Isaku Yamahata wrote:
> > On Wed, Dec 15, 2010 at 08:27:49AM -0700, Alex Williamson wrote:
> > > On Wed, 2010-12-15 at 11:56 +0200, Michael S. Tsirkin wrote:
> >
On Wed, Dec 22, 2010 at 12:20:23AM +0100, Andreas Färber wrote:
> From: Hervé Poussineau
>
> v1:
> * Rebased.
>
> Signed-off-by: Hervé Poussineau
> Cc: Michael S. Tsirkin
> Signed-off-by: Andreas Färber
> ---
>
> Hello Michael,
>
> Could you please take a look at this? I'm out of my fie
verted.
It will be addressed for 0.15 release.
Cc: "Michael S. Tsirkin"
Cc: Alex Williamson
Cc: Blue Swirl
Signed-off-by: Isaku Yamahata
---
hw/apb_pci.c|9 +
hw/dec_pci.c|6 ++
hw/ioh3420.c|4
hw/xio3130_downstre
The change set of b1aeb92666d2fde413c34578b3b42bbfe5f2a506 in pci branch
was mismerged. The compatibility should be kept for 0.13, not for 0.14.
Signed-off-by: Isaku Yamahata
---
hw/pc_piix.c | 12
1 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/hw/pc_piix.c b/hw
support flr.
Signed-off-by: Isaku Yamahata
---
hw/pci.c|6 +-
hw/pci.h|1 +
hw/pcie.c | 11 +--
hw/pcie.h |2 --
hw/xio3130_downstream.c |2 +-
hw/xio3130_upstream.c |3 ---
6 files changed, 12
On Wed, Dec 22, 2010 at 08:27:17AM +0200, Michael S. Tsirkin wrote:
> On Wed, Dec 22, 2010 at 12:13:43PM +0900, Isaku Yamahata wrote:
> > Right now pcibus_get_dev_path() isn't migration save because
> > bus number/secondary bus number are set by guest OS.
> > So it can&#
On Tue, Dec 21, 2010 at 02:24:29PM -0600, Adnan Khaleel wrote:
> Hello,
Hi.
> I have a question regarding how Qemu PCIe devices handle Config Transactions
> vs
> Memory Transactions (assuming the PCI device is setup to act
> as PCI_BASE_ADDRESS_SPACE_MEMORY).
>
> I'm using portions of hw/cirr
This patch series introduces hmp command to inject aer error.
Now fw device path is used to specify pci function.
Isaku Yamahata (3):
build, pci: remove QMP dependency on core PCI code
pci: introduce a parser for fw device path to pci device
pcie/aer: glue aer error injection into qemu
Introduce a function to parse fw device path to pci device.
the format is
/p...@{, }/[]@,/.../[]@,
= "i"
=
= slot number in hex
= func number in hex
Signed-off-by: Isaku Yamahata
---
hw/pci.c | 128 ++
hw/pci.h |2
introduce pcie_aer_inject_error command.
Signed-off-by: Isaku Yamahata
---
Changes v9 -> v10:
- use fw device path
- error path
- pci-stub.c for CONFIG_PCI=n
Changes v8 -> v9:
- revise error code
Changes v7 -> v8:
- use domain:slot.func:slot.func...:slot.func instead of domain:bus:
by introducing pci-stub.c, eliminate QMP dependency on core PCI code
rquired by query-pci command.
Signed-off-by: Isaku Yamahata
---
Makefile.objs |4 +---
Makefile.target |2 ++
hw/pci-stub.c | 37 +
3 files changed, 40 insertions(+), 3
On Wed, Dec 22, 2010 at 01:04:43PM +0200, Michael S. Tsirkin wrote:
> On Wed, Dec 22, 2010 at 07:54:49PM +0900, Isaku Yamahata wrote:
> > Introduce a function to parse fw device path to pci device.
> > the format is
> > /p...@{,
> > }/[]@,/.../[]@,
> >
> &g
On Wed, Dec 22, 2010 at 02:03:55PM +0200, Michael S. Tsirkin wrote:
> On Wed, Dec 22, 2010 at 08:36:40PM +0900, Isaku Yamahata wrote:
> > On Wed, Dec 22, 2010 at 01:04:43PM +0200, Michael S. Tsirkin wrote:
> > > On Wed, Dec 22, 2010 at 07:54:49PM +0900, Isaku Yamahata wrote:
&
Introduce a function to parse fw device path to pci device.
the format is
/p...@{, }/[]@,/.../[]@,
= "i"
=
= slot number in hex
= func number in hex
Signed-off-by: Isaku Yamahata
---
hw/pci.c | 129 ++
hw/pci.h |2
This patch series introduces hmp command to inject aer error.
Now fw device path is used to specify pci function.
Changes v10 -> v11:
- use qdev id and use fw dev path as fallback
Isaku Yamahata (5):
qdev: export qdev_find_recursive() for later use
pci: introduce a helper function to conv
This patch introduce a helper function to get PCIDevice from qdev id.
This function will be used later.
Signed-off-by: Isaku Yamahata
---
hw/pci.c | 35 +++
hw/pci.h |1 +
2 files changed, 36 insertions(+), 0 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
introduce pcie_aer_inject_error command.
Signed-off-by: Isaku Yamahata
---
Change v10 -> v11:
- use qdev id
Changes v9 -> v10:
- use fw device path
- error path
- pci-stub.c for CONFIG_PCI=n
Changes v8 -> v9:
- revise error code
Changes v7 -> v8:
- use domain:slot.func:slot.func.
This patch exports qdev_find_recursive() for later use.
Signed-off-by: Isaku Yamahata
---
hw/qdev.c |2 +-
hw/qdev.h |2 ++
2 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/hw/qdev.c b/hw/qdev.c
index 4747c67..31eb464 100644
--- a/hw/qdev.c
+++ b/hw/qdev.c
@@ -548,7 +548,7
pcie_aer_inject command: When qdev id failed, try fw device path as
fallback.
Signed-off-by: Isaku Yamahata
---
hmp-commands.hx |7 ++-
hw/pcie_aer.c | 12
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/hmp-commands.hx b/hmp-commands.hx
index 8d84ddc
The code looks good.
Regarding to the format itself, I don't have strong opinion about it.
What cames into my mind while I'm looking at the code is,
Does BusInfo have to have two path functions? get_dev_path and get_fw_dev_path.
Right now only pci supplies get_dev_path, on the other hand
get_fw_de
How about creating stub functions instead of #ifdefs?
something like
pc-stubs.c
#ifndef CONFIG_VMWARE_VGA
pci_vmsvga_init()
{
error ...
}
#endif
#ifndef CONFIG_...
...
On Wed, Jan 12, 2011 at 11:34:29PM -0700, David Ahern wrote:
> David Ahern (8):
> fix 'no such file' error from make_d
make pci_find_device() ARI aware.
Signed-off-by: Isaku Yamahata
---
hw/pci.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 8d0e3df..851f350 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -1596,11 +1596,18 @@ PCIBus *pci_find_bus(PCIBus *bus
use qemu_malloc() instead of direct use of malloc().
Signed-off-by: Isaku Yamahata
---
hw/pci.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 851f350..86af0ee 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -2053,7 +2053,7 @@ static char
This patch makes pci bus creation aware of pci domain.
Signed-off-by: Isaku Yamahata
---
hw/pci.c | 19 ++-
hw/pci.h |7 ---
hw/piix_pci.c |2 +-
3 files changed, 19 insertions(+), 9 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 86af0ee..e1e7b25
deassert intx on device reset.
So far pci_device_reset() is used for system reset.
In that case, interrupt controller is reset at the same time so that
all irq is are deasserted.
But now pci bus reset/flr is supported, and in that case irq needs to be
disabled explicitly.
Signed-off-by: Isaku
use pci_device_deassert_intx().
Signed-off-by: Isaku Yamahata
---
hw/msi.c |5 +
1 files changed, 1 insertions(+), 4 deletions(-)
diff --git a/hw/msi.c b/hw/msi.c
index f03f519..3dc3a24 100644
--- a/hw/msi.c
+++ b/hw/msi.c
@@ -255,7 +255,6 @@ void msi_write_config(PCIDevice *dev
So far pci_device_reset() is used for system reset.
In that case, interrupt controller is also reset so that
all irq is are deasserted.
But now pci bus reset/flr is supported, and in that case irq needs to be
disabled explicitly.
Isaku Yamahata (3):
pci: deassert intx on reset.
msi: simply
use pci_device_deassert_intx().
Signed-off-by: Isaku Yamahata
---
hw/msix.c |5 +
1 files changed, 1 insertions(+), 4 deletions(-)
diff --git a/hw/msix.c b/hw/msix.c
index e123082..daaf9b7 100644
--- a/hw/msix.c
+++ b/hw/msix.c
@@ -159,7 +159,6 @@ void msix_write_config(PCIDevice *dev
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