> -Original Message-
> From: Jason Wang [mailto:jasow...@redhat.com]
> Sent: Thursday, January 6, 2022 10:34 AM
> To: Michael S. Tsirkin
> Cc: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
> ; Stefan Hajnoczi ; Stefano
> Garzarella ; Cornelia Huck ; pbonzini
> ; Gonglei
On Tue, 4 Jan 2022 12:58:05 -0500
Stefan Berger wrote:
> Add missing TPM device identification objects _STR and _UID. They will
> appear as files 'description' and 'uid' under Linux sysfs.
>
> Following inspection of sysfs entries for hardware TPMs we chose
> uid '1'.
My guess would be that
Web camera is an important port of a desktop instance, QEMU supports
USB passthrough and USB redirect to support for general cases.
Several problems we have hit:
1, the heavy bandwidth of network. a 1080*720@30FPS(MJPEG) uses
~5MB/s.
2, Issues of USB passthrough, Ex USB reset from guest
Hi Richard,
On Wed, 05 Jan 2022 21:36:55 +,
Richard Henderson wrote:
>
> On 1/3/22 10:05 AM, Marc Zyngier wrote:
> > -/*
> > - * KVM does not support modifications to this feature.
> > - * We have not registered the cpu properties when KVM
> > - * is in use,
On Wed, Nov 10, 2021 at 05:42:19PM +0100, Antonio Caggiano wrote:
> From: Gerd Hoffmann
>
> Use VIRTIO_GPU_SHM_ID_HOST_VISIBLE as id for virtio-gpu.
>
> Signed-off-by: Antonio Caggiano
I guess Gerd can apply this as appropriate.
Acked-by: Michael S. Tsirkin
> ---
>
Based-on: <20220106074740.1754661-1-gaos...@loongson.cn>
Hi all,
This series only support linux-user emulation.
More about LoongArch at: https://github.com/loongson/
The latest kernel:
* https://github.com/loongson/linux/tree/loongarch-next
Patches need review:
*
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
linux-user/loongarch64/signal.c| 198 +
linux-user/loongarch64/target_signal.h | 13 ++
2 files changed, 211 insertions(+)
create mode 100644 linux-user/loongarch64/signal.c
create mode 100644
This includes:
- FLD.{S/D}, FST.{S/D}
- FLDX.{S/D}, FSTX.{S/D}
- FLD{GT/LE}.{S/D}, FST{GT/LE}.{S/D}
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
.../loongarch/insn_trans/trans_fmemory.c.inc | 153 ++
target/loongarch/insns.decode
On 5/1/22 10:50, Kostiantyn Kostiuk wrote:
Signed-off-by: Kostiantyn Kostiuk
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
This includes:
- EXT.W.{B/H}
- CL{O/Z}.{W/D}, CT{O/Z}.{W/D}
- BYTEPICK.{W/D}
- REVB.{2H/4H/2W/D}
- REVH.{2W/D}
- BITREV.{4B/8B}, BITREV.{W/D}
- BSTRINS.{W/D}, BSTRPICK.{W/D}
- MASKEQZ, MASKNEZ
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
This patch series reduces the playback latency for audio backends,
in some cases significantly. For PulseAudio, the audio buffer is
also moved from the QEMU side to the PulseAudio server side. This
improves the drop-out safety for PulseAudio.
I actually measured the latency reduction with the
On 6/1/22 08:47, Song Gao wrote:
TARGET_SIGSTKSZ is not used, we should remove it.
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
linux-user/alpha/target_signal.h | 1 -
linux-user/generic/signal.h | 1 -
linux-user/hppa/target_signal.h | 1 -
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
This patch adds loongarch64 linux-user default configs file.
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
configs/targets/loongarch64-linux-user.mak | 3 +++
1 file changed, 3 insertions(+)
create mode 100644
This patch adds support for disassembling via option '-d in_asm'.
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
include/disas/dis-asm.h | 2 +
meson.build | 1 +
target/loongarch/disas.c | 612 +++
This includes:
- LL.{W/D}, SC.{W/D}
- AM{SWAP/ADD/AND/OR/XOR/MAX/MIN}[_DB].{W/D}
- AM{MAX/MIN}[_DB].{WU/DU}
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
.../loongarch/insn_trans/trans_atomic.c.inc | 114 ++
On Wed, Nov 10, 2021 at 05:42:20PM +0100, Antonio Caggiano wrote:
> From: "Dr. David Alan Gilbert"
>
> Define a new capability type 'VIRTIO_PCI_CAP_SHARED_MEMORY_CFG'
> and the data structure 'virtio_pci_shm_cap' to go with it.
> They allow defining shared memory regions with sizes and offsets
>
This includes:
- FCMP.cond.{S/D}
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
target/loongarch/fpu_helper.c| 60
target/loongarch/helper.h| 9 +++
target/loongarch/insn_trans/trans_fcmp.c.inc
Aakarshit Agarwal writes:
> Hello Sir/Ma'am,
>
> I am Aakarshit Agarwal, final year student pursuing B.Tech in computer
> science with a specialization in DevOps from UPES Dehradun. I
> love the topic and technologies you used for GSoC'21. I would love to
> contribute to your organization
On Mon, 6 Dec 2021 14:42:55 +0100
Thomas Huth wrote:
> When running "qemu-system-x86_64 -M pc,help" I noticed that some
> properties were still missing their description. Add them now so
> that users get at least a slightly better idea what they are all
> about.
>
> Signed-off-by: Thomas Huth
On Wed, Jan 05, 2022 at 06:24:25PM -0500, Steven Sistare wrote:
> On 1/5/2022 6:09 PM, Michael S. Tsirkin wrote:
> > On Wed, Jan 05, 2022 at 04:40:43PM -0500, Steven Sistare wrote:
> >> On 1/5/2022 4:14 PM, Michael S. Tsirkin wrote:
> >>> On Wed, Jan 05, 2022 at 12:24:21PM -0500, Steven Sistare
This includes:
- F{ADD/SUB/MUL/DIV}.{S/D}
- F{MADD/MSUB/NMADD/NMSUB}.{S/D}
- F{MAX/MIN}.{S/D}
- F{MAXA/MINA}.{S/D}
- F{ABS/NEG}.{S/D}
- F{SQRT/RECIP/RSQRT}.{S/D}
- F{SCALEB/LOGB/COPYSIGN}.{S/D}
- FCLASS.{S/D}
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
ping
On 12/22/21 12:30 PM, Li Zhang wrote:
Cleanup multifd_send_thread
Signed-off-by: Li Zhang
---
migration/multifd.c | 82 ++---
1 file changed, 41 insertions(+), 41 deletions(-)
diff --git a/migration/multifd.c b/migration/multifd.c
index
Am Thu, 6 Jan 2022 10:23:18 +0100
schrieb Volker Rümelin :
> From: Volker Rümelin
>
> Replace open-coded buffer arithmetic with the available function
> audio_ring_dist(). Because the name audio_ring_dist implies it
> calculates the distance between two points, define the alias
> function name
Coroutine pool size was 64 from long ago, and the basis was organized in the
commit message in c740ad92.
At that time, virtio-blk queue-size and num-queue were not configuable, and
equivalent values were 128 and 1.
Coroutine pool size 64 was fine then.
Later queue-size and num-queue got
We encountered random disk IO performance drop since qemu-5.0.0, and this patch
fixes it.
Commit message in c740ad92 implied to adjust coroutine pool size adaptively, so
I tried to implement this.
Could you review this patch?
Hiroki Narukawa (1):
util: adjust coroutine pool size to virtio
v1 -> v2:
[missing CC qemu-devel@nongnu.org, resend]
Separate v1 patch set into 2 parts:
Introduce camera subsystem (this one).
USB desc fix and UVC.
Add maintainer infomation.
v1:
1, The full picture of this patch set:
+-+ ++ +---+
Cc'ing Stefan / Paolo.
On 6/1/22 09:20, Hiroki Narukawa wrote:
Coroutine pool size was 64 from long ago, and the basis was organized in the
commit message in c740ad92.
At that time, virtio-blk queue-size and num-queue were not configuable, and
equivalent values were 128 and 1.
Coroutine
This patch adds main translation routines and
basic functions for translation.
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
target/loongarch/helper.h| 6 ++
target/loongarch/op_helper.c | 21 +
target/loongarch/translate.c | 159
This includes:
- BEQ, BNE, BLT[U], BGE[U]
- BEQZ, BNEZ
- B
- BL
- JIRL
- BCEQZ, BCNEZ
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
.../loongarch/insn_trans/trans_branch.c.inc | 83 +++
target/loongarch/insns.decode |
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
configure | 3 +
linux-user/loongarch64/cpu_loop.c | 94 +
linux-user/loongarch64/target_cpu.h | 34 +++
3 files changed, 131 insertions(+)
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
linux-user/elfload.c| 53 +
linux-user/loongarch64/target_elf.h | 12 +++
2 files changed, 65 insertions(+)
create mode
This includes:
- sockbits.h
- target_errno_defs.h
- target_fcntl.h
- termbits.h
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
linux-user/loongarch64/sockbits.h | 11 +++
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
linux-user/loongarch64/target_structs.h | 47 +
1 file changed, 47 insertions(+)
create mode 100644 linux-user/loongarch64/target_structs.h
diff --git a/linux-user/loongarch64/target_structs.h
On Tue, Dec 21, 2021 at 03:32:32PM +0100, Lukasz Maniak wrote:
> From: Knut Omang
>
> This patch provides the building blocks for creating an SR/IOV
> PCIe Extended Capability header and register/unregister
> SR/IOV Virtual Functions.
>
> Signed-off-by: Knut Omang
> ---
> hw/pci/meson.build
This includes:
- FMOV.{S/D}
- FSEL
- MOVGR2FR.{W/D}, MOVGR2FRH.W
- MOVFR2GR.{S/D}, MOVFRH2GR.S
- MOVGR2FCSR, MOVFCSR2GR
- MOVFR2CF, MOVCF2FR
- MOVGR2CF, MOVCF2GR
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
target/loongarch/fpu_helper.c
This includes:
- CRC[C].W.{B/H/W/D}.W
- SYSCALL
- BREAK
- ASRT{LE/GT}.D
- RDTIME{L/H}.W, RDTIME.D
- CPUCFG
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
target/loongarch/helper.h | 4 +
This patch gives an introduction to the LoongArch target.
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
MAINTAINERS | 5 +++
target/loongarch/README | 77 +
2 files changed, 82 insertions(+)
create
This patch adds target state header, target definitions
and initialization routines.
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
target/loongarch/cpu-param.h | 18 ++
target/loongarch/cpu.c | 314
This includes:
- LD.{B[U]/H[U]/W[U]/D}, ST.{B/H/W/D}
- LDX.{B[U]/H[U]/W[U]/D}, STX.{B/H/W/D}
- LDPTR.{W/D}, STPTR.{W/D}
- PRELD
- LD{GT/LE}.{B/H/W/D}, ST{GT/LE}.{B/H/W/D}
- DBAR, IBAR
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
ping
Any comments?
Thanks
Li
On 12/17/21 11:12 AM, Li Zhang wrote:
Clean up some unnecessary code
Signed-off-by: Li Zhang
---
migration/multifd.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/migration/multifd.c b/migration/multifd.c
index
This patch adds build loongarch-linux-user target support.
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
target/loongarch/meson.build | 19 +++
target/meson.build | 1 +
2 files changed,
TARGET_SIGSTKSZ is not used, we should remove it.
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
linux-user/alpha/target_signal.h | 1 -
linux-user/generic/signal.h | 1 -
linux-user/hppa/target_signal.h | 1 -
linux-user/mips/target_signal.h | 1 -
On 1/5/22 22:23, Daniel Henrique Barboza wrote:
Hi,
This second version was rebased with upstream and includes fixed/amended
versions of relevant patches that were sent to the mailing list and aren't
upstream yet. In this process 4 patches from v1 were discarded, becoming
either irrelevant or
On Tue, Dec 14, 2021 at 2:39 AM Frédéric Pétrot
wrote:
>
> This series of patches provides partial 128-bit support for the riscv
> target architecture, namely RVI and RVM, with minimal csr support.
>
> Thanks again for the reviews and advices.
I think this is all reviewed now. I was getting an
Hello,
Thanks for you answer!
I may put together a patch to crash if VEX.L is 1 (shouldn't be hard) and
submit it to the patch list.
Do you think it qualifies as "trivial patch" or should i go on with the
full patch submission process?
On Thu, Jan 6, 2022 at 3:45 AM Richard Henderson <
We should disable '__BITS_PER_LONG' at [1] before run gensyscalls.sh
[1] arch/loongarch/include/uapi/asm/bitsperlong.h
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
linux-user/loongarch64/syscall_nr.h | 313
This includes:
- SLL.W, SRL.W, SRA.W, ROTR.W
- SLLI.W, SRLI.W, SRAI.W, ROTRI.W
- SLL.D, SRL.D, SRA.D, ROTR.D
- SLLI.D, SRLI.D, SRAI.D, ROTRI.D
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
target/loongarch/insn_trans/trans_shift.c.inc | 106
On Thu, Nov 11, 2021 at 06:33:44PM +0300, Roman Kagan wrote:
> Error propagation between the generic vhost code and the specific backends is
> not quite consistent: some places follow "return -1 and set errno" convention,
> while others assume "return negated errno". Furthermore, not enough care
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
scripts/qemu-binfmt-conf.sh | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/scripts/qemu-binfmt-conf.sh b/scripts/qemu-binfmt-conf.sh
index 7de996d536..da6a937be8 100755
---
On a Linux platform, user process could accesses /dev/videoX to
capture video frames.
We can run QEMU like this:
qemu-system-x86_64 ... -cameradev v4l2,path=/dev/video0,id=camera0
To test a /dev/videoX device support video capture, install v4l-utils
package and run command:
~# v4l2-ctl
This includes:
- FCVT.S.D, FCVT.D.S
- FFINT.{S/D}.{W/L}, FTINT.{W/L}.{S/D}
- FTINT{RM/RP/RZ/RNE}.{W/L}.{S/D}
- FRINT.{S/D}
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
target/loongarch/fpu_helper.c| 393 +++
On 06/01/2022 22:24, Alistair Francis wrote:
On Fri, Jan 7, 2022 at 7:04 AM Frédéric Pétrot
wrote:
This patch adds the support of the '-cpu rv128' option to
qemu-system-riscv64 so that we can indicate that we want to run rv128
executables.
Still, there is no support for 128-bit insns at that
On Fri, Jan 7, 2022 at 4:23 PM Frédéric Pétrot
wrote:
>
> On 06/01/2022 22:24, Alistair Francis wrote:
> > On Fri, Jan 7, 2022 at 7:04 AM Frédéric Pétrot
> > wrote:
> >>
> >> This patch adds the support of the '-cpu rv128' option to
> >> qemu-system-riscv64 so that we can indicate that we want
On 1/7/2022 12:06 AM, Laszlo Ersek wrote:
On 01/04/22 14:08, Xiaoyao Li wrote:
+ Laszlo,
Regarding laoding TDVF as pflash, I have some questions:
- pflash requires KVM to support readonly mmeory. However, for TDX, it
doesn't support readonly memory. Is it a must? or we can make an
exception
On Fri, Jan 7, 2022 at 10:14 AM Atish Patra wrote:
>
> From: Atish Patra
>
> Currently, the predicate function for PMU related CSRs only works if
> virtualization is enabled. It also does not check mcounteren bits before
> before cycle/minstret/hpmcounterx access.
>
> Support supervisor mode
On 05/01/2022 10:48, Thomas Huth wrote:
Add some documentation files to the corresponding machine sections
and mention the machine names in the section titles where it is
not so obvious (e.g. that "taihu" is a 405 machine).
Signed-off-by: Thomas Huth
---
MAINTAINERS | 12
1
On 05/01/2022 20.52, Lucas Ramage wrote:
Hi Thomas,
I intentionally sent the email via my gmx address. But I want my commit under
the infinite-omicron email address.
I had a few warnings on my end, but it builds fine with Sphinx v3.4.3 on Debian
Bullseye. I can clean up the warnings in the
"PowerPC Processor binding to IEEE 1275" says in
"8.2.1. Initial Register Values" that the initial state is defined as
32bit so do it for both SLOF and VOF.
This should not cause behavioral change as SLOF switches to 64bit very
early anyway. As nothing enforces LE anywhere, this drops it for VOF.
On 06/01/2022 13.22, Laurent Vivier wrote:
"qemu-system-m68k -M q800 -bios /dev/null" crahses with a segfault
in q800_init().
This happens because the code doesn't check that rom_ptr() returned
a non-NULL pointer .
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/756
Reported-by: Peter
On 1/7/22 08:24, Alexey Kardashevskiy wrote:
"PowerPC Processor binding to IEEE 1275" says in
"8.2.1. Initial Register Values" that the initial state is defined as
32bit so do it for both SLOF and VOF.
This should not cause behavioral change as SLOF switches to 64bit very
early anyway. As
On Fri, Jan 7, 2022 at 10:18 AM Atish Patra wrote:
>
> The RISC-V privilege specification provides flexibility to implement
> any number of counters from 29 programmable counters. However, the QEMU
> implements all the counters.
>
> Make it configurable through pmu config parameter which now will
imestamp: Thu Jan 6 15:45:42 2022
$ rbd --conf /etc/ceph/ceph-dev01.conf --id lieven snap ls
dhp-standard/c4ca7ee9-36ce-4fc9-9d3b-ece8a4f8b83e/c1ad11d0-4f6a-4cc1-8aa3-ff3c413c1471.raw
SNAPID NAME SIZE PROTECTED TIMESTAMP
12297 dlp-20210921-144509 20 GiB Tue Se
On Tue, 28 Dec 2021 at 03:34, Troy Lee wrote:
>
> Hi Klaus,
>
> On Thu, Dec 23, 2021 at 11:57 PM Klaus Heinrich Kiwi
> wrote:
> >
> > Em qui., 23 de dez. de 2021 às 09:54, Cédric Le Goater
> > escreveu:
> > >
> > > [ Adding Klaus ]
> >
> > Thanks Cedric. It's been a while since I've looked at
On Thu, 6 Jan 2022 at 15:45, Alex Bennée wrote:
> Peter Maydell writes:
> > Yeah, that trick only works for the real CPU object, not for
> > passing to SoC or SoC-like objects.
>
> Hmm I wonder if I should be instantiating the underlying CPU object?
> AIUI the cores are cortex-m0+ so I assume
On Tue, 4 Jan 2022 12:58:04 -0500
Stefan Berger wrote:
> Replace existing TPM related tables, that are about to change, with
> empty files.
>
> Cc: Michael S. Tsirkin
> Cc: Igor Mammedov
> Cc: Ani Sinha
> Signed-off-by: Stefan Berger
> Acked-by: Ani Sinha
> Message-id:
On Thu, 16 Dec 2021 at 06:48, Byron Lathi wrote:
>
> Add support for the Cortex-A5. These changes are based off of the A7 and
> A9 Init functions, using the appropriate values from the technical
> reference manual for the A5.
>
> Signed-off-by: Byron Lathi
> ---
> target/arm/cpu_tcg.c | 36
On 1/6/22 1:16 AM, Marc Zyngier wrote:
+static bool kvm_arm_pauth_supported(void)
+{
+return (kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_ADDRESS) &&
+kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_GENERIC));
+}
Do we really need to have them both set to play the
On 1/6/22 11:55, Igor Mammedov wrote:
On Thu, 6 Jan 2022 09:01:36 -0500
Stefan Berger wrote:
On 1/6/22 08:56, Michael S. Tsirkin wrote:
On Thu, Jan 06, 2022 at 08:53:00AM -0500, Stefan Berger wrote:
On 1/6/22 03:36, Igor Mammedov wrote:
On Tue, 4 Jan 2022 12:58:05 -0500
Stefan Berger
This patch series reduces the playback latency for audio backends,
in some cases significantly. For PulseAudio, the audio buffer is
also moved from the QEMU side to the PulseAudio server side. This
improves the drop-out safety for PulseAudio.
Volker Rümelin (15):
audio: replace open-coded
The AVX instruction set is not supported by Qemu.
However, some AVX instructions are properly decoded and emulated as their
legacy SSE version.
This patch prevent this by generating an illegal_op instead of a bogus SSE
instruction.
Signed-off-by: Stevie Lavern
---
target/i386/tcg/translate.c |
From: Richard Henderson
Leave TARGET_ALIGNED_ONLY set, but use the new CPUState
flag to set MO_UNALN for the instructions that the kernel
handles in the unaligned trap.
Signed-off-by: Richard Henderson
Reviewed-by: Laurent Vivier
Message-Id:
From: Richard Henderson
The first word of page1 is data, so the whole thing
can't be implemented with emulation of addresses.
Use init_guest_commpage for the allocation.
Hijack trap number 16 to implement cmpxchg.
Signed-off-by: Richard Henderson
Reviewed-by: Laurent Vivier
Message-Id:
在 2022/1/6 19:00, Eric Auger 写道:
Hi CHenxiangn
On 12/29/21 8:13 AM, chenxiang (M) via wrote:
Hi Eric,
在 2021/10/5 16:53, Eric Auger 写道:
Add a 'preserve_config' field in struct GPEXConfig and
if set generate the DSM #5 for preserving PCI boot configurations.
The DSM presence is needed to
On Wed, 5 Jan 2022 at 21:05, Alex Bennée wrote:
> Can't be added as a subregion to the container...
>
> qemu-system-arm: ../../softmmu/memory.c:2538:
> memory_region_add_subregion_common: Assertion `!subregion->container' failed.
This assert means you tried to add the same MemoryRegion
as a
No one objected, so I think we can go for the 11th.
On Thu, Jan 06, 2022 at 12:21:56PM +0100, Mark Burton wrote:
> Can we confirm the 11th for this meeting?
>
> Cheers
> Mark.
>
>
> > On 4 Jan 2022, at 10:29, Edgar E. Iglesias wrote:
> >
> >
> >
> > On Tue, Dec 14, 2021 at 3:49 PM Markus
xscmpnedp was added in ISA v3.0 but removed in v3.0B. This patch
removes this instruction as it was not in the final version of v3.0.
RFC to know if you think this is the correct approach.
Signed-off-by: Víctor Colombo
---
target/ppc/fpu_helper.c | 1 -
target/ppc/helper.h
On 1/6/22 05:18, Cédric Le Goater wrote:
On 1/5/22 22:23, Daniel Henrique Barboza wrote:
Hi,
This second version was rebased with upstream and includes fixed/amended
versions of relevant patches that were sent to the mailing list and aren't
upstream yet. In this process 4 patches from v1
On 1/6/22 06:30, David Gibson wrote:
On Wed, Jan 05, 2022 at 05:40:26PM -0300, Fabiano Rosas wrote:
The ppc_interrupts_little_endian function could be used for interrupts
delivered in Hypervisor mode, so add support for powernv8 and powernv9
to it.
Also drop the comment because it is
Big changes that were tagged originally but did not make the cut:
- SRIOV/nvme (not sure they are my tree material anyway)
- TPM (blocked over Igor's compat concerns)
- ACPI ERST (some coding style violations)
The following changes since commit 7d4ae4d4978079d564d3b6354c90a949130409fe:
Merge
From: Cindy Lu
Add functions to support configure interrupt.
The configure interrupt process will start in vhost_dev_start
and stop in vhost_dev_stop.
Also add the functions to support vhost_config_pending and
vhost_config_mask, for masked_config_notifier, we only
use the notifier saved in vq
From: David Hildenbrand
If we warn about the block size being smaller than the default, we skip
some alignment checks.
This can currently only fail on x86-64, when specifying a block size of
1 MiB, however, we detect the THP size of 2 MiB.
Fixes: 228957fea3a9 ("virtio-mem: Probe THP size to
From: Frederic Barrat
Skip triggering an LSI when the AER root error status is updated if no
LSI is defined for the device. We can have a root bridge with no LSI,
MSI and MSI-X defined, for example on POWER systems.
Signed-off-by: Frederic Barrat
Message-Id:
From: Thomas Huth
When running "qemu-system-x86_64 -M pc,help" I noticed that some
properties were still missing their description. Add them now so
that users get at least a slightly better idea what they are all
about.
Signed-off-by: Thomas Huth
Message-Id:
From: David Hildenbrand
Temporarily modifying the SIGBUS handler is really nasty, as we might be
unlucky and receive an MCE SIGBUS while having our handler registered.
Unfortunately, there is no way around messing with SIGBUS when
MADV_POPULATE_WRITE is not applicable or not around.
Let's
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Message-Id: <20211227193120.1084176-5-imamm...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
tests/qtest/bios-tables-test-allowed-diff.h | 2 --
tests/data/acpi/q35/FACP.slic | Bin 244 -> 244
From: David Hildenbrand
For scarce memory resources, such as hugetlb, we want to be able to
prealloc such memory resources in order to not crash later on access. On
simple user errors we could otherwise easily run out of memory resources
an crash the VM -- pretty much undesired.
For ordinary
From: Thomas Huth
The virtio-balloon-stats documentation might be useful for people that
are implementing software that talks to QEMU via QMP, so this should
reside in the docs/interop/ directory. While we're at it, also convert
the file to restructured text and mention it in the MAINTAINERS
From: David Hildenbrand
Let's limit the number of threads to something sane, especially that
- We don't have more threads than the number of pages we have
- We don't have threads that initialize small (< 64 MiB) memory
Reviewed-by: Pankaj Gupta
Reviewed-by: Dr. David Alan Gilbert
Reviewed-by:
From: Cindy Lu
To reuse the notifier process in configure interrupt.
Use the virtio_pci_get_notifier function to get the notifier.
the INPUT of this function is the IDX, the OUTPUT is notifier and
the vector
Signed-off-by: Cindy Lu
Message-Id: <20211104164827.21911-3-l...@redhat.com>
When commit 0643c12e4b dropped the 'x-' prefix for Zb[abcs] and set
them to be enabled by default, the comment about experimental
extensions was kept in place above them. This moves it down a few
lines to only cover experimental extensions.
References: 0643c12e4b ("target/riscv: Enable bitmanip
On 1/5/22 22:23, Daniel Henrique Barboza wrote:
The next step before enabling user creatable pnv-phb4 devices is to
decople the init of the stack->phb object from
pnv_pec_stk_instance_init().
First, use 'defaults_enabled()' inside pnv_pec_realize() to create the
stack->phb object, while
Peter Maydell writes:
> On Wed, 5 Jan 2022 at 21:05, Alex Bennée wrote:
>> Can't be added as a subregion to the container...
>>
>> qemu-system-arm: ../../softmmu/memory.c:2538:
>> memory_region_add_subregion_common: Assertion `!subregion->container' failed.
>
> This assert means you tried
On 1/5/22 22:23, Daniel Henrique Barboza wrote:
At this moment, stack->phb is the plain PnvPHB4 device itself instead
of a pointer to the device. This will present a problem when adding user
creatable devices because we can't deal with this struct and the
realize() callback from the user
On Mon, 22 Nov 2021 at 11:11, Philippe Mathieu-Daudé wrote:
>
> Mention in aux_bus_init() docstring that the AUXBus
> is not simply initialized, it is also allocated.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/hw/misc/auxbus.h | 12 +++-
> 1 file changed, 7 insertions(+),
From: Volker Rümelin
This is a patch to improve the pulseaudio playback experience.
Asking pulseaudio for a playback latency of 15ms is quite
demanding. Increase this to 46ms. The total playback latency
now is 31ms larger. One of the next patches will reduce the
total playback latency again by
From: Volker Rümelin
Now that the mixing buffer size no longer adds to playback
latency, fix the samples vs. frames mix-up in the mixing buffer
size calculation. This change will go largely unnoticed as long
as the user doesn't use a buffer-size smaller than timer-period.
Signed-off-by: Volker
From: Volker Rümelin
Add the buffer_get_free pcm_ops function to reduce the effective
playback buffer size. All intermediate audio playback buffers
become temporary buffers.
Signed-off-by: Volker Rümelin
---
audio/paaudio.c | 33 -
1 file changed, 24
Peter Maydell writes:
> On Thu, 6 Jan 2022 at 14:26, Alex Bennée wrote:
>>
>>
>> Peter Maydell writes:
>>
>> > On Wed, 5 Jan 2022 at 21:05, Alex Bennée wrote:
>> >> Can't be added as a subregion to the container...
>> >>
>> >> qemu-system-arm: ../../softmmu/memory.c:2538:
>> >>
On 1/6/22 13:36, Daniel Henrique Barboza wrote:
On 1/6/22 05:18, Cédric Le Goater wrote:
On 1/5/22 22:23, Daniel Henrique Barboza wrote:
Hi,
This second version was rebased with upstream and includes fixed/amended
versions of relevant patches that were sent to the mailing list and aren't
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