** Changed in: qemu
Status: Fix Committed => Fix Released
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https://bugs.launchpad.net/bugs/1863247
Title:
AArch64 EXT instruction for V register does not clear MSB side bits
St
All of those, and tbl, tbx, ins, are fixed in the three subsequent
commits.
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https://bugs.launchpad.net/bugs/1863247
Title:
AArch64 EXT instruction for V register does not clear MSB si
Thank you for bug fix.
I found trn1, trn2, zip1, zip2, uz1, uz2 instructions seem to have same bug.
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https://bugs.launchpad.net/bugs/1863247
Title:
AArch64 EXT instruction for V regist
Fixed here:
https://git.qemu.org/?p=qemu.git;a=commitdiff;h=78cedfabd53b
** Changed in: qemu
Status: In Progress => Fix Committed
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Title:
Yep.
** Changed in: qemu
Status: New => In Progress
** Changed in: qemu
Assignee: (unassigned) => Richard Henderson (rth)
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Title:
