CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: jmcneill
Date: Sun Aug 8 13:43:09 UTC 2021
Modified Files:
src/sys/arch/arm/arm: smccc.c
Log Message:
fix armv7 build
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/arm/smccc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/smccc.c
diff -u src/sys/arch/arm/arm/smccc.c:1.2 src/sys/arch/arm/arm/smccc.c:1.3
--- src/sys/arch/arm/arm/smccc.c:1.2 Sat Aug 7 21:21:49 2021
+++ src/sys/arch/arm/arm/smccc.c Sun Aug 8 13:43:09 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: smccc.c,v 1.2 2021/08/07 21:21:49 jmcneill Exp $ */
+/* $NetBSD: smccc.c,v 1.3 2021/08/08 13:43:09 jmcneill Exp $ */
/*-
* Copyright (c) 2021 Jared McNeill
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: smccc.c,v 1.2 2021/08/07 21:21:49 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: smccc.c,v 1.3 2021/08/08 13:43:09 jmcneill Exp $");
#include
#include
@@ -35,6 +35,12 @@ __KERNEL_RCSID(0, "$NetBSD: smccc.c,v 1.
#include
#include
+#if defined(__arm__)
+#define SMCCC_ARCH_ATTRIBUTE __attribute__ ((target("arch=armv7ve")))
+#else
+#define SMCCC_ARCH_ATTRIBUTE
+#endif
+
/* Minimum supported PSCI version for SMCCC discovery */
#define PSCI_VERSION_1_0 0x1
@@ -89,7 +95,7 @@ smccc_version(void)
*
* Generic call interface for SMC/HVC calls.
*/
-int
+SMCCC_ARCH_ATTRIBUTE int
smccc_call(uint32_t fid,
register_t arg1, register_t arg2, register_t arg3, register_t arg4,
register_t *res0, register_t *res1, register_t *res2, register_t *res3)
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: jmcneill
Date: Sat Aug 7 21:21:49 UTC 2021
Modified Files:
src/sys/arch/arm/arm: smccc.c smccc.h
Log Message:
arm: SMCCC: Add return values to smccc_call
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/arm/smccc.c \
src/sys/arch/arm/arm/smccc.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/smccc.c
diff -u src/sys/arch/arm/arm/smccc.c:1.1 src/sys/arch/arm/arm/smccc.c:1.2
--- src/sys/arch/arm/arm/smccc.c:1.1 Fri Aug 6 19:38:53 2021
+++ src/sys/arch/arm/arm/smccc.c Sat Aug 7 21:21:49 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: smccc.c,v 1.1 2021/08/06 19:38:53 jmcneill Exp $ */
+/* $NetBSD: smccc.c,v 1.2 2021/08/07 21:21:49 jmcneill Exp $ */
/*-
* Copyright (c) 2021 Jared McNeill
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: smccc.c,v 1.1 2021/08/06 19:38:53 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: smccc.c,v 1.2 2021/08/07 21:21:49 jmcneill Exp $");
#include
#include
@@ -42,7 +42,10 @@ __KERNEL_RCSID(0, "$NetBSD: smccc.c,v 1.
#define SMCCC_VERSION 0x8000
/* True if SMCCC is detected. */
-static bool smccc_present;
+static bool smccc_present;
+
+/* SMCCC conduit (SMC or HVC) */
+static enum psci_conduit smccc_conduit = PSCI_CONDUIT_NONE;
/*
* smccc_probe --
@@ -58,6 +61,13 @@ smccc_probe(void)
}
smccc_present = psci_features(SMCCC_VERSION) == PSCI_SUCCESS;
+ if (smccc_present) {
+ smccc_conduit = psci_conduit();
+
+ aprint_debug("SMCCC: Version %#x (%s)\n",
+ smccc_version(),
+ smccc_conduit == PSCI_CONDUIT_SMC ? "SMC" : "HVC");
+ }
}
return smccc_present;
}
@@ -70,7 +80,8 @@ smccc_probe(void)
int
smccc_version(void)
{
- return smccc_call(SMCCC_VERSION, 0, 0, 0);
+ return smccc_call(SMCCC_VERSION, 0, 0, 0, 0,
+ NULL, NULL, NULL, NULL);
}
/*
@@ -79,11 +90,54 @@ smccc_version(void)
* Generic call interface for SMC/HVC calls.
*/
int
-smccc_call(register_t fid, register_t arg1, register_t arg2, register_t arg3)
+smccc_call(uint32_t fid,
+register_t arg1, register_t arg2, register_t arg3, register_t arg4,
+register_t *res0, register_t *res1, register_t *res2, register_t *res3)
{
+ register_t args[5] = { fid, arg1, arg2, arg3, arg4 };
+
+ register register_t r0 asm ("r0");
+ register register_t r1 asm ("r1");
+ register register_t r2 asm ("r2");
+ register register_t r3 asm ("r3");
+ register register_t r4 asm ("r4");
+
if (!smccc_present) {
return SMCCC_NOT_SUPPORTED;
}
- return psci_call(fid, arg1, arg2, arg3);
+ KASSERT(smccc_conduit != PSCI_CONDUIT_NONE);
+
+ r0 = args[0];
+ r1 = args[1];
+ r2 = args[2];
+ r3 = args[3];
+ r4 = args[4];
+
+ if (smccc_conduit == PSCI_CONDUIT_SMC) {
+ asm volatile ("smc #0" :
+ "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3) :
+ "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4) :
+ "memory");
+ } else {
+ asm volatile ("hvc #0" :
+ "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3) :
+ "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4) :
+ "memory");
+ }
+
+ if (res0) {
+ *res0 = r0;
+ }
+ if (res1) {
+ *res1 = r1;
+ }
+ if (res2) {
+ *res2 = r2;
+ }
+ if (res3) {
+ *res3 = r3;
+ }
+
+ return r0;
}
Index: src/sys/arch/arm/arm/smccc.h
diff -u src/sys/arch/arm/arm/smccc.h:1.1 src/sys/arch/arm/arm/smccc.h:1.2
--- src/sys/arch/arm/arm/smccc.h:1.1 Fri Aug 6 19:38:53 2021
+++ src/sys/arch/arm/arm/smccc.h Sat Aug 7 21:21:49 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: smccc.h,v 1.1 2021/08/06 19:38:53 jmcneill Exp $ */
+/* $NetBSD: smccc.h,v 1.2 2021/08/07 21:21:49 jmcneill Exp $ */
/*-
* Copyright (c) 2021 Jared McNeill
@@ -50,6 +50,7 @@ int smccc_version(void);
/*
* Call an SMC/HVC service.
*/
-int smccc_call(register_t, register_t, register_t, register_t);
+int smccc_call(uint32_t, register_t, register_t, register_t, register_t,
+ register_t *, register_t *, register_t *, register_t *);
#endif /* _ARM_SMCCC_H */
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: jmcneill
Date: Sat Aug 7 21:20:14 UTC 2021
Modified Files:
src/sys/arch/arm/arm: psci.c psci.h
Log Message:
arm: PSCI: Add a function to return the PSCI conduit.
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/arm/psci.c
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/arm/psci.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/psci.c
diff -u src/sys/arch/arm/arm/psci.c:1.6 src/sys/arch/arm/arm/psci.c:1.7
--- src/sys/arch/arm/arm/psci.c:1.6 Fri Aug 6 19:38:53 2021
+++ src/sys/arch/arm/arm/psci.c Sat Aug 7 21:20:14 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: psci.c,v 1.6 2021/08/06 19:38:53 jmcneill Exp $ */
+/* $NetBSD: psci.c,v 1.7 2021/08/07 21:20:14 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: psci.c,v 1.6 2021/08/06 19:38:53 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: psci.c,v 1.7 2021/08/07 21:20:14 jmcneill Exp $");
#include
#include
@@ -68,6 +68,18 @@ psci_call(register_t fid, register_t arg
return psci_call_fn(fid, arg1, arg2, arg3);
}
+enum psci_conduit
+psci_conduit(void)
+{
+ if (psci_call_fn == psci_call_smc) {
+ return PSCI_CONDUIT_SMC;
+ } else if (psci_call_fn == psci_call_hvc) {
+ return PSCI_CONDUIT_HVC;
+ } else {
+ return PSCI_CONDUIT_NONE;
+ }
+}
+
uint32_t
psci_version(void)
{
Index: src/sys/arch/arm/arm/psci.h
diff -u src/sys/arch/arm/arm/psci.h:1.3 src/sys/arch/arm/arm/psci.h:1.4
--- src/sys/arch/arm/arm/psci.h:1.3 Fri Aug 6 19:38:53 2021
+++ src/sys/arch/arm/arm/psci.h Sat Aug 7 21:20:14 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: psci.h,v 1.3 2021/08/06 19:38:53 jmcneill Exp $ */
+/* $NetBSD: psci.h,v 1.4 2021/08/07 21:20:14 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill
@@ -42,6 +42,15 @@ enum psci_function {
};
/*
+ * Possible PSCI conduits.
+ */
+enum psci_conduit {
+ PSCI_CONDUIT_NONE,
+ PSCI_CONDUIT_SMC,
+ PSCI_CONDUIT_HVC,
+};
+
+/*
* PSCI error codes
*/
#define PSCI_SUCCESS 0
@@ -71,6 +80,11 @@ void psci_init(psci_fn);
bool psci_available(void);
/*
+ * Return the PSCI conduit type.
+ */
+enum psci_conduit psci_conduit(void);
+
+/*
* PSCI call methods, implemented in psci.S
*/
int psci_call_smc(register_t, register_t, register_t, register_t);
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: skrll Date: Fri Jul 2 07:15:35 UTC 2021 Modified Files: src/sys/arch/arm/arm: cpufunc.c Log Message: Be consistent about #ifndef ARM32_DISABLE_ALIGNMENT_FAULTS. NFCI. To generate a diff of this commit: cvs rdiff -u -r1.180 -r1.181 src/sys/arch/arm/arm/cpufunc.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/cpufunc.c diff -u src/sys/arch/arm/arm/cpufunc.c:1.180 src/sys/arch/arm/arm/cpufunc.c:1.181 --- src/sys/arch/arm/arm/cpufunc.c:1.180 Sun Jan 31 05:59:55 2021 +++ src/sys/arch/arm/arm/cpufunc.c Fri Jul 2 07:15:35 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: cpufunc.c,v 1.180 2021/01/31 05:59:55 skrll Exp $ */ +/* $NetBSD: cpufunc.c,v 1.181 2021/07/02 07:15:35 skrll Exp $ */ /* * arm7tdmi support code Copyright (c) 2001 John Fremlin @@ -49,7 +49,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.180 2021/01/31 05:59:55 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.181 2021/07/02 07:15:35 skrll Exp $"); #include "opt_arm_start.h" #include "opt_compat_netbsd.h" @@ -2868,10 +2868,10 @@ pj4bv7_setup(char *args) pj4b_config(); cpuctrl = CPU_CONTROL_MMU_ENABLE; -#ifdef ARM32_DISABLE_ALIGNMENT_FAULTS - cpuctrl |= CPU_CONTROL_UNAL_ENABLE; -#else +#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS cpuctrl |= CPU_CONTROL_AFLT_ENABLE; +#else + cpuctrl |= CPU_CONTROL_UNAL_ENABLE; #endif cpuctrl |= CPU_CONTROL_DC_ENABLE; cpuctrl |= CPU_CONTROL_IC_ENABLE;
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Sun Feb 21 08:47:13 UTC 2021
Modified Files:
src/sys/arch/arm/arm: arm_machdep.c
Log Message:
KNF consistency
To generate a diff of this commit:
cvs rdiff -u -r1.66 -r1.67 src/sys/arch/arm/arm/arm_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/arm_machdep.c
diff -u src/sys/arch/arm/arm/arm_machdep.c:1.66 src/sys/arch/arm/arm/arm_machdep.c:1.67
--- src/sys/arch/arm/arm/arm_machdep.c:1.66 Sun Feb 21 08:46:28 2021
+++ src/sys/arch/arm/arm/arm_machdep.c Sun Feb 21 08:47:13 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: arm_machdep.c,v 1.66 2021/02/21 08:46:28 skrll Exp $ */
+/* $NetBSD: arm_machdep.c,v 1.67 2021/02/21 08:47:13 skrll Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -80,7 +80,7 @@
#include
-__KERNEL_RCSID(0, "$NetBSD: arm_machdep.c,v 1.66 2021/02/21 08:46:28 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: arm_machdep.c,v 1.67 2021/02/21 08:47:13 skrll Exp $");
#include
#include
@@ -310,12 +310,14 @@ cpu_intr_p(void)
struct lwp *
arm_curlwp(void)
{
+
return curlwp;
}
struct cpu_info *
arm_curcpu(void)
{
+
return curcpu();
}
#endif
@@ -340,6 +342,7 @@ cpu_kpreempt_exit(uintptr_t where)
bool
cpu_kpreempt_disabled(void)
{
+
return curcpu()->ci_cpl != IPL_NONE;
}
#endif /* __HAVE_PREEMPTION */
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Sun Feb 21 08:46:28 UTC 2021
Modified Files:
src/sys/arch/arm/arm: arm_machdep.c
Log Message:
Some preemption updates - still not being used (yet)
To generate a diff of this commit:
cvs rdiff -u -r1.65 -r1.66 src/sys/arch/arm/arm/arm_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/arm_machdep.c
diff -u src/sys/arch/arm/arm/arm_machdep.c:1.65 src/sys/arch/arm/arm/arm_machdep.c:1.66
--- src/sys/arch/arm/arm/arm_machdep.c:1.65 Tue Dec 1 02:43:13 2020
+++ src/sys/arch/arm/arm/arm_machdep.c Sun Feb 21 08:46:28 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: arm_machdep.c,v 1.65 2020/12/01 02:43:13 rin Exp $ */
+/* $NetBSD: arm_machdep.c,v 1.66 2021/02/21 08:46:28 skrll Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -80,7 +80,7 @@
#include
-__KERNEL_RCSID(0, "$NetBSD: arm_machdep.c,v 1.65 2020/12/01 02:43:13 rin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: arm_machdep.c,v 1.66 2021/02/21 08:46:28 skrll Exp $");
#include
#include
@@ -223,6 +223,8 @@ void
cpu_need_resched(struct cpu_info *ci, struct lwp *l, int flags)
{
+ KASSERT(kpreempt_disabled());
+
if (flags & RESCHED_IDLE) {
#ifdef MULTIPROCESSOR
/*
@@ -322,13 +324,17 @@ arm_curcpu(void)
bool
cpu_kpreempt_enter(uintptr_t where, int s)
{
+
+ KASSERT(kpreempt_disabled());
+
return s == IPL_NONE;
}
void
cpu_kpreempt_exit(uintptr_t where)
{
- atomic_and_uint(()->ci_astpending, (unsigned int)~__BIT(1));
+
+ /* do nothing */
}
bool
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: skrll Date: Wed Feb 17 06:54:23 UTC 2021 Modified Files: src/sys/arch/arm/arm: idle_machdep.c Log Message: Trailing whitespace. *snigger* To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/arm/idle_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/idle_machdep.c diff -u src/sys/arch/arm/arm/idle_machdep.c:1.5 src/sys/arch/arm/arm/idle_machdep.c:1.6 --- src/sys/arch/arm/arm/idle_machdep.c:1.5 Sun Aug 18 06:28:18 2013 +++ src/sys/arch/arm/arm/idle_machdep.c Wed Feb 17 06:54:23 2021 @@ -1,11 +1,11 @@ -/* $NetBSD: idle_machdep.c,v 1.5 2013/08/18 06:28:18 matt Exp $ */ +/* $NetBSD: idle_machdep.c,v 1.6 2021/02/17 06:54:23 skrll Exp $ */ /*- * Copyright (c) 2007 The NetBSD Foundation, Inc. * All rights reserved. * * This code is derived from software contributed to The NetBSD Foundation - * by Nick Hudson + * by Nick Hudson * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -31,7 +31,7 @@ #include -__KERNEL_RCSID(0, "$NetBSD: idle_machdep.c,v 1.5 2013/08/18 06:28:18 matt Exp $"); +__KERNEL_RCSID(0, "$NetBSD: idle_machdep.c,v 1.6 2021/02/17 06:54:23 skrll Exp $"); #include #include
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: skrll Date: Sun Jan 31 05:59:55 UTC 2021 Modified Files: src/sys/arch/arm/arm: cpufunc.c Log Message: One #include "opt_cputypes.h" is enough for anyone To generate a diff of this commit: cvs rdiff -u -r1.179 -r1.180 src/sys/arch/arm/arm/cpufunc.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/cpufunc.c diff -u src/sys/arch/arm/arm/cpufunc.c:1.179 src/sys/arch/arm/arm/cpufunc.c:1.180 --- src/sys/arch/arm/arm/cpufunc.c:1.179 Tue Dec 1 02:46:19 2020 +++ src/sys/arch/arm/arm/cpufunc.c Sun Jan 31 05:59:55 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: cpufunc.c,v 1.179 2020/12/01 02:46:19 rin Exp $ */ +/* $NetBSD: cpufunc.c,v 1.180 2021/01/31 05:59:55 skrll Exp $ */ /* * arm7tdmi support code Copyright (c) 2001 John Fremlin @@ -49,7 +49,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.179 2020/12/01 02:46:19 rin Exp $"); +__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.180 2021/01/31 05:59:55 skrll Exp $"); #include "opt_arm_start.h" #include "opt_compat_netbsd.h" @@ -90,7 +90,6 @@ __KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v #endif #if defined(CPU_PJ4B) -#include "opt_cputypes.h" #include "opt_mvsoc.h" #include #if defined(ARMADAXP)
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: skrll Date: Wed Jan 27 13:50:17 UTC 2021 Modified Files: src/sys/arch/arm/arm: armv6_start.S Log Message: Trailing whitespace... heh To generate a diff of this commit: cvs rdiff -u -r1.33 -r1.34 src/sys/arch/arm/arm/armv6_start.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/armv6_start.S diff -u src/sys/arch/arm/arm/armv6_start.S:1.33 src/sys/arch/arm/arm/armv6_start.S:1.34 --- src/sys/arch/arm/arm/armv6_start.S:1.33 Tue Dec 1 13:11:55 2020 +++ src/sys/arch/arm/arm/armv6_start.S Wed Jan 27 13:50:17 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: armv6_start.S,v 1.33 2020/12/01 13:11:55 skrll Exp $ */ +/* $NetBSD: armv6_start.S,v 1.34 2021/01/27 13:50:17 skrll Exp $ */ /*- * Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc. @@ -578,9 +578,9 @@ generic_vstartv6: /* SWP is only usable on uni-processor ARMv7 systems. */ #ifdef MULTIPROCESSOR -#define CPU_CONTROL_XP_SWP_ENABLE 0 +#define CPU_CONTROL_XP_SWP_ENABLE 0 #else -#define CPU_CONTROL_XP_SWP_ENABLE CPU_CONTROL_SWP_ENABLE +#define CPU_CONTROL_XP_SWP_ENABLE CPU_CONTROL_SWP_ENABLE #endif // bits to set in the Control Register
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Fri Dec 18 07:40:27 UTC 2020
Modified Files:
src/sys/arch/arm/arm: efi_runtime.c
Log Message:
Make this compile on arm
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/arm/efi_runtime.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/efi_runtime.c
diff -u src/sys/arch/arm/arm/efi_runtime.c:1.4 src/sys/arch/arm/arm/efi_runtime.c:1.5
--- src/sys/arch/arm/arm/efi_runtime.c:1.4 Tue Sep 8 17:20:10 2020
+++ src/sys/arch/arm/arm/efi_runtime.c Fri Dec 18 07:40:27 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: efi_runtime.c,v 1.4 2020/09/08 17:20:10 jmcneill Exp $ */
+/* $NetBSD: efi_runtime.c,v 1.5 2020/12/18 07:40:27 skrll Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: efi_runtime.c,v 1.4 2020/09/08 17:20:10 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: efi_runtime.c,v 1.5 2020/12/18 07:40:27 skrll Exp $");
#include
#include
@@ -67,8 +67,8 @@ arm_efirt_init(paddr_t efi_system_table)
ST = (void *)(va + (efi_system_table - trunc_page(efi_system_table)));
if (ST->st_hdr.th_sig != EFI_SYSTBL_SIG) {
- aprint_error("EFI: signature mismatch (%#lx != %#lx)\n",
- ST->st_hdr.th_sig, EFI_SYSTBL_SIG);
+ aprint_error("EFI: signature mismatch (%#" PRIx64 " != %#"
+ PRIx64 ")\n", ST->st_hdr.th_sig, EFI_SYSTBL_SIG);
return EINVAL;
}
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: dholland
Date: Fri Dec 11 09:14:19 UTC 2020
Modified Files:
src/sys/arch/arm/arm: bcopyinout.S
Log Message:
arm copyin/out: make copyin not use copyout's epilogue (typo in labels)
The epilogues are the same, so this is harmless, but if they ever
changed (e.g. after rearranging the register usage) it would be broken
in a very confusing way.
To generate a diff of this commit:
cvs rdiff -u -r1.21 -r1.22 src/sys/arch/arm/arm/bcopyinout.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/bcopyinout.S
diff -u src/sys/arch/arm/arm/bcopyinout.S:1.21 src/sys/arch/arm/arm/bcopyinout.S:1.22
--- src/sys/arch/arm/arm/bcopyinout.S:1.21 Wed Jan 24 09:04:44 2018
+++ src/sys/arch/arm/arm/bcopyinout.S Fri Dec 11 09:14:19 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: bcopyinout.S,v 1.21 2018/01/24 09:04:44 skrll Exp $ */
+/* $NetBSD: bcopyinout.S,v 1.22 2020/12/11 09:14:19 dholland Exp $ */
/*
* Copyright (c) 2002 Wasabi Systems, Inc.
@@ -52,7 +52,7 @@
#include "bcopyinout_xscale.S"
#else
-RCSID("$NetBSD: bcopyinout.S,v 1.21 2018/01/24 09:04:44 skrll Exp $")
+RCSID("$NetBSD: bcopyinout.S,v 1.22 2020/12/11 09:14:19 dholland Exp $")
.text
.align 0
@@ -239,7 +239,7 @@ ENTRY(copyin)
* If we're done, bail.
*/
cmp r2, #0
- beq .Lout
+ beq .Liout
.Licleanup:
and r6, r2, #0x3
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: skrll Date: Fri Dec 4 08:00:53 UTC 2020 Modified Files: src/sys/arch/arm/arm: psci.c Log Message: Trailing whitespace To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/arm/psci.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/psci.c diff -u src/sys/arch/arm/arm/psci.c:1.3 src/sys/arch/arm/arm/psci.c:1.4 --- src/sys/arch/arm/arm/psci.c:1.3 Sat Oct 13 00:07:55 2018 +++ src/sys/arch/arm/arm/psci.c Fri Dec 4 08:00:53 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: psci.c,v 1.3 2018/10/13 00:07:55 jmcneill Exp $ */ +/* $NetBSD: psci.c,v 1.4 2020/12/04 08:00:53 skrll Exp $ */ /*- * Copyright (c) 2017 Jared McNeill @@ -29,7 +29,7 @@ #include "opt_diagnostic.h" #include -__KERNEL_RCSID(0, "$NetBSD: psci.c,v 1.3 2018/10/13 00:07:55 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: psci.c,v 1.4 2020/12/04 08:00:53 skrll Exp $"); #include #include @@ -66,7 +66,7 @@ psci_call(register_t fid, register_t arg return PSCI_NOT_SUPPORTED; return psci_call_fn(fid, arg1, arg2, arg3); -} +} uint32_t psci_version(void)
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: skrll Date: Tue Dec 1 13:11:55 UTC 2020 Modified Files: src/sys/arch/arm/arm: armv6_start.S Log Message: Simplify the simplification... basically always set sctlr.u before setting cpsr.e To generate a diff of this commit: cvs rdiff -u -r1.32 -r1.33 src/sys/arch/arm/arm/armv6_start.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/armv6_start.S diff -u src/sys/arch/arm/arm/armv6_start.S:1.32 src/sys/arch/arm/arm/armv6_start.S:1.33 --- src/sys/arch/arm/arm/armv6_start.S:1.32 Tue Dec 1 08:35:31 2020 +++ src/sys/arch/arm/arm/armv6_start.S Tue Dec 1 13:11:55 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: armv6_start.S,v 1.32 2020/12/01 08:35:31 skrll Exp $ */ +/* $NetBSD: armv6_start.S,v 1.33 2020/12/01 13:11:55 skrll Exp $ */ /*- * Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc. @@ -96,12 +96,10 @@ ENTRY_NP(generic_start) #if defined(__ARMEB__) -#if defined(_ARM_ARCH_6) - /* Make sure U bit is always set with E bit in SCTLR. */ + /* Make sure sctlr.u = 1 when cpsr.e = 1. */ mrc p15, 0, R_TMP1, c1, c0, 0 orr R_TMP1, R_TMP1, #CPU_CONTROL_UNAL_ENABLE mcr p15, 0, R_TMP1, c1, c0, 0 -#endif setend be /* force big endian */ #endif
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: skrll Date: Tue Dec 1 08:35:31 UTC 2020 Modified Files: src/sys/arch/arm/arm: armv6_start.S Log Message: Simplify previous To generate a diff of this commit: cvs rdiff -u -r1.31 -r1.32 src/sys/arch/arm/arm/armv6_start.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/armv6_start.S diff -u src/sys/arch/arm/arm/armv6_start.S:1.31 src/sys/arch/arm/arm/armv6_start.S:1.32 --- src/sys/arch/arm/arm/armv6_start.S:1.31 Tue Dec 1 02:46:19 2020 +++ src/sys/arch/arm/arm/armv6_start.S Tue Dec 1 08:35:31 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: armv6_start.S,v 1.31 2020/12/01 02:46:19 rin Exp $ */ +/* $NetBSD: armv6_start.S,v 1.32 2020/12/01 08:35:31 skrll Exp $ */ /*- * Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc. @@ -96,15 +96,14 @@ ENTRY_NP(generic_start) #if defined(__ARMEB__) -# if defined(_ARM_ARCH_7) - setend be /* force big endian */ -# else /* _ARM_ARCH_6 */ +#if defined(_ARM_ARCH_6) /* Make sure U bit is always set with E bit in SCTLR. */ mrc p15, 0, R_TMP1, c1, c0, 0 orr R_TMP1, R_TMP1, #CPU_CONTROL_UNAL_ENABLE mcr p15, 0, R_TMP1, c1, c0, 0 - setend be -# endif +#endif + + setend be /* force big endian */ #endif /* disable IRQs/FIQs. */
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: rin
Date: Tue Dec 1 02:46:19 UTC 2020
Modified Files:
src/sys/arch/arm/arm: armv6_start.S cpufunc.c
Log Message:
Fix earmv6{,hf}eb start-up routines:
- Turn on U-bit in SCTLR before E-bit is turned on by ``setend be'',
in order to avoid undefined condition. ARM1176JZF-S, at least, halts
if only E-bit is turned on.
- Turn on EE-bit in SCTLR instead of B-bit as we've switched to BE8.
To generate a diff of this commit:
cvs rdiff -u -r1.30 -r1.31 src/sys/arch/arm/arm/armv6_start.S
cvs rdiff -u -r1.178 -r1.179 src/sys/arch/arm/arm/cpufunc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/armv6_start.S
diff -u src/sys/arch/arm/arm/armv6_start.S:1.30 src/sys/arch/arm/arm/armv6_start.S:1.31
--- src/sys/arch/arm/arm/armv6_start.S:1.30 Tue Oct 13 21:06:18 2020
+++ src/sys/arch/arm/arm/armv6_start.S Tue Dec 1 02:46:19 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: armv6_start.S,v 1.30 2020/10/13 21:06:18 skrll Exp $ */
+/* $NetBSD: armv6_start.S,v 1.31 2020/12/01 02:46:19 rin Exp $ */
/*-
* Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc.
@@ -95,9 +95,16 @@
ENTRY_NP(generic_start)
- // ARMv7 only?!?
#if defined(__ARMEB__)
+# if defined(_ARM_ARCH_7)
setend be /* force big endian */
+# else /* _ARM_ARCH_6 */
+ /* Make sure U bit is always set with E bit in SCTLR. */
+ mrc p15, 0, R_TMP1, c1, c0, 0
+ orr R_TMP1, R_TMP1, #CPU_CONTROL_UNAL_ENABLE
+ mcr p15, 0, R_TMP1, c1, c0, 0
+ setend be
+# endif
#endif
/* disable IRQs/FIQs. */
@@ -1086,6 +1093,11 @@ Lcontrol_set:
#else
#define CPU_CONTROL_EXTRA CPU_CONTROL_SYST_ENABLE
#endif
+#if defined(__ARMEL__)
+#define CPU_CONTROL_EX_BEND_SET 0
+#else
+#define CPU_CONTROL_EX_BEND_SET CPU_CONTROL_EX_BEND
+#endif
.word CPU_CONTROL_MMU_ENABLE | \
CPU_CONTROL_WBUF_ENABLE |/* not defined in 1176 (SBO) */ \
CPU_CONTROL_32BP_ENABLE |/* SBO */ \
@@ -1094,7 +1106,8 @@ Lcontrol_set:
(1 << 16) | /* SBO - Global enable for data tcm */ \
(1 << 18) | /* SBO - Global enable for insn tcm */ \
CPU_CONTROL_UNAL_ENABLE | \
- CPU_CONTROL_EXTRA
+ CPU_CONTROL_EXTRA | \
+ CPU_CONTROL_EX_BEND_SET
/* bits to clear in the Control Register */
Lcontrol_clr:
Index: src/sys/arch/arm/arm/cpufunc.c
diff -u src/sys/arch/arm/arm/cpufunc.c:1.178 src/sys/arch/arm/arm/cpufunc.c:1.179
--- src/sys/arch/arm/arm/cpufunc.c:1.178 Fri Oct 30 18:54:36 2020
+++ src/sys/arch/arm/arm/cpufunc.c Tue Dec 1 02:46:19 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.178 2020/10/30 18:54:36 skrll Exp $ */
+/* $NetBSD: cpufunc.c,v 1.179 2020/12/01 02:46:19 rin Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.178 2020/10/30 18:54:36 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.179 2020/12/01 02:46:19 rin Exp $");
#include "opt_arm_start.h"
#include "opt_compat_netbsd.h"
@@ -2769,6 +2769,11 @@ arm11_setup(char *args)
#endif
| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
/* | CPU_CONTROL_BPRD_ENABLE */;
+
+#ifdef __ARMEB__
+ cpuctrl |= CPU_CONTROL_EX_BEND;
+#endif
+
int cpuctrlmask = cpuctrl
| CPU_CONTROL_ROM_ENABLE | CPU_CONTROL_BPRD_ENABLE
| CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE
@@ -2780,10 +2785,6 @@ arm11_setup(char *args)
cpuctrl = parse_cpu_options(args, arm11_options, cpuctrl);
-#ifdef __ARMEB__
- cpuctrl |= CPU_CONTROL_BEND_ENABLE;
-#endif
-
#ifndef ARM_HAS_VBAR
if (vector_page == ARM_VECTORS_HIGH)
cpuctrl |= CPU_CONTROL_VECRELOC;
@@ -2818,6 +2819,11 @@ arm11mpcore_setup(char *args)
| CPU_CONTROL_XP_ENABLE
#endif
| CPU_CONTROL_BPRD_ENABLE ;
+
+#ifdef __ARMEB__
+ cpuctrl |= CPU_CONTROL_EX_BEND;
+#endif
+
int cpuctrlmask = cpuctrl
| CPU_CONTROL_AFLT_ENABLE
| CPU_CONTROL_VECRELOC;
@@ -3057,6 +3063,10 @@ arm11x6_setup(char *args)
#endif
CPU_CONTROL_IC_ENABLE;
+#ifdef __ARMEB__
+ cpuctrl |= CPU_CONTROL_EX_BEND;
+#endif
+
/*
* "write as existing" bits
* inverse of this is mask
@@ -3075,10 +3085,6 @@ arm11x6_setup(char *args)
cpuctrl = parse_cpu_options(args, arm11_options, cpuctrl);
-#ifdef __ARMEB__
- cpuctrl |= CPU_CONTROL_BEND_ENABLE;
-#endif
-
#ifndef ARM_HAS_VBAR
if (vector_page == ARM_VECTORS_HIGH)
cpuctrl |= CPU_CONTROL_VECRELOC;
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Mon Nov 30 21:06:56 UTC 2020
Modified Files:
src/sys/arch/arm/arm: cpu_subr.c
Log Message:
Ensure stores are observed before the 'sev' instructions.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/arm/cpu_subr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpu_subr.c
diff -u src/sys/arch/arm/arm/cpu_subr.c:1.1 src/sys/arch/arm/arm/cpu_subr.c:1.2
--- src/sys/arch/arm/arm/cpu_subr.c:1.1 Sat Feb 15 08:16:10 2020
+++ src/sys/arch/arm/arm/cpu_subr.c Mon Nov 30 21:06:56 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_subr.c,v 1.1 2020/02/15 08:16:10 skrll Exp $ */
+/* $NetBSD: cpu_subr.c,v 1.2 2020/11/30 21:06:56 skrll Exp $ */
/*-
* Copyright (c) 2020 The NetBSD Foundation, Inc.
@@ -33,13 +33,15 @@
#include "opt_multiprocessor.h"
#include
-__KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.1 2020/02/15 08:16:10 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.2 2020/11/30 21:06:56 skrll Exp $");
#include
#include
#include
#include
+#include
+
#ifdef VERBOSE_INIT_ARM
#define VPRINTF(...) printf(__VA_ARGS__)
#else
@@ -86,7 +88,8 @@ cpu_boot_secondary_processors(void)
for (size_t n = 0; n < __arraycount(arm_cpu_mbox); n++)
atomic_or_ulong(_cpu_mbox[n], arm_cpu_hatched[n]);
- __asm __volatile ("sev; sev; sev");
+ dsb(ishst);
+ __asm __volatile ("sev");
/* wait all cpus have done cpu_hatch() */
for (cpuno = 1; cpuno < ncpu; cpuno++) {
@@ -136,7 +139,8 @@ cpu_clr_mbox(int cpuindex)
/* Notify cpu_boot_secondary_processors that we're done */
atomic_and_ulong(_cpu_mbox[off], ~bit);
membar_producer();
- __asm __volatile("sev; sev; sev");
+ dsb(ishst);
+ __asm __volatile("sev");
}
#endif
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: rin Date: Thu Nov 12 01:03:22 UTC 2020 Modified Files: src/sys/arch/arm/arm: cpu_exec.c Log Message: If neither COMPAT_NETBSD32 nor MODULAR is defined, there's no chance for lwp to be running under COMPAT_NETBSD32. Suggested by mrg. To generate a diff of this commit: cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/arm/cpu_exec.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/cpu_exec.c diff -u src/sys/arch/arm/arm/cpu_exec.c:1.11 src/sys/arch/arm/arm/cpu_exec.c:1.12 --- src/sys/arch/arm/arm/cpu_exec.c:1.11 Tue Nov 10 21:40:07 2020 +++ src/sys/arch/arm/arm/cpu_exec.c Thu Nov 12 01:03:22 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: cpu_exec.c,v 1.11 2020/11/10 21:40:07 rin Exp $ */ +/* $NetBSD: cpu_exec.c,v 1.12 2020/11/12 01:03:22 rin Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. @@ -30,7 +30,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: cpu_exec.c,v 1.11 2020/11/10 21:40:07 rin Exp $"); +__KERNEL_RCSID(0, "$NetBSD: cpu_exec.c,v 1.12 2020/11/12 01:03:22 rin Exp $"); #include "opt_compat_netbsd.h" @@ -55,7 +55,11 @@ arm_netbsd_elf32_probe(struct lwp *l, st const Elf_Ehdr * const eh = eh0; const bool elf_aapcs_p = (eh->e_flags & EF_ARM_EABIMASK) >= EF_ARM_EABI_VER4; +#if defined(COMPAT_NETBSD32) || defined(MODULAR) const bool netbsd32_p = (epp->ep_esch->es_emul != _netbsd); +#else + const bool netbsd32_p = false; +#endif #ifdef __ARM_EABI__ const bool aapcs_p = true; #else
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: rin Date: Tue Nov 10 21:40:07 UTC 2020 Modified Files: src/sys/arch/arm/arm: cpu_exec.c Log Message: Test (epp->ep_esch->es_emul != _netbsd) instead of (epp->ep_esch->es_emul == _netbsd32) to determine whether curlwp is running on COMPAT_NETBSD32 or not. The former is possible even if COMPAT_NETBSD32 is not built in the main kernel. Now, compat_netbsd32 module can work on !COMPAT_NETBSD32 kernel. Discussed with pgoyette. XXX Apply similar fixes, i.e., drop ``#ifdef COMPAT_NETBSD32'' conditional codes from the rest parts of MD codes for aarch64 and mips64. To generate a diff of this commit: cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/arm/cpu_exec.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/cpu_exec.c diff -u src/sys/arch/arm/arm/cpu_exec.c:1.10 src/sys/arch/arm/arm/cpu_exec.c:1.11 --- src/sys/arch/arm/arm/cpu_exec.c:1.10 Mon Apr 27 06:54:12 2015 +++ src/sys/arch/arm/arm/cpu_exec.c Tue Nov 10 21:40:07 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: cpu_exec.c,v 1.10 2015/04/27 06:54:12 skrll Exp $ */ +/* $NetBSD: cpu_exec.c,v 1.11 2020/11/10 21:40:07 rin Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. @@ -30,10 +30,9 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: cpu_exec.c,v 1.10 2015/04/27 06:54:12 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: cpu_exec.c,v 1.11 2020/11/10 21:40:07 rin Exp $"); #include "opt_compat_netbsd.h" -#include "opt_compat_netbsd32.h" #include #include @@ -45,10 +44,6 @@ __KERNEL_RCSID(0, "$NetBSD: cpu_exec.c,v #include #include /* mandatory */ -#ifdef COMPAT_NETBSD32 -#include -#endif - #include #if EXEC_ELF32 @@ -60,11 +55,7 @@ arm_netbsd_elf32_probe(struct lwp *l, st const Elf_Ehdr * const eh = eh0; const bool elf_aapcs_p = (eh->e_flags & EF_ARM_EABIMASK) >= EF_ARM_EABI_VER4; -#ifdef COMPAT_NETBSD32 - const bool netbsd32_p = (epp->ep_esch->es_emul == _netbsd32); -#else - const bool netbsd32_p = false; -#endif + const bool netbsd32_p = (epp->ep_esch->es_emul != _netbsd); #ifdef __ARM_EABI__ const bool aapcs_p = true; #else
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: rin
Date: Tue Nov 10 21:38:03 UTC 2020
Modified Files:
src/sys/arch/arm/arm: core_machdep.c
Log Message:
Stop turning on EABI flag to core files dumped by OABI binaries.
This seems a bug introduced in rev 1.5:
http://cvsweb.netbsd.org/bsdweb.cgi/src/sys/arch/arm/arm/core_machdep.c#rev1.5
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/arm/core_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/core_machdep.c
diff -u src/sys/arch/arm/arm/core_machdep.c:1.9 src/sys/arch/arm/arm/core_machdep.c:1.10
--- src/sys/arch/arm/arm/core_machdep.c:1.9 Wed Nov 20 19:37:51 2019
+++ src/sys/arch/arm/arm/core_machdep.c Tue Nov 10 21:38:03 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: core_machdep.c,v 1.9 2019/11/20 19:37:51 pgoyette Exp $ */
+/* $NetBSD: core_machdep.c,v 1.10 2020/11/10 21:38:03 rin Exp $ */
/*
* Copyright (c) 1994-1998 Mark Brinicombe.
@@ -37,11 +37,10 @@
#include
-__KERNEL_RCSID(0, "$NetBSD: core_machdep.c,v 1.9 2019/11/20 19:37:51 pgoyette Exp $");
+__KERNEL_RCSID(0, "$NetBSD: core_machdep.c,v 1.10 2020/11/10 21:38:03 rin Exp $");
#ifdef _KERNEL_OPT
#include "opt_execfmt.h"
-#include "opt_compat_netbsd32.h"
#else
#define EXEC_ELF32 1
#endif
@@ -61,9 +60,6 @@ __KERNEL_RCSID(0, "$NetBSD: core_machdep
#ifdef EXEC_ELF32
#include
-#ifdef COMPAT_NETBSD32
-#include
-#endif
#endif
#include
@@ -120,21 +116,16 @@ cpu_coredump(struct lwp *l, struct cored
void
arm_netbsd_elf32_coredump_setup(struct lwp *l, void *arg)
{
-#if defined(__ARMEB__) || defined(__ARM_EABI__) || defined(COMPAT_NETBSD32)
+#if defined(__ARMEB__) || defined(__ARM_EABI__)
Elf_Ehdr * const eh = arg;
-#if defined(__ARM_EABI__) || defined(COMPAT_NETBSD32)
+#endif
+#ifdef __ARM_EABI__
struct proc * const p = l->l_proc;
-#ifdef __ARM_EABI__
if (p->p_emul == _netbsd) {
eh->e_flags |= EF_ARM_EABI_VER5;
}
-#elif defined(COMPAT_NETBSD32)
- if (p->p_emul == _netbsd32) {
- eh->e_flags |= EF_ARM_EABI_VER5;
- }
#endif
-#endif /* __ARM_EABI__ || COMPAT_NETBSD32 */
#ifdef __ARMEB__
if (CPU_IS_ARMV7_P()
|| (CPU_IS_ARMV6_P()
@@ -142,6 +133,5 @@ arm_netbsd_elf32_coredump_setup(struct l
eh->e_flags |= EF_ARM_BE8;
}
#endif
-#endif
}
#endif
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: skrll Date: Tue Oct 13 21:06:18 UTC 2020 Modified Files: src/sys/arch/arm/arm: armv6_start.S Log Message: Remove some XXXNHs To generate a diff of this commit: cvs rdiff -u -r1.29 -r1.30 src/sys/arch/arm/arm/armv6_start.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/armv6_start.S diff -u src/sys/arch/arm/arm/armv6_start.S:1.29 src/sys/arch/arm/arm/armv6_start.S:1.30 --- src/sys/arch/arm/arm/armv6_start.S:1.29 Tue Sep 22 00:55:08 2020 +++ src/sys/arch/arm/arm/armv6_start.S Tue Oct 13 21:06:18 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: armv6_start.S,v 1.29 2020/09/22 00:55:08 mrg Exp $ */ +/* $NetBSD: armv6_start.S,v 1.30 2020/10/13 21:06:18 skrll Exp $ */ /*- * Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc. @@ -721,7 +721,6 @@ armv7_mmuinit: mov r4, lr mov r5, r0 // save TTBR - // XXXNH dsb - Why? XPUTC(#'F') dsb// Drain the write buffers. @@ -755,7 +754,6 @@ armv7_mmuinit: mov r1, #0 // get KERNEL_PID mcr p15, 0, r1, c13, c0, 1 // CONTEXTIDR write - // XXXNH FreeBSD doesn't do this isb isb // Set the Domain Access register. Very important!
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: skrll Date: Thu Sep 24 11:02:02 UTC 2020 Modified Files: src/sys/arch/arm/arm: bus_space_asm_generic.S Log Message: Trailing whitespace To generate a diff of this commit: cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/arm/bus_space_asm_generic.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/bus_space_asm_generic.S diff -u src/sys/arch/arm/arm/bus_space_asm_generic.S:1.11 src/sys/arch/arm/arm/bus_space_asm_generic.S:1.12 --- src/sys/arch/arm/arm/bus_space_asm_generic.S:1.11 Mon Oct 28 22:50:25 2013 +++ src/sys/arch/arm/arm/bus_space_asm_generic.S Thu Sep 24 11:02:02 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: bus_space_asm_generic.S,v 1.11 2013/10/28 22:50:25 matt Exp $ */ +/* $NetBSD: bus_space_asm_generic.S,v 1.12 2020/09/24 11:02:02 skrll Exp $ */ /* * Copyright (c) 1997 Causality Limited. @@ -529,7 +529,7 @@ ENTRY_NP(generic_armv4_bs_c_2) adds r0, r0, r2 adds r1, r1, r2 - negs r2, r2 + negs r2, r2 1: ldrh r3, [r0, r2] strh r3, [r1, r2]
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: mrg Date: Tue Sep 22 00:55:09 UTC 2020 Modified Files: src/sys/arch/arm/arm: armv6_start.S Log Message: swp is only useful on armv7 uni-processor systems. we will need the emulation if we want to run old binaries.. To generate a diff of this commit: cvs rdiff -u -r1.28 -r1.29 src/sys/arch/arm/arm/armv6_start.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/armv6_start.S diff -u src/sys/arch/arm/arm/armv6_start.S:1.28 src/sys/arch/arm/arm/armv6_start.S:1.29 --- src/sys/arch/arm/arm/armv6_start.S:1.28 Mon Sep 21 21:26:43 2020 +++ src/sys/arch/arm/arm/armv6_start.S Tue Sep 22 00:55:08 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: armv6_start.S,v 1.28 2020/09/21 21:26:43 mrg Exp $ */ +/* $NetBSD: armv6_start.S,v 1.29 2020/09/22 00:55:08 mrg Exp $ */ /*- * Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc. @@ -572,6 +572,13 @@ generic_vstartv6: #define CPU_CONTROL_XP_ENABLE_SET 0 #endif +/* SWP is only usable on uni-processor ARMv7 systems. */ +#ifdef MULTIPROCESSOR +#define CPU_CONTROL_XP_SWP_ENABLE 0 +#else +#define CPU_CONTROL_XP_SWP_ENABLE CPU_CONTROL_SWP_ENABLE +#endif + // bits to set in the Control Register // #define CPU_CONTROL_SET ( \ @@ -660,7 +667,7 @@ armv7_init: #define ARMV7_SCTLR_SET ( \ CPU_CONTROL_UNAL_ENABLE | \ -CPU_CONTROL_SWP_ENABLE | \ +CPU_CONTROL_XP_SWP_ENABLE | \ 0) mrc p15, 0, r0, c1, c0, 0
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: mrg Date: Mon Sep 21 21:26:43 UTC 2020 Modified Files: src/sys/arch/arm/arm: armv6_start.S Log Message: turn on CPU_CONTROL_SWP_ENABLE. this allows armv[67] systems to use 'swp' and 'swpb' instructions, which means they can run armv[45] software. arm recommends ldrex/strex for armv6 and newer, and it is not present in armv8 at all or some armv7. we emulate it on armv8 and need to add emulation for the some armv7. using the hardware is going to be faster, so, enable this path too. ok jmcneill. To generate a diff of this commit: cvs rdiff -u -r1.27 -r1.28 src/sys/arch/arm/arm/armv6_start.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/armv6_start.S diff -u src/sys/arch/arm/arm/armv6_start.S:1.27 src/sys/arch/arm/arm/armv6_start.S:1.28 --- src/sys/arch/arm/arm/armv6_start.S:1.27 Fri Aug 28 13:36:52 2020 +++ src/sys/arch/arm/arm/armv6_start.S Mon Sep 21 21:26:43 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: armv6_start.S,v 1.27 2020/08/28 13:36:52 skrll Exp $ */ +/* $NetBSD: armv6_start.S,v 1.28 2020/09/21 21:26:43 mrg Exp $ */ /*- * Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc. @@ -660,6 +660,7 @@ armv7_init: #define ARMV7_SCTLR_SET ( \ CPU_CONTROL_UNAL_ENABLE | \ +CPU_CONTROL_SWP_ENABLE | \ 0) mrc p15, 0, r0, c1, c0, 0
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: skrll Date: Mon Sep 21 10:35:12 UTC 2020 Modified Files: src/sys/arch/arm/arm: undefined.c Log Message: Allow an undefined instruction to use lr (r14) as Rt. New gcc emits this with TPIDRURO read. Not sure why the exception handler cares if sp or pc are used as Rt To generate a diff of this commit: cvs rdiff -u -r1.66 -r1.67 src/sys/arch/arm/arm/undefined.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/undefined.c diff -u src/sys/arch/arm/arm/undefined.c:1.66 src/sys/arch/arm/arm/undefined.c:1.67 --- src/sys/arch/arm/arm/undefined.c:1.66 Tue Oct 1 18:00:07 2019 +++ src/sys/arch/arm/arm/undefined.c Mon Sep 21 10:35:12 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: undefined.c,v 1.66 2019/10/01 18:00:07 chs Exp $ */ +/* $NetBSD: undefined.c,v 1.67 2020/09/21 10:35:12 skrll Exp $ */ /* * Copyright (c) 2001 Ben Harris. @@ -55,7 +55,7 @@ #include #endif -__KERNEL_RCSID(0, "$NetBSD: undefined.c,v 1.66 2019/10/01 18:00:07 chs Exp $"); +__KERNEL_RCSID(0, "$NetBSD: undefined.c,v 1.67 2020/09/21 10:35:12 skrll Exp $"); #include #include @@ -136,7 +136,7 @@ cp15_trapper(u_int addr, u_int insn, str * Don't overwrite sp, pc, etc. */ const u_int regno = (insn >> 12) & 15; - if (regno > 12) + if (regno == 13 || regno == 15) return 1; /*
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: jmcneill
Date: Tue Sep 8 17:20:11 UTC 2020
Modified Files:
src/sys/arch/arm/arm: efi_runtime.c
Log Message:
Disable EFI runtime support for BE kernels
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/arm/efi_runtime.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/efi_runtime.c
diff -u src/sys/arch/arm/arm/efi_runtime.c:1.3 src/sys/arch/arm/arm/efi_runtime.c:1.4
--- src/sys/arch/arm/arm/efi_runtime.c:1.3 Mon Dec 16 00:03:50 2019
+++ src/sys/arch/arm/arm/efi_runtime.c Tue Sep 8 17:20:10 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: efi_runtime.c,v 1.3 2019/12/16 00:03:50 jmcneill Exp $ */
+/* $NetBSD: efi_runtime.c,v 1.4 2020/09/08 17:20:10 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -30,10 +30,11 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: efi_runtime.c,v 1.3 2019/12/16 00:03:50 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: efi_runtime.c,v 1.4 2020/09/08 17:20:10 jmcneill Exp $");
#include
#include
+#include
#include
@@ -41,12 +42,13 @@ __KERNEL_RCSID(0, "$NetBSD: efi_runtime.
static kmutex_t efi_lock;
-static struct efi_systbl *ST = NULL;
static struct efi_rt *RT = NULL;
int
arm_efirt_init(paddr_t efi_system_table)
{
+#if BYTE_ORDER == LITTLE_ENDIAN
+ struct efi_systbl *ST;
const size_t sz = PAGE_SIZE * 2;
vaddr_t va, cva;
paddr_t cpa;
@@ -74,6 +76,10 @@ arm_efirt_init(paddr_t efi_system_table)
mutex_init(_lock, MUTEX_DEFAULT, IPL_HIGH);
return 0;
+#else
+ /* EFI runtime not supported in big endian mode */
+ return ENXIO;
+#endif
}
int
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Fri Aug 28 13:00:29 UTC 2020
Modified Files:
src/sys/arch/arm/arm: armv6_start.S
Log Message:
Change to the KVA stack address straight after the MMU is turned on
To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/arm/arm/armv6_start.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/armv6_start.S
diff -u src/sys/arch/arm/arm/armv6_start.S:1.24 src/sys/arch/arm/arm/armv6_start.S:1.25
--- src/sys/arch/arm/arm/armv6_start.S:1.24 Fri Aug 28 12:56:19 2020
+++ src/sys/arch/arm/arm/armv6_start.S Fri Aug 28 13:00:29 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: armv6_start.S,v 1.24 2020/08/28 12:56:19 skrll Exp $ */
+/* $NetBSD: armv6_start.S,v 1.25 2020/08/28 13:00:29 skrll Exp $ */
/*-
* Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc.
@@ -467,6 +467,9 @@ generic_startv7:
b armv7_mmuinit
generic_vstartv7:
+ // Stack to KVA address
+ add sp, sp, R_VTOPDIFF
+
VPRINTF("virtual\n\r")
#if defined(KASAN)
@@ -521,6 +524,9 @@ generic_startv6:
b armv6_mmuinit
generic_vstartv6:
+ // Stack to KVA address
+ add sp, sp, R_VTOPDIFF
+
VPRINTF("virtual\n\r")
#if defined(KASAN)
@@ -882,7 +888,7 @@ ASEND(cpu_mpstart)
* Now running with real kernel VA via bootstrap tables
*/
armv7_mpcontinuation:
- // Adjust stack back to KVA address
+ // Stack to KVA address
add sp, sp, R_VTOPDIFF
VPRINTF("virtual\n\r")
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Fri Aug 28 12:56:19 UTC 2020
Modified Files:
src/sys/arch/arm/arm: armv6_start.S
Log Message:
#ifdef -> #if defined
To generate a diff of this commit:
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/arm/arm/armv6_start.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/armv6_start.S
diff -u src/sys/arch/arm/arm/armv6_start.S:1.23 src/sys/arch/arm/arm/armv6_start.S:1.24
--- src/sys/arch/arm/arm/armv6_start.S:1.23 Fri Aug 28 11:15:08 2020
+++ src/sys/arch/arm/arm/armv6_start.S Fri Aug 28 12:56:19 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: armv6_start.S,v 1.23 2020/08/28 11:15:08 skrll Exp $ */
+/* $NetBSD: armv6_start.S,v 1.24 2020/08/28 12:56:19 skrll Exp $ */
/*-
* Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc.
@@ -99,7 +99,7 @@
ENTRY_NP(generic_start)
// ARMv7 only?!?
-#ifdef __ARMEB__
+#if defined(__ARMEB__)
setend be /* force big endian */
#endif
@@ -143,7 +143,7 @@ ENTRY_NP(generic_start)
VPRINTX(r6)
#endif
-#ifdef VERBOSE_INIT_ARM
+#if defined(VERBOSE_INIT_ARM)
VPRINTF("\n\rmidr : ")
mrc p15, 0, r0, c0, c0, 0 // MIDR
VPRINTX(r0)
@@ -469,7 +469,7 @@ generic_startv7:
generic_vstartv7:
VPRINTF("virtual\n\r")
-#ifdef KASAN
+#if defined(KASAN)
ldr r0, =start_stacks_bottom
bl _C_LABEL(kasan_early_init)
@@ -503,7 +503,7 @@ generic_startv6:
bl armv6_init
bl generic_savevars
-#ifdef ARM_MMU_EXTENDED
+#if defined(ARM_MMU_EXTENDED)
mov R_DEVATTR, #L1_S_V6_XN
#else
mov R_DEVATTR, #0
@@ -523,7 +523,7 @@ generic_startv6:
generic_vstartv6:
VPRINTF("virtual\n\r")
-#ifdef KASAN
+#if defined(KASAN)
ldr r0, =start_stacks_bottom
bl _C_LABEL(kasan_early_init)
@@ -547,13 +547,13 @@ generic_vstartv6:
//
// SCTLR register initialization values
//
-#ifdef __ARMEL__
+#if defined(__ARMEL__)
#define CPU_CONTROL_EX_BEND_SET 0
#else
#define CPU_CONTROL_EX_BEND_SET CPU_CONTROL_EX_BEND
#endif
-#ifdef ARM32_DISABLE_ALIGNMENT_FAULTS
+#if defined(ARM32_DISABLE_ALIGNMENT_FAULTS)
#define CPU_CONTROL_AFLT_ENABLE_CLR CPU_CONTROL_AFLT_ENABLE
#define CPU_CONTROL_AFLT_ENABLE_SET 0
#else
@@ -561,7 +561,7 @@ generic_vstartv6:
#define CPU_CONTROL_AFLT_ENABLE_SET CPU_CONTROL_AFLT_ENABLE
#endif
-#ifdef ARM_MMU_EXTENDED
+#if defined(ARM_MMU_EXTENDED)
#define CPU_CONTROL_XP_ENABLE_CLR 0
#define CPU_CONTROL_XP_ENABLE_SET CPU_CONTROL_XP_ENABLE
#else
@@ -678,7 +678,7 @@ armv7_init:
dsb
isb
-#ifdef VERBOSE_INIT_ARM
+#if defined(VERBOSE_INIT_ARM)
XPUTC(#'B')
VPRINTF(" sctlr:")
@@ -810,7 +810,7 @@ ENTRY_NP(cpu_mpstart)
3: wfi
b 3b
#else
-#ifdef __ARMEB__
+#if defined(__ARMEB__)
setend be// switch to BE now
#endif
@@ -848,7 +848,7 @@ ENTRY_NP(cpu_mpstart)
lsl r5, #INIT_ARM_STACK_SHIFT
sub sp, sp, r5
-#ifdef VERBOSE_INIT_ARM
+#if defined(VERBOSE_INIT_ARM)
VPRINTF("\n\rmidr : ")
mrc p15, 0, r0, c0, c0, 0 // MIDR
VPRINTX(r0)
@@ -930,7 +930,7 @@ armv7_mpcontinuation:
ldr r6, [r5, #CI_IDLELWP] // get the idlelwp
ldr r7, [r6, #L_PCB] // now get its pcb
ldr sp, [r7, #PCB_KSP] // finally, we can load our SP
-#ifdef TPIDRPRW_IS_CURCPU
+#if defined(TPIDRPRW_IS_CURCPU)
mcr p15, 0, r5, c13, c0, 4 // squirrel away curcpu()
#elif defined(TPIDRPRW_IS_CURLWP)
mcr p15, 0, r6, c13, c0, 4 // squirrel away curlwp()
@@ -989,7 +989,7 @@ ENTRY_NP(armv6_init)
mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffers. */
-#ifdef VERBOSE_INIT_ARM
+#if defined(VERBOSE_INIT_ARM)
XPUTC(#'B')
VPRINTF(" sctlr:")
@@ -1044,7 +1044,7 @@ armv6_mmuinit:
* Enable the MMU, etc.
*/
-#ifdef VERBOSE_INIT_ARM
+#if defined(VERBOSE_INIT_ARM)
VPRINTF(" sctlr:")
mrc p15, 0, r0, c1, c0, 0
VPRINTX(r0)
@@ -1087,7 +1087,7 @@ armv6_mmuinit:
/* bits to set in the Control Register */
Lcontrol_set:
-#ifdef ARM_MMU_EXTENDED
+#if defined(ARM_MMU_EXTENDED)
#define CPU_CONTROL_EXTRA CPU_CONTROL_XP_ENABLE
#else
#define CPU_CONTROL_EXTRA CPU_CONTROL_SYST_ENABLE
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Fri Aug 28 11:15:08 UTC 2020
Modified Files:
src/sys/arch/arm/arm: armv6_start.S
Log Message:
arm_cpu_topology_set only takes two arguments
To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/arm/arm/armv6_start.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/armv6_start.S
diff -u src/sys/arch/arm/arm/armv6_start.S:1.22 src/sys/arch/arm/arm/armv6_start.S:1.23
--- src/sys/arch/arm/arm/armv6_start.S:1.22 Tue Aug 25 15:03:48 2020
+++ src/sys/arch/arm/arm/armv6_start.S Fri Aug 28 11:15:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: armv6_start.S,v 1.22 2020/08/25 15:03:48 skrll Exp $ */
+/* $NetBSD: armv6_start.S,v 1.23 2020/08/28 11:15:08 skrll Exp $ */
/*-
* Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc.
@@ -485,7 +485,6 @@ generic_vstartv7:
mrc p15, 0, r1, c0, c0, 5 // MPIDR get
str r1, [r0, #CI_MPIDR]
- mov r2, #0
bl arm_cpu_topology_set
VPRINTF("go\n\r")
@@ -905,7 +904,6 @@ armv7_mpcontinuation:
mrc p15, 0, r1, c0, c0, 5 // MPIDR get
str r1, [r0, #CI_MPIDR]
- mov r2, #0
bl arm_cpu_topology_set
/*
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Tue Aug 25 15:03:48 UTC 2020
Modified Files:
src/sys/arch/arm/arm: armv6_start.S
Log Message:
More debug
To generate a diff of this commit:
cvs rdiff -u -r1.21 -r1.22 src/sys/arch/arm/arm/armv6_start.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/armv6_start.S
diff -u src/sys/arch/arm/arm/armv6_start.S:1.21 src/sys/arch/arm/arm/armv6_start.S:1.22
--- src/sys/arch/arm/arm/armv6_start.S:1.21 Sun Jul 19 11:47:47 2020
+++ src/sys/arch/arm/arm/armv6_start.S Tue Aug 25 15:03:48 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: armv6_start.S,v 1.21 2020/07/19 11:47:47 skrll Exp $ */
+/* $NetBSD: armv6_start.S,v 1.22 2020/08/25 15:03:48 skrll Exp $ */
/*-
* Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc.
@@ -467,9 +467,13 @@ generic_startv7:
b armv7_mmuinit
generic_vstartv7:
+ VPRINTF("virtual\n\r")
+
#ifdef KASAN
ldr r0, =start_stacks_bottom
bl _C_LABEL(kasan_early_init)
+
+ VPRINTF("kasan\n\r")
#endif
/* r0 = _info_store[0] */
@@ -518,9 +522,13 @@ generic_startv6:
b armv6_mmuinit
generic_vstartv6:
+ VPRINTF("virtual\n\r")
+
#ifdef KASAN
ldr r0, =start_stacks_bottom
bl _C_LABEL(kasan_early_init)
+
+ VPRINTF("kasan\n\r")
#endif
VPRINTF("go\n\r")
@@ -878,7 +886,7 @@ armv7_mpcontinuation:
// Adjust stack back to KVA address
add sp, sp, R_VTOPDIFF
- VPRINTF("go\n\r")
+ VPRINTF("virtual\n\r")
// index into cpu_mpidr[] or cpu_number if not found
mov r0, R_INDEX
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Thu Jul 9 11:40:54 UTC 2020
Modified Files:
src/sys/arch/arm/arm: armv6_start.S
Log Message:
Remove some newlines
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/arm/arm/armv6_start.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/armv6_start.S
diff -u src/sys/arch/arm/arm/armv6_start.S:1.18 src/sys/arch/arm/arm/armv6_start.S:1.19
--- src/sys/arch/arm/arm/armv6_start.S:1.18 Wed Jul 8 10:17:59 2020
+++ src/sys/arch/arm/arm/armv6_start.S Thu Jul 9 11:40:54 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: armv6_start.S,v 1.18 2020/07/08 10:17:59 skrll Exp $ */
+/* $NetBSD: armv6_start.S,v 1.19 2020/07/09 11:40:54 skrll Exp $ */
/*-
* Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc.
@@ -525,8 +525,6 @@ generic_vstartv6:
#endif
-
-
#if defined(_ARM_ARCH_7)
//
@@ -554,7 +552,6 @@ generic_vstartv6:
#define CPU_CONTROL_XP_ENABLE_SET 0
#endif
-
// bits to set in the Control Register
//
#define CPU_CONTROL_SET ( \
@@ -572,7 +569,6 @@ generic_vstartv6:
CPU_CONTROL_XP_ENABLE_CLR | \
0)
-
/*
* Perform the initialization of the an ARMv7 core required by NetBSD.
*
@@ -646,7 +642,6 @@ armv7_init:
CPU_CONTROL_UNAL_ENABLE | \
0)
-
mrc p15, 0, r0, c1, c0, 0
movw r1, #:lower16:ARMV7_SCTLR_CLEAR
movt r1, #:upper16:ARMV7_SCTLR_CLEAR
@@ -740,7 +735,6 @@ armv7_mmuinit:
mov r1, #DOMAIN_DEFAULT
mcr p15, 0, r1, c3, c0, 0 // DACR write
-
#if 0
/*
@@ -867,7 +861,6 @@ ENTRY_NP(cpu_mpstart)
b armv7_mmuinit
ASEND(cpu_mpstart)
-
/*
* Now running with real kernel VA via bootstrap tables
*/
@@ -1076,7 +1069,6 @@ armv6_mmuinit:
.ltorg
-
/* bits to set in the Control Register */
Lcontrol_set:
#ifdef ARM_MMU_EXTENDED
@@ -1109,7 +1101,6 @@ Lcontrol_wax:
(1 << 10)
#endif
-
ENTRY_NP(generic_vprint)
push {r4, lr}
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: skrll Date: Fri Jul 3 06:15:27 UTC 2020 Modified Files: src/sys/arch/arm/arm: armv6_start.S Log Message: Wrap a comment To generate a diff of this commit: cvs rdiff -u -r1.16 -r1.17 src/sys/arch/arm/arm/armv6_start.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/armv6_start.S diff -u src/sys/arch/arm/arm/armv6_start.S:1.16 src/sys/arch/arm/arm/armv6_start.S:1.17 --- src/sys/arch/arm/arm/armv6_start.S:1.16 Fri Mar 20 19:48:03 2020 +++ src/sys/arch/arm/arm/armv6_start.S Fri Jul 3 06:15:27 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: armv6_start.S,v 1.16 2020/03/20 19:48:03 skrll Exp $ */ +/* $NetBSD: armv6_start.S,v 1.17 2020/07/03 06:15:27 skrll Exp $ */ /*- * Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc. @@ -224,7 +224,10 @@ generic_savevars: .ltorg - /* Allocate some memory after the kernel image for stacks and bootstrap L1PT */ + /* + * Allocate some memory after the kernel image for stacks and + * bootstrap L1PT + */ .section "_init_memory", "aw", %nobits .p2align INIT_ARM_STACK_SHIFT start_stacks_bottom:
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Sun Mar 29 08:27:41 UTC 2020
Modified Files:
src/sys/arch/arm/arm: arm_cpu_topology.c
Log Message:
Fix a c error from 1.3 that should fixes mrg's rk3399 slow vs fast CPU
problem.
My XU4 certainly reports the right relative speeds for the 5 (yes, 5) CPUs
that are avalable.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/arm/arm_cpu_topology.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/arm_cpu_topology.c
diff -u src/sys/arch/arm/arm/arm_cpu_topology.c:1.4 src/sys/arch/arm/arm/arm_cpu_topology.c:1.5
--- src/sys/arch/arm/arm/arm_cpu_topology.c:1.4 Sat Feb 15 08:16:10 2020
+++ src/sys/arch/arm/arm/arm_cpu_topology.c Sun Mar 29 08:27:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: arm_cpu_topology.c,v 1.4 2020/02/15 08:16:10 skrll Exp $ */
+/* $NetBSD: arm_cpu_topology.c,v 1.5 2020/03/29 08:27:41 skrll Exp $ */
/*
* Copyright (c) 2020 Matthew R. Green
@@ -33,7 +33,7 @@
#include "opt_multiprocessor.h"
#include
-__KERNEL_RCSID(0, "$NetBSD: arm_cpu_topology.c,v 1.4 2020/02/15 08:16:10 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: arm_cpu_topology.c,v 1.5 2020/03/29 08:27:41 skrll Exp $");
#include
#include
@@ -97,8 +97,8 @@ arm_cpu_do_topology(struct cpu_info *con
for (CPU_INFO_FOREACH(cii, ci)) {
if (ci == newci)
continue;
- cpu_topology_setspeed(newci,
- newci->ci_capacity_dmips_mhz < best_cap);
+ cpu_topology_setspeed(ci,
+ ci->ci_capacity_dmips_mhz < best_cap);
}
#endif /* MULTIPROCESSOR */
}
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: rin Date: Mon Feb 24 12:08:09 UTC 2020 Modified Files: src/sys/arch/arm/arm: fiq.c Log Message: Fix previous; we need for machines with !ARM_HAS_VBAR && !__ARM_FIQ_INDIRECT. To generate a diff of this commit: cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/arm/fiq.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/fiq.c diff -u src/sys/arch/arm/arm/fiq.c:1.9 src/sys/arch/arm/arm/fiq.c:1.10 --- src/sys/arch/arm/arm/fiq.c:1.9 Sat Feb 22 19:49:11 2020 +++ src/sys/arch/arm/arm/fiq.c Mon Feb 24 12:08:08 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: fiq.c,v 1.9 2020/02/22 19:49:11 chs Exp $ */ +/* $NetBSD: fiq.c,v 1.10 2020/02/24 12:08:08 rin Exp $ */ /* * Copyright (c) 2001, 2002 Wasabi Systems, Inc. @@ -36,7 +36,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: fiq.c,v 1.9 2020/02/22 19:49:11 chs Exp $"); +__KERNEL_RCSID(0, "$NetBSD: fiq.c,v 1.10 2020/02/24 12:08:08 rin Exp $"); #include #include @@ -44,6 +44,8 @@ __KERNEL_RCSID(0, "$NetBSD: fiq.c,v 1.9 #include #include +#include + TAILQ_HEAD(, fiqhandler) fiqhandler_stack = TAILQ_HEAD_INITIALIZER(fiqhandler_stack);
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Wed Jan 22 10:52:35 UTC 2020
Modified Files:
src/sys/arch/arm/arm: arm_machdep.c
Log Message:
Oops, the cast is required
To generate a diff of this commit:
cvs rdiff -u -r1.61 -r1.62 src/sys/arch/arm/arm/arm_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/arm_machdep.c
diff -u src/sys/arch/arm/arm/arm_machdep.c:1.61 src/sys/arch/arm/arm/arm_machdep.c:1.62
--- src/sys/arch/arm/arm/arm_machdep.c:1.61 Tue Jan 21 04:59:47 2020
+++ src/sys/arch/arm/arm/arm_machdep.c Wed Jan 22 10:52:35 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: arm_machdep.c,v 1.61 2020/01/21 04:59:47 skrll Exp $ */
+/* $NetBSD: arm_machdep.c,v 1.62 2020/01/22 10:52:35 skrll Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -80,7 +80,7 @@
#include
-__KERNEL_RCSID(0, "$NetBSD: arm_machdep.c,v 1.61 2020/01/21 04:59:47 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: arm_machdep.c,v 1.62 2020/01/22 10:52:35 skrll Exp $");
#include
#include
@@ -309,7 +309,7 @@ cpu_kpreempt_enter(uintptr_t where, int
void
cpu_kpreempt_exit(uintptr_t where)
{
- atomic_and_uint(()->ci_astpending, ~__BIT(1));
+ atomic_and_uint(()->ci_astpending, (unsigned int)~__BIT(1));
}
bool
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Tue Jan 21 04:59:47 UTC 2020
Modified Files:
src/sys/arch/arm/arm: arm_machdep.c
Log Message:
Remove unnecessary cast
To generate a diff of this commit:
cvs rdiff -u -r1.60 -r1.61 src/sys/arch/arm/arm/arm_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/arm_machdep.c
diff -u src/sys/arch/arm/arm/arm_machdep.c:1.60 src/sys/arch/arm/arm/arm_machdep.c:1.61
--- src/sys/arch/arm/arm/arm_machdep.c:1.60 Tue Jan 7 09:57:10 2020
+++ src/sys/arch/arm/arm/arm_machdep.c Tue Jan 21 04:59:47 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: arm_machdep.c,v 1.60 2020/01/07 09:57:10 skrll Exp $ */
+/* $NetBSD: arm_machdep.c,v 1.61 2020/01/21 04:59:47 skrll Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -80,7 +80,7 @@
#include
-__KERNEL_RCSID(0, "$NetBSD: arm_machdep.c,v 1.60 2020/01/07 09:57:10 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: arm_machdep.c,v 1.61 2020/01/21 04:59:47 skrll Exp $");
#include
#include
@@ -309,7 +309,7 @@ cpu_kpreempt_enter(uintptr_t where, int
void
cpu_kpreempt_exit(uintptr_t where)
{
- atomic_and_uint(()->ci_astpending, (unsigned int)~__BIT(1));
+ atomic_and_uint(()->ci_astpending, ~__BIT(1));
}
bool
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: mrg
Date: Thu Jan 16 06:34:24 UTC 2020
Modified Files:
src/sys/arch/arm/arm: arm_cpu_topology.c
Log Message:
make the topology support empty on non-SMP enabled kernels.
reduces kernel sizes and also fixes the builds.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/arm/arm_cpu_topology.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/arm_cpu_topology.c
diff -u src/sys/arch/arm/arm/arm_cpu_topology.c:1.1 src/sys/arch/arm/arm/arm_cpu_topology.c:1.2
--- src/sys/arch/arm/arm/arm_cpu_topology.c:1.1 Wed Jan 15 08:34:04 2020
+++ src/sys/arch/arm/arm/arm_cpu_topology.c Thu Jan 16 06:34:24 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: arm_cpu_topology.c,v 1.1 2020/01/15 08:34:04 mrg Exp $ */
+/* $NetBSD: arm_cpu_topology.c,v 1.2 2020/01/16 06:34:24 mrg Exp $ */
/*
* Copyright (c) 2020 Matthew R. Green
@@ -28,10 +28,12 @@
* SUCH DAMAGE.
*/
+/* CPU topology support for ARMv7 and ARMv8 systems. */
+
#include "opt_multiprocessor.h"
#include
-__KERNEL_RCSID(0, "$NetBSD: arm_cpu_topology.c,v 1.1 2020/01/15 08:34:04 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: arm_cpu_topology.c,v 1.2 2020/01/16 06:34:24 mrg Exp $");
#include
#include
@@ -40,12 +42,14 @@ __KERNEL_RCSID(0, "$NetBSD: arm_cpu_topo
#include
#include
+#include
#include
void
arm_cpu_topology_set(struct cpu_info * const ci, uint64_t mpidr, bool slow)
{
+#ifdef MULTIPROCESSOR
uint pkgid, coreid, smtid, numaid = 0;
if (mpidr & MPIDR_MT) {
@@ -58,6 +62,7 @@ arm_cpu_topology_set(struct cpu_info * c
smtid = 0;
}
cpu_topology_set(ci, pkgid, coreid, smtid, numaid, slow);
+#endif /* MULTIPROCESSOR */
}
void
@@ -66,7 +71,6 @@ arm_cpu_do_topology(struct cpu_info *con
#ifdef MULTIPROCESSOR
struct cpu_info *ci;
CPU_INFO_ITERATOR cii;
-#endif /* MULTIPROCESSOR */
prop_dictionary_t dict;
uint32_t capacity_dmips_mhz = 0;
static uint32_t best_cap = 0;
@@ -87,7 +91,6 @@ arm_cpu_do_topology(struct cpu_info *con
arm_cpu_topology_set(newci, arm_cpu_mpidr(newci),
newci->ci_capacity_dmips_mhz < best_cap);
-#ifdef MULTIPROCESSOR
/*
* Using saved largest capacity, refresh previous topology info.
* It's supposed to be OK to re-set topology.
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: skrll Date: Tue Jan 7 09:55:30 UTC 2020 Modified Files: src/sys/arch/arm/arm: arm_machdep.c Log Message: Give __HAVE_PIC_FAST_SOFTINTS a chance of compiling To generate a diff of this commit: cvs rdiff -u -r1.58 -r1.59 src/sys/arch/arm/arm/arm_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/arm_machdep.c diff -u src/sys/arch/arm/arm/arm_machdep.c:1.58 src/sys/arch/arm/arm/arm_machdep.c:1.59 --- src/sys/arch/arm/arm/arm_machdep.c:1.58 Tue Dec 3 15:20:59 2019 +++ src/sys/arch/arm/arm/arm_machdep.c Tue Jan 7 09:55:30 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: arm_machdep.c,v 1.58 2019/12/03 15:20:59 riastradh Exp $ */ +/* $NetBSD: arm_machdep.c,v 1.59 2020/01/07 09:55:30 skrll Exp $ */ /* * Copyright (c) 2001 Wasabi Systems, Inc. @@ -80,7 +80,7 @@ #include -__KERNEL_RCSID(0, "$NetBSD: arm_machdep.c,v 1.58 2019/12/03 15:20:59 riastradh Exp $"); +__KERNEL_RCSID(0, "$NetBSD: arm_machdep.c,v 1.59 2020/01/07 09:55:30 skrll Exp $"); #include #include @@ -273,7 +273,7 @@ cpu_intr_p(void) __insn_barrier(); idepth = l->l_cpu->ci_intr_depth; #ifdef __HAVE_PIC_FAST_SOFTINTS - cpl = ci->ci_cpl; + cpl = l->l_cpu->ci_cpl; #endif __insn_barrier(); } while (__predict_false(ncsw != l->l_ncsw));
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: skrll Date: Sun Dec 8 10:12:19 UTC 2019 Modified Files: src/sys/arch/arm/arm: lock_cas.S Log Message: Typo in comment To generate a diff of this commit: cvs rdiff -u -r1.13 -r1.14 src/sys/arch/arm/arm/lock_cas.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/lock_cas.S diff -u src/sys/arch/arm/arm/lock_cas.S:1.13 src/sys/arch/arm/arm/lock_cas.S:1.14 --- src/sys/arch/arm/arm/lock_cas.S:1.13 Sat Apr 6 03:06:24 2019 +++ src/sys/arch/arm/arm/lock_cas.S Sun Dec 8 10:12:19 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: lock_cas.S,v 1.13 2019/04/06 03:06:24 thorpej Exp $ */ +/* $NetBSD: lock_cas.S,v 1.14 2019/12/08 10:12:19 skrll Exp $ */ /*- * Copyright (c) 2007 The NetBSD Foundation, Inc. @@ -127,7 +127,7 @@ ENTRY(_ucas_32_mp) bne 1b 2: str r5, [r3] - mov r0, #0 /* return value in case if miscompare */ + mov r0, #0 /* return value in case of miscompare */ .Lucasfault: movs r3, #0 str r3, [r4, #PCB_ONFAULT]
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: skrll Date: Mon Apr 8 07:35:32 UTC 2019 Modified Files: src/sys/arch/arm/arm: armv6_start.S Log Message: Fix a comment. To generate a diff of this commit: cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/arm/armv6_start.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/armv6_start.S diff -u src/sys/arch/arm/arm/armv6_start.S:1.11 src/sys/arch/arm/arm/armv6_start.S:1.12 --- src/sys/arch/arm/arm/armv6_start.S:1.11 Thu Apr 4 14:24:20 2019 +++ src/sys/arch/arm/arm/armv6_start.S Mon Apr 8 07:35:32 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: armv6_start.S,v 1.11 2019/04/04 14:24:20 skrll Exp $ */ +/* $NetBSD: armv6_start.S,v 1.12 2019/04/08 07:35:32 skrll Exp $ */ /*- * Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc. @@ -854,7 +854,10 @@ armv7_mpcontinuation: mov r0, R_INDEX // index into cpu_mpidr[] or cpu_number if not found bl cpu_init_secondary_processor - /* Wait for cpu_boot_secondary_processors the when cpu_info is allocated, etc */ + /* + * Wait for cpu_boot_secondary_processors when cpu_info has + * been allocated, etc + */ movw r6, #:lower16:arm_cpu_mbox movt r6, #:upper16:arm_cpu_mbox
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: thorpej Date: Sun Apr 7 14:14:03 UTC 2019 Modified Files: src/sys/arch/arm/arm: fusu.S Log Message: ...and now I really have the list of arch versions that require the armv2 style of ufetch_16/ustore_16. And since it's so many, just stop naming it for the arch version, and name it for the instruction capability. To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/arm/fusu.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/fusu.S diff -u src/sys/arch/arm/arm/fusu.S:1.6 src/sys/arch/arm/arm/fusu.S:1.7 --- src/sys/arch/arm/arm/fusu.S:1.6 Sun Apr 7 04:11:56 2019 +++ src/sys/arch/arm/arm/fusu.S Sun Apr 7 14:14:03 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: fusu.S,v 1.6 2019/04/07 04:11:56 thorpej Exp $ */ +/* $NetBSD: fusu.S,v 1.7 2019/04/07 14:14:03 thorpej Exp $ */ /*- * Copyright (c) 2019 The NetBSD Foundation, Inc. @@ -70,6 +70,10 @@ #include +#if (ARM_ARCH_2 + ARM_ARCH_3 + ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6) > 0 +#define NO_LDRHT_STRHT +#endif + #define RETURN_SUCCESS \ mov r0, #0x ; \ mov pc, lr @@ -99,9 +103,9 @@ ENTRY(_ufetch_8) RETURN_SUCCESS END(_ufetch_8) -#if (ARM_ARCH_2 + ARM_ARCH_3 + ARM_ARCH_4 + ARM_ARCH_5) > 0 -/* LINTSTUB: int _ufetch_16_armv2(const uint16_t *uaddr, uint16_t *valp); */ -ENTRY(_ufetch_16_armv2) +#ifdef NO_LDRHT_STRHT +/* LINTSTUB: int _ufetch_16_no_ldrht(const uint16_t *uaddr, uint16_t *valp); */ +ENTRY(_ufetch_16_no_ldrht) UFETCHSTORE_PROLOGUE ldrbt r3, [r0], #1 @@ -112,15 +116,15 @@ ENTRY(_ufetch_16_armv2) UFETCHSTORE_EPILOGUE RETURN_SUCCESS -END(_ufetch_16_armv2) +END(_ufetch_16_no_ldrht) /* LINTSTUB: int _ufetch_16(const uint16_t *uaddr, uint16_t *valp); */ -STRONG_ALIAS(_ufetch_16,_ufetch_16_armv2) +STRONG_ALIAS(_ufetch_16,_ufetch_16_no_ldrht) #else /* XXX */ -/* LINTSTUB: int _ufetch_16_armv6(const uint16_t *uaddr, uint16_t *valp); */ -ENTRY(_ufetch_16_armv6) +/* LINTSTUB: int _ufetch_16_ldrht(const uint16_t *uaddr, uint16_t *valp); */ +ENTRY(_ufetch_16_ldrht) UFETCHSTORE_PROLOGUE ldrht r3, [r0] @@ -128,11 +132,11 @@ ENTRY(_ufetch_16_armv6) UFETCHSTORE_EPILOGUE RETURN_SUCCESS -END(_ufetch_16_armv6) +END(_ufetch_16_ldrht) /* LINTSTUB: int _ufetch_16(const uint16_t *uaddr, uint16_t *valp); */ -STRONG_ALIAS(_ufetch_16,_ufetch_16_armv6) -#endif /* (ARM_ARCH_2 + ARM_ARCH_3 + ARM_ARCH_4 + ARM_ARCH_5) > 0 */ +STRONG_ALIAS(_ufetch_16,_ufetch_16_ldrht) +#endif /* NO_LDRHT_STRHT */ /* LINTSTUB: int _ufetch_32(const uint32_t *uaddr, uint32_t *valp); */ ENTRY(_ufetch_32) @@ -155,9 +159,9 @@ ENTRY(_ustore_8) RETURN_SUCCESS END(_ustore_8) -#if (ARM_ARCH_2 + ARM_ARCH_3 + ARM_ARCH_4 + ARM_ARCH_5) > 0 -/* LINTSTUB: int _ustore_16_armv2(uint16_t *uaddr, uint16_t val); */ -ENTRY(_ustore_16_armv2) +#ifdef NO_LDRHT_STRHT +/* LINTSTUB: int _ustore_16_no_strht(uint16_t *uaddr, uint16_t val); */ +ENTRY(_ustore_16_no_strht) UFETCHSTORE_PROLOGUE #ifdef __ARMEB__ @@ -171,26 +175,26 @@ ENTRY(_ustore_16_armv2) UFETCHSTORE_EPILOGUE RETURN_SUCCESS -END(_ustore_16_armv2) +END(_ustore_16_no_strht) /* LINTSTUB: int _ustore_16(uint16_t *uaddr, uint16_t val); */ -STRONG_ALIAS(_ustore_16,_ustore_16_armv2) +STRONG_ALIAS(_ustore_16,_ustore_16_no_strht) #else /* XXX */ -/* LINTSTUB: int _ustore_16_armv4(uint16_t *uaddr, uint16_t val); */ -ENTRY(_ustore_16_armv6) +/* LINTSTUB: int _ustore_16_strht(uint16_t *uaddr, uint16_t val); */ +ENTRY(_ustore_16_strht) UFETCHSTORE_PROLOGUE strht r1, [r0] UFETCHSTORE_EPILOGUE RETURN_SUCCESS -END(_ustore_16_armv6) +END(_ustore_16_strht) /* LINTSTUB: int _ustore_16(uint16_t *uaddr, uint16_t val); */ -STRONG_ALIAS(_ustore_16,_ustore_16_armv6) -#endif /* (ARM_ARCH_2 + ARM_ARCH_3 + ARM_ARCH_4 + ARM_ARCH_5) > 0 */ +STRONG_ALIAS(_ustore_16,_ustore_16_strht) +#endif /* NO_LDRHT_STRHT */ /* LINTSTUB: int _ustore_32(uint32_t *uaddr, uint32_t val); */ ENTRY(_ustore_32)
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: thorpej Date: Sun Apr 7 04:11:56 UTC 2019 Modified Files: src/sys/arch/arm/arm: fusu.S Log Message: Fix ARM_ARCH_* brain fart. To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/arm/fusu.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/fusu.S diff -u src/sys/arch/arm/arm/fusu.S:1.5 src/sys/arch/arm/arm/fusu.S:1.6 --- src/sys/arch/arm/arm/fusu.S:1.5 Sat Apr 6 03:06:24 2019 +++ src/sys/arch/arm/arm/fusu.S Sun Apr 7 04:11:56 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: fusu.S,v 1.5 2019/04/06 03:06:24 thorpej Exp $ */ +/* $NetBSD: fusu.S,v 1.6 2019/04/07 04:11:56 thorpej Exp $ */ /*- * Copyright (c) 2019 The NetBSD Foundation, Inc. @@ -99,7 +99,7 @@ ENTRY(_ufetch_8) RETURN_SUCCESS END(_ufetch_8) -#if (ARM_ARCH_2 + ARM_ARCH_3) > 0 +#if (ARM_ARCH_2 + ARM_ARCH_3 + ARM_ARCH_4 + ARM_ARCH_5) > 0 /* LINTSTUB: int _ufetch_16_armv2(const uint16_t *uaddr, uint16_t *valp); */ ENTRY(_ufetch_16_armv2) UFETCHSTORE_PROLOGUE @@ -114,10 +114,13 @@ ENTRY(_ufetch_16_armv2) RETURN_SUCCESS END(_ufetch_16_armv2) +/* LINTSTUB: int _ufetch_16(const uint16_t *uaddr, uint16_t *valp); */ +STRONG_ALIAS(_ufetch_16,_ufetch_16_armv2) + #else /* XXX */ -/* LINTSTUB: int _ufetch_16_armv4(const uint16_t *uaddr, uint16_t *valp); */ -ENTRY(_ufetch_16_armv4) +/* LINTSTUB: int _ufetch_16_armv6(const uint16_t *uaddr, uint16_t *valp); */ +ENTRY(_ufetch_16_armv6) UFETCHSTORE_PROLOGUE ldrht r3, [r0] @@ -125,15 +128,11 @@ ENTRY(_ufetch_16_armv4) UFETCHSTORE_EPILOGUE RETURN_SUCCESS -END(_ufetch_16_armv4) -#endif /* (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0 */ +END(_ufetch_16_armv6) /* LINTSTUB: int _ufetch_16(const uint16_t *uaddr, uint16_t *valp); */ -#if (ARM_ARCH_2 + ARM_ARCH_3) > 0 -STRONG_ALIAS(_ufetch_16,_ufetch_16_armv2) -#else -STRONG_ALIAS(_ufetch_16,_ufetch_16_armv4) -#endif /* #if (ARM_ARCH_2 + ARM_ARCH_3) > 0 */ +STRONG_ALIAS(_ufetch_16,_ufetch_16_armv6) +#endif /* (ARM_ARCH_2 + ARM_ARCH_3 + ARM_ARCH_4 + ARM_ARCH_5) > 0 */ /* LINTSTUB: int _ufetch_32(const uint32_t *uaddr, uint32_t *valp); */ ENTRY(_ufetch_32) @@ -156,7 +155,7 @@ ENTRY(_ustore_8) RETURN_SUCCESS END(_ustore_8) -#if (ARM_ARCH_2 + ARM_ARCH_3) > 0 +#if (ARM_ARCH_2 + ARM_ARCH_3 + ARM_ARCH_4 + ARM_ARCH_5) > 0 /* LINTSTUB: int _ustore_16_armv2(uint16_t *uaddr, uint16_t val); */ ENTRY(_ustore_16_armv2) UFETCHSTORE_PROLOGUE @@ -174,26 +173,24 @@ ENTRY(_ustore_16_armv2) RETURN_SUCCESS END(_ustore_16_armv2) +/* LINTSTUB: int _ustore_16(uint16_t *uaddr, uint16_t val); */ +STRONG_ALIAS(_ustore_16,_ustore_16_armv2) + #else /* XXX */ /* LINTSTUB: int _ustore_16_armv4(uint16_t *uaddr, uint16_t val); */ -ENTRY(_ustore_16_armv4) +ENTRY(_ustore_16_armv6) UFETCHSTORE_PROLOGUE strht r1, [r0] UFETCHSTORE_EPILOGUE RETURN_SUCCESS -END(_ustore_16_armv4) -#endif /* (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0 */ +END(_ustore_16_armv6) /* LINTSTUB: int _ustore_16(uint16_t *uaddr, uint16_t val); */ -/* XXXJRT Run-time upgrade to armv4 version would be nice. */ -#if (ARM_ARCH_2 + ARM_ARCH_3) > 0 -STRONG_ALIAS(_ustore_16,_ustore_16_armv2) -#else -STRONG_ALIAS(_ustore_16,_ustore_16_armv4) -#endif /* #if (ARM_ARCH_2 + ARM_ARCH_3) > 0 */ +STRONG_ALIAS(_ustore_16,_ustore_16_armv6) +#endif /* (ARM_ARCH_2 + ARM_ARCH_3 + ARM_ARCH_4 + ARM_ARCH_5) > 0 */ /* LINTSTUB: int _ustore_32(uint32_t *uaddr, uint32_t val); */ ENTRY(_ustore_32)
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Thu Apr 4 14:24:20 UTC 2019
Modified Files:
src/sys/arch/arm/arm: armv6_start.S
Log Message:
Restructure so that storing of uboot args (including FDT address) and
virtual to physical offset is done after armv[67]_init where we ensure
MMU and caches are off, and cache is invalidated.
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/arm/armv6_start.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/armv6_start.S
diff -u src/sys/arch/arm/arm/armv6_start.S:1.10 src/sys/arch/arm/arm/armv6_start.S:1.11
--- src/sys/arch/arm/arm/armv6_start.S:1.10 Wed Apr 3 17:55:27 2019
+++ src/sys/arch/arm/arm/armv6_start.S Thu Apr 4 14:24:20 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: armv6_start.S,v 1.10 2019/04/03 17:55:27 skrll Exp $ */
+/* $NetBSD: armv6_start.S,v 1.11 2019/04/04 14:24:20 skrll Exp $ */
/*-
* Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc.
@@ -91,6 +91,7 @@
R_TMP2 .req r9
R_VTOPDIFF .req r10
R_FDTADDR .req r11
+ R_INDEX .req r11
.text
@@ -127,33 +128,15 @@ ENTRY_NP(generic_start)
VPRINTF("\n\rsp: ")
VPRINTX(sp)
- ldr R_TMP1, =kern_vtopdiff
- sub R_TMP1, R_TMP1, R_VTOPDIFF
- str R_VTOPDIFF, [R_TMP1]
-
ldr R_TMP1, =(L1_S_SIZE - 1)
ands R_TMP2, R_VTOPDIFF, R_TMP1
bne arm_bad_vtopdiff
- /*
- * store uboot arguments to uboot_args[4]
- */
- ldr R_TMP1, =uboot_args
- sub R_TMP1, R_TMP1, R_VTOPDIFF
-
- str r4, [R_TMP1, #(4*0)]
- str r5, [R_TMP1, #(4*1)]
- str r6, [R_TMP1, #(4*2)]
- str r7, [R_TMP1, #(4*3)]
-
#if defined(FDTBASE)
/*
* ARM boot protocol has FDT address in r2 which is now in r6
*/
VPRINTF("\n\rfdt : ")
- ldr R_TMP1, =fdt_addr_r
- sub R_TMP1, R_TMP1, R_VTOPDIFF
- str r6, [R_TMP1]
mov R_FDTADDR, r6 // Save fdt_addr_r for mapping later
VPRINTX(r6)
@@ -195,6 +178,58 @@ arm_bad_vtopdiff:
1: b 1b
ASEND(generic_start)
+generic_vstart:
+ VPRINTF("go\n\r")
+
+ /*
+ * Jump to start in locore.S, which in turn will call initarm and main.
+ */
+ b start
+
+/*
+ * Save the u-boot arguments (including FDT address) and the virtual to physical
+ * offset.
+ *
+ * Uses the following callee saved registers:
+ *
+ * r8 (R_TMP1), r9 (R_TMP2)
+ */
+generic_savevars:
+ mov R_TMP1, lr
+ /*
+ * Store virtual to physical address difference
+ */
+ ldr R_TMP2, =kern_vtopdiff
+ sub R_TMP2, R_TMP2, R_VTOPDIFF
+ str R_VTOPDIFF, [R_TMP2]
+
+ /*
+ * store uboot arguments to uboot_args[4]
+ */
+ ldr R_TMP2, =uboot_args
+ sub R_TMP2, R_VTOPDIFF
+
+ VPRINTF("\n\ruboot : @")
+ VPRINTX(R_TMP2)
+ str r4, [R_TMP2, #(4*0)]
+ str r5, [R_TMP2, #(4*1)]
+ str r6, [R_TMP2, #(4*2)]
+ str r7, [R_TMP2, #(4*3)]
+
+#if defined(FDTBASE)
+ /*
+ * ARM boot protocol has FDT address in r2 which is now in r6
+ */
+ VPRINTF("\n\rfdt : ")
+ ldr R_TMP2, =fdt_addr_r
+ sub R_TMP2, R_VTOPDIFF
+ str r6, [R_TMP2]
+
+ VPRINTX(r6)
+#endif
+
+ RETr(R_TMP1)
+
.ltorg
/* Allocate some memory after the kernel image for stacks and bootstrap L1PT */
@@ -413,40 +448,34 @@ generic_startv7:
.arch_extension sec
.arch_extension virt
- VPRINTF("v7 :")
+ VPRINTF("v7: ")
bl armv7_init
+ bl generic_savevars
mov R_DEVATTR, #L1_S_V6_XN
bl arm_build_translation_table
/*
- * Turn on the MMU. Return to new enabled address space.
+ * Turn on the MMU. Return to virtual address space.
*/
movw r0, #:lower16:TEMP_L1_TABLE
movt r0, #:upper16:TEMP_L1_TABLE
sub r0, R_VTOPDIFF
// Return to virtual addess after the call to armv7_mmuinit
- movw lr, #:lower16:1f
- movt lr, #:upper16:1f
+ movw lr, #:lower16:generic_vstart
+ movt lr, #:upper16:generic_vstart
b armv7_mmuinit
-1:
-
- VPRINTF("go\n\r")
-
- /*
- * Jump to start in locore.S, which in turn will call initarm and main.
- */
- b start
/* NOTREACHED */
.ltorg
#elif defined(_ARM_ARCH_6)
generic_startv6:
- VPRINTF("v6: ")
+ VPRINTF("v6: ")
bl armv6_init
+ bl generic_savevars
#ifdef ARM_MMU_EXTENDED
mov R_DEVATTR, #L1_S_V6_XN
@@ -462,15 +491,8 @@ generic_startv6:
ldr r0, =TEMP_L1_TABLE
sub r0, R_VTOPDIFF
- ldr lr, =1f
+ ldr lr, =generic_vstart
b armv6_mmuinit
-1:
- VPRINTF("go\n\r")
-
- /*
- * Jump to start in locore.S, which in turn will call initarm and main.
- */
- b start
/* NOTREACHED */
.ltorg
@@ -530,8 +552,7 @@ generic_startv6:
*
* Uses the following callee saved registers:
*
- * Callee saved:
- * r4, r5, r6, r7
+ * r8 (R_TMP1), r9 (R_TMP2)
*/
armv7_init:
@@ -539,8 +560,8 @@ armv7_init:
.arch_extension sec
.arch_extension virt
- mov r4, lr
- mov r5, sp
+ mov R_TMP1, lr
+ mov R_TMP2, sp
/*
* Leave HYP mode and move into supervisor mode with IRQs/FIQs
@@ -577,7 +598,7 @@ armv7_init:
mov r0, #0
msr spsr_sxc, r0 // set SPSR[23:8] to known value
- mov sp, r5
+ mov sp, R_TMP2
XPUTC('A')
@@ -606,11 +627,11 @@ armv7_init:
movw r2,
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Wed Apr 3 17:55:27 UTC 2019
Modified Files:
src/sys/arch/arm/arm: armv6_start.S
Log Message:
Debug output alignment
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/arm/armv6_start.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/armv6_start.S
diff -u src/sys/arch/arm/arm/armv6_start.S:1.9 src/sys/arch/arm/arm/armv6_start.S:1.10
--- src/sys/arch/arm/arm/armv6_start.S:1.9 Tue Apr 2 20:00:36 2019
+++ src/sys/arch/arm/arm/armv6_start.S Wed Apr 3 17:55:27 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: armv6_start.S,v 1.9 2019/04/02 20:00:36 jmcneill Exp $ */
+/* $NetBSD: armv6_start.S,v 1.10 2019/04/03 17:55:27 skrll Exp $ */
/*-
* Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc.
@@ -118,13 +118,13 @@ ENTRY_NP(generic_start)
// We can now call functions
- VPRINTF("\n\rpc :")
+ VPRINTF("\n\rpc: ")
VPRINTX(pc)
- VPRINTF("\n\roff :")
+ VPRINTF("\n\roff : ")
VPRINTX(R_VTOPDIFF)
- VPRINTF("\n\rsp :")
+ VPRINTF("\n\rsp: ")
VPRINTX(sp)
ldr R_TMP1, =kern_vtopdiff
@@ -150,7 +150,7 @@ ENTRY_NP(generic_start)
/*
* ARM boot protocol has FDT address in r2 which is now in r6
*/
- VPRINTF("\n\rfdt :")
+ VPRINTF("\n\rfdt : ")
ldr R_TMP1, =fdt_addr_r
sub R_TMP1, R_TMP1, R_VTOPDIFF
str r6, [R_TMP1]
@@ -160,22 +160,22 @@ ENTRY_NP(generic_start)
#endif
#ifdef VERBOSE_INIT_ARM
- VPRINTF("\n\rmidr :")
+ VPRINTF("\n\rmidr : ")
mrc p15, 0, r0, c0, c0, 0 // MIDR
VPRINTX(r0)
VPRINTF("\n\rrevidr: ")
mrc p15, 0, r0, c0, c0, 6 // REVIDR
VPRINTX(r0)
- VPRINTF("\n\rmpidr:")
+ VPRINTF("\n\rmpidr : ")
mrc p15, 0, r0, c0, c0, 5 // MPIDR
VPRINTX(r0)
- VPRINTF("\n\rttb0 :")
+ VPRINTF("\n\rttb0 : ")
mrc p15, 0, r0, c2, c0, 0 // TTBR0 read
VPRINTX(r0)
- VPRINTF("\n\rttb1 :")
+ VPRINTF("\n\rttb1 : ")
mrc p15, 0, r0, c2, c0, 1 // TTBR1 read
VPRINTX(r0)
- VPRINTF("\n\rttcr :")
+ VPRINTF("\n\rttcr : ")
mrc p15, 0, r0, c2, c0, 2 // TTBCR read
VPRINTX(r0)
VPRINTF("\n\r")
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: jmcneill Date: Tue Apr 2 20:00:36 UTC 2019 Modified Files: src/sys/arch/arm/arm: armv6_start.S Log Message: Whitespace police To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/arm/armv6_start.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/armv6_start.S diff -u src/sys/arch/arm/arm/armv6_start.S:1.8 src/sys/arch/arm/arm/armv6_start.S:1.9 --- src/sys/arch/arm/arm/armv6_start.S:1.8 Sat Feb 9 07:20:21 2019 +++ src/sys/arch/arm/arm/armv6_start.S Tue Apr 2 20:00:36 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: armv6_start.S,v 1.8 2019/02/09 07:20:21 skrll Exp $ */ +/* $NetBSD: armv6_start.S,v 1.9 2019/04/02 20:00:36 jmcneill Exp $ */ /*- * Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc. @@ -56,7 +56,7 @@ #define START_CONSADDR CONADDR #endif -#if defined( VERBOSE_INIT_ARM) +#if defined(VERBOSE_INIT_ARM) #define XPUTC(n) mov r0, n; bl uartputc #define VPRINTF(string) bl generic_vprint; .asciz string; .align 2 #define VPRINTX(regno) mov r0, regno; bl generic_printx
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: skrll Date: Sun Mar 17 08:25:10 UTC 2019 Modified Files: src/sys/arch/arm/arm: undefined.c Log Message: Fixup a comment To generate a diff of this commit: cvs rdiff -u -r1.63 -r1.64 src/sys/arch/arm/arm/undefined.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/undefined.c diff -u src/sys/arch/arm/arm/undefined.c:1.63 src/sys/arch/arm/arm/undefined.c:1.64 --- src/sys/arch/arm/arm/undefined.c:1.63 Sat Mar 16 10:13:34 2019 +++ src/sys/arch/arm/arm/undefined.c Sun Mar 17 08:25:10 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: undefined.c,v 1.63 2019/03/16 10:13:34 skrll Exp $ */ +/* $NetBSD: undefined.c,v 1.64 2019/03/17 08:25:10 skrll Exp $ */ /* * Copyright (c) 2001 Ben Harris. @@ -55,7 +55,7 @@ #include #endif -__KERNEL_RCSID(0, "$NetBSD: undefined.c,v 1.63 2019/03/16 10:13:34 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: undefined.c,v 1.64 2019/03/17 08:25:10 skrll Exp $"); #include #include @@ -344,11 +344,11 @@ undefinedinstruction(trapframe_t *tf) } /* * Should use fuword() here .. but in the interests of - * squeezing every bit of speed we will just use - * ReadWord(). We know the instruction can be read + * squeezing every bit of speed we will just use + * read_insn(). We know the instruction can be read * as was just executed so this will never fail unless * the kernel is screwed up in which case it does - * not really matter does it ? + * not really matter does it? */ fault_instruction = read_insn(fault_pc, user); }
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Sat Mar 16 10:13:34 UTC 2019
Modified Files:
src/sys/arch/arm/arm: undefined.c
Log Message:
Style and whitespace. NFC.
To generate a diff of this commit:
cvs rdiff -u -r1.62 -r1.63 src/sys/arch/arm/arm/undefined.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/undefined.c
diff -u src/sys/arch/arm/arm/undefined.c:1.62 src/sys/arch/arm/arm/undefined.c:1.63
--- src/sys/arch/arm/arm/undefined.c:1.62 Mon May 28 21:05:00 2018
+++ src/sys/arch/arm/arm/undefined.c Sat Mar 16 10:13:34 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: undefined.c,v 1.62 2018/05/28 21:05:00 chs Exp $ */
+/* $NetBSD: undefined.c,v 1.63 2019/03/16 10:13:34 skrll Exp $ */
/*
* Copyright (c) 2001 Ben Harris.
@@ -55,7 +55,7 @@
#include
#endif
-__KERNEL_RCSID(0, "$NetBSD: undefined.c,v 1.62 2018/05/28 21:05:00 chs Exp $");
+__KERNEL_RCSID(0, "$NetBSD: undefined.c,v 1.63 2019/03/16 10:13:34 skrll Exp $");
#include
#include
@@ -399,10 +399,13 @@ undefinedinstruction(trapframe_t *tf)
fault_code = 0;
/* OK this is were we do something about the instruction. */
- LIST_FOREACH(uh, _handlers[coprocessor], uh_link)
- if (uh->uh_handler(fault_pc, fault_instruction, tf,
- fault_code) == 0)
- break;
+ LIST_FOREACH(uh, _handlers[coprocessor], uh_link) {
+ int ret = uh->uh_handler(fault_pc, fault_instruction, tf,
+ fault_code);
+
+ if (ret == 0)
+ break;
+ }
if (uh == NULL) {
/* Fault has not been handled */
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: skrll Date: Sat Feb 9 07:20:21 UTC 2019 Modified Files: src/sys/arch/arm/arm: armv6_start.S Log Message: Typo in comment To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/arm/armv6_start.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/armv6_start.S diff -u src/sys/arch/arm/arm/armv6_start.S:1.7 src/sys/arch/arm/arm/armv6_start.S:1.8 --- src/sys/arch/arm/arm/armv6_start.S:1.7 Sat Feb 9 07:19:02 2019 +++ src/sys/arch/arm/arm/armv6_start.S Sat Feb 9 07:20:21 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: armv6_start.S,v 1.7 2019/02/09 07:19:02 skrll Exp $ */ +/* $NetBSD: armv6_start.S,v 1.8 2019/02/09 07:20:21 skrll Exp $ */ /*- * Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc. @@ -634,7 +634,7 @@ armv7_init: .ltorg /* - * Transititions the CPU to using the TTB passed in r0. + * Transitions the CPU to using the TTB passed in r0. * * Uses the following callee saved registers: *
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Sat Feb 9 07:19:02 UTC 2019
Modified Files:
src/sys/arch/arm/arm: armv6_start.S
Log Message:
Print revidr of BP as well as APs
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/arm/armv6_start.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/armv6_start.S
diff -u src/sys/arch/arm/arm/armv6_start.S:1.6 src/sys/arch/arm/arm/armv6_start.S:1.7
--- src/sys/arch/arm/arm/armv6_start.S:1.6 Wed Feb 6 14:12:25 2019
+++ src/sys/arch/arm/arm/armv6_start.S Sat Feb 9 07:19:02 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: armv6_start.S,v 1.6 2019/02/06 14:12:25 skrll Exp $ */
+/* $NetBSD: armv6_start.S,v 1.7 2019/02/09 07:19:02 skrll Exp $ */
/*-
* Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc.
@@ -163,6 +163,9 @@ ENTRY_NP(generic_start)
VPRINTF("\n\rmidr :")
mrc p15, 0, r0, c0, c0, 0 // MIDR
VPRINTX(r0)
+ VPRINTF("\n\rrevidr: ")
+ mrc p15, 0, r0, c0, c0, 6 // REVIDR
+ VPRINTX(r0)
VPRINTF("\n\rmpidr:")
mrc p15, 0, r0, c0, c0, 5 // MPIDR
VPRINTX(r0)
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Wed Feb 6 14:12:25 UTC 2019
Modified Files:
src/sys/arch/arm/arm: armv6_start.S
Log Message:
Don't VPRINTF until we have stack for our CPU setup properly
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/arm/armv6_start.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/armv6_start.S
diff -u src/sys/arch/arm/arm/armv6_start.S:1.5 src/sys/arch/arm/arm/armv6_start.S:1.6
--- src/sys/arch/arm/arm/armv6_start.S:1.5 Thu Jan 3 10:26:41 2019
+++ src/sys/arch/arm/arm/armv6_start.S Wed Feb 6 14:12:25 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: armv6_start.S,v 1.5 2019/01/03 10:26:41 skrll Exp $ */
+/* $NetBSD: armv6_start.S,v 1.6 2019/02/06 14:12:25 skrll Exp $ */
/*-
* Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc.
@@ -757,18 +757,6 @@ ENTRY_NP(cpu_mpstart)
ldr R_VTOPDIFF, =cpu_mpstart
sub R_VTOPDIFF, R_VTOPDIFF, R_TMP2
- ldr R_TMP2, =start_stacks_top
- sub sp, R_TMP2, R_VTOPDIFF
-
-#ifdef VERBOSE_INIT_ARM
- VPRINTF("\n\rmidr :")
- mrc p15, 0, r0, c0, c0, 0 // MIDR
- VPRINTX(r0)
- VPRINTF("\n\rmpidr:")
- mrc p15, 0, r0, c0, c0, 5 // MPIDR
- VPRINTX(r0)
-#endif
-
mrc p15, 0, r4, c0, c0, 5 // MPIDR get
and r4, #(MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0)
@@ -789,15 +777,27 @@ ENTRY_NP(cpu_mpstart)
2:
mov R_TMP2, r0 // save cpu_index for later
- VPRINTF("index: ")
- VPRINTX(R_TMP2)
- XPUTC('\n')
- XPUTC('\r')
+ ldr R_TMP1, =start_stacks_top
+ sub sp, R_TMP1, R_VTOPDIFF
mov r5, R_TMP2
lsl r5, #INIT_ARM_STACK_SHIFT
sub sp, sp, r5
+#ifdef VERBOSE_INIT_ARM
+ VPRINTF("\n\rmidr : ")
+ mrc p15, 0, r0, c0, c0, 0 // MIDR
+ VPRINTX(r0)
+ VPRINTF("\n\rrevidr: ")
+ mrc p15, 0, r0, c0, c0, 6 // REVIDR
+ VPRINTX(r0)
+ VPRINTF("\n\rmpidr : ")
+ mrc p15, 0, r0, c0, c0, 5 // MPIDR
+ VPRINTX(r0)
+#endif
+ VPRINTF("\n\rindex : ")
+ VPRINTX(R_TMP2)
+ VPRINTF("\n\rsp: ")
VPRINTX(sp)
XPUTC('\n')
XPUTC('\r')
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: skrll Date: Wed Jan 2 16:27:04 UTC 2019 Modified Files: src/sys/arch/arm/arm: armv6_start.S Log Message: Whitespace To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/arm/armv6_start.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/armv6_start.S diff -u src/sys/arch/arm/arm/armv6_start.S:1.3 src/sys/arch/arm/arm/armv6_start.S:1.4 --- src/sys/arch/arm/arm/armv6_start.S:1.3 Wed Jan 2 16:17:15 2019 +++ src/sys/arch/arm/arm/armv6_start.S Wed Jan 2 16:27:04 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: armv6_start.S,v 1.3 2019/01/02 16:17:15 skrll Exp $ */ +/* $NetBSD: armv6_start.S,v 1.4 2019/01/02 16:27:04 skrll Exp $ */ /*- * Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc. @@ -480,6 +480,7 @@ generic_startv6: #else #define CPU_CONTROL_EX_BEND_SET CPU_CONTROL_EX_BEND #endif + #ifdef ARM32_DISABLE_ALIGNMENT_FAULTS #define CPU_CONTROL_AFLT_ENABLE_CLR CPU_CONTROL_AFLT_ENABLE #define CPU_CONTROL_AFLT_ENABLE_SET 0 @@ -487,6 +488,7 @@ generic_startv6: #define CPU_CONTROL_AFLT_ENABLE_CLR 0 #define CPU_CONTROL_AFLT_ENABLE_SET CPU_CONTROL_AFLT_ENABLE #endif + #ifdef ARM_MMU_EXTENDED #define CPU_CONTROL_XP_ENABLE_CLR 0 #define CPU_CONTROL_XP_ENABLE_SET CPU_CONTROL_XP_ENABLE @@ -760,7 +762,6 @@ ENTRY_NP(cpu_mpstart) // disables and clears caches bl armv7_init - movw r0, #:lower16:TEMP_L1_TABLE movt r0, #:upper16:TEMP_L1_TABLE sub r0, R_VTOPDIFF
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Wed Jan 2 16:17:15 UTC 2019
Modified Files:
src/sys/arch/arm/arm: armv6_start.S
Log Message:
Misc. tidyup
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/arm/armv6_start.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/armv6_start.S
diff -u src/sys/arch/arm/arm/armv6_start.S:1.2 src/sys/arch/arm/arm/armv6_start.S:1.3
--- src/sys/arch/arm/arm/armv6_start.S:1.2 Wed Jan 2 14:31:33 2019
+++ src/sys/arch/arm/arm/armv6_start.S Wed Jan 2 16:17:15 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: armv6_start.S,v 1.2 2019/01/02 14:31:33 skrll Exp $ */
+/* $NetBSD: armv6_start.S,v 1.3 2019/01/02 16:17:15 skrll Exp $ */
/*-
* Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc.
@@ -667,16 +667,15 @@ armv7_mmuinit:
#if 0
-//XXXNH FreeBSD
-288 /*
-289 * Set TEX remap registers
-290 * - All is set to uncacheable memory
-291 */
-292 ldr r0, =0xA
-293 mcr CP15_PRRR(r0)
-294 mov r0, #0
-295 mcr CP15_NMRR(r0)
+/*
+ * Set TEX remap registers
+ * - All is set to uncacheable memory
+ */
+ ldr r0, =0xA
+ mcr CP15_PRRR(r0)
+ mov r0, #0
+ mcr CP15_NMRR(r0)
#endif
XPUTC(#'I')
@@ -758,16 +757,6 @@ ENTRY_NP(cpu_mpstart)
XPUTC('\n')
XPUTC('\r')
-#if 0
- // We haven't used anything from memory yet so we can invalidate the
- // L1 cache without fear of losing valuable data. Afterwards, we can
- // flush icache without worrying about anything getting written back
- // to memory.
- bl armv7_dcache_l1inv_all // toss-dcache
- bl armv7_icache_inv_all // toss i-cache after d-cache
-
-#endif
-
// disables and clears caches
bl armv7_init
@@ -970,13 +959,6 @@ armv6_mmuinit:
nop
nop
-#if 0
- VPRINTF("MMU\n\r")
-
- VPRINTX(r4)
- VPRINTF("\n\r")
-#endif
-
mov pc, r4
.ltorg
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Wed Jan 2 14:31:33 UTC 2019
Modified Files:
src/sys/arch/arm/arm: armv6_start.S
Log Message:
Fix a ASEND
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/arm/armv6_start.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/armv6_start.S
diff -u src/sys/arch/arm/arm/armv6_start.S:1.1 src/sys/arch/arm/arm/armv6_start.S:1.2
--- src/sys/arch/arm/arm/armv6_start.S:1.1 Thu Oct 18 09:01:52 2018
+++ src/sys/arch/arm/arm/armv6_start.S Wed Jan 2 14:31:33 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: armv6_start.S,v 1.1 2018/10/18 09:01:52 skrll Exp $ */
+/* $NetBSD: armv6_start.S,v 1.2 2019/01/02 14:31:33 skrll Exp $ */
/*-
* Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc.
@@ -1034,7 +1034,7 @@ ENTRY_NP(generic_vprint)
pop {r4}
add sp, sp, #4
mov pc, lr
-ASEND(generic_prints)
+ASEND(generic_vprint)
ENTRY_NP(generic_prints)
push {r4, lr}
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Tue Oct 30 09:05:51 UTC 2018
Modified Files:
src/sys/arch/arm/arm: disassem.c
Log Message:
Allow setend be decode
To generate a diff of this commit:
cvs rdiff -u -r1.39 -r1.40 src/sys/arch/arm/arm/disassem.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/disassem.c
diff -u src/sys/arch/arm/arm/disassem.c:1.39 src/sys/arch/arm/arm/disassem.c:1.40
--- src/sys/arch/arm/arm/disassem.c:1.39 Sat Jun 3 11:51:59 2017
+++ src/sys/arch/arm/arm/disassem.c Tue Oct 30 09:05:51 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: disassem.c,v 1.39 2017/06/03 11:51:59 skrll Exp $ */
+/* $NetBSD: disassem.c,v 1.40 2018/10/30 09:05:51 skrll Exp $ */
/*
* Copyright (c) 1996 Mark Brinicombe.
@@ -49,7 +49,7 @@
#include
-__KERNEL_RCSID(0, "$NetBSD: disassem.c,v 1.39 2017/06/03 11:51:59 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: disassem.c,v 1.40 2018/10/30 09:05:51 skrll Exp $");
#include
@@ -134,7 +134,7 @@ static const struct arm32_insn arm32_i[]
* miscellaneous instructions
*/
{ 0xfff10020, 0xf100, "cps", "C!c" },
-{ 0xfff100f0, 0xf101, "setend\tle", "" },
+{ 0xfff102f0, 0xf101, "setend\tle", "" },
{ 0xfff102f0, 0xf1010200, "setend\tbe", "" },
/* pli */
/* pld */
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: jmcneill
Date: Sat Oct 13 00:07:55 UTC 2018
Modified Files:
src/sys/arch/arm/arm: psci.c psci.h
Log Message:
Add function that returns true if PSCI has been initialized
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/arm/psci.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/arm/psci.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/psci.c
diff -u src/sys/arch/arm/arm/psci.c:1.2 src/sys/arch/arm/arm/psci.c:1.3
--- src/sys/arch/arm/arm/psci.c:1.2 Fri Jun 15 15:59:20 2018
+++ src/sys/arch/arm/arm/psci.c Sat Oct 13 00:07:55 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: psci.c,v 1.2 2018/06/15 15:59:20 jakllsch Exp $ */
+/* $NetBSD: psci.c,v 1.3 2018/10/13 00:07:55 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill
@@ -29,7 +29,7 @@
#include "opt_diagnostic.h"
#include
-__KERNEL_RCSID(0, "$NetBSD: psci.c,v 1.2 2018/06/15 15:59:20 jakllsch Exp $");
+__KERNEL_RCSID(0, "$NetBSD: psci.c,v 1.3 2018/10/13 00:07:55 jmcneill Exp $");
#include
#include
@@ -106,6 +106,12 @@ psci_init(psci_fn fn)
psci_call_fn = fn;
}
+bool
+psci_available(void)
+{
+ return psci_call_fn != NULL;
+}
+
void
psci_clearfunc(void)
{
Index: src/sys/arch/arm/arm/psci.h
diff -u src/sys/arch/arm/arm/psci.h:1.1 src/sys/arch/arm/arm/psci.h:1.2
--- src/sys/arch/arm/arm/psci.h:1.1 Wed Jun 28 23:48:23 2017
+++ src/sys/arch/arm/arm/psci.h Sat Oct 13 00:07:55 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: psci.h,v 1.1 2017/06/28 23:48:23 jmcneill Exp $ */
+/* $NetBSD: psci.h,v 1.2 2018/10/13 00:07:55 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill
@@ -65,6 +65,11 @@ typedef int (*psci_fn)(register_t, regis
void psci_init(psci_fn);
/*
+ * Return true if PSCI is available (psci_init has been called).
+ */
+bool psci_available(void);
+
+/*
* PSCI call methods, implemented in psci.S
*/
int psci_call_smc(register_t, register_t, register_t, register_t);
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: skrll Date: Sat Oct 6 15:54:55 UTC 2018 Modified Files: src/sys/arch/arm/arm: cpufunc_asm_armv7.S Log Message: Add the ARM ARM cache operation name in some comments To generate a diff of this commit: cvs rdiff -u -r1.27 -r1.28 src/sys/arch/arm/arm/cpufunc_asm_armv7.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/cpufunc_asm_armv7.S diff -u src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.27 src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.28 --- src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.27 Thu Aug 24 14:19:36 2017 +++ src/sys/arch/arm/arm/cpufunc_asm_armv7.S Sat Oct 6 15:54:55 2018 @@ -347,7 +347,7 @@ ENTRY_NP(armv7_icache_inv_all) mov r2, ip @ r2 now contains set way decr /* r3 = ways/sets, r2 = way decr, r1 = set decr, r0 and ip are free */ -1: mcr p15, 0, r3, c7, c6, 2 @ invalidate line +1: mcr p15, 0, r3, c7, c6, 2 @ DCISW (data cache invalidate by set/way) movs r0, r3 @ get current way/set beq 2f @ at 0 means we are done. lsls r0, r0, #10 @ clear way bits leaving only set bits @@ -391,7 +391,7 @@ ENTRY_NP(armv7_dcache_l1inv_all) sub r2, r2, r0 @ subtract from way decr /* r3 = ways/sets/level, r2 = way decr, r1 = set decr, r0 and ip are free */ -1: mcr p15, 0, r3, c7, c6, 2 @ invalidate line +1: mcr p15, 0, r3, c7, c6, 2 @ DCISW (data cache invalidate by set/way) cmp r3, #15 @ are we done with this level (way/set == 0) bls .Ldone_l1inv @ yes, we've finished ubfx r0, r3, #4, #18 @ extract set bits @@ -445,7 +445,7 @@ ENTRY_NP(armv7_dcache_inv_all) sub r2, r2, r0 @ subtract from way decr /* r3 = ways/sets/level, r2 = way decr, r1 = set decr, r0 and ip are free */ -1: mcr p15, 0, r3, c7, c6, 2 @ invalidate line +1: mcr p15, 0, r3, c7, c6, 2 @ DCISW (data cache invalidate by set/way) cmp r3, #15 @ are we done with this level (way/set == 0) bls .Lnext_level_inv @ yes, go to next level ubfx r0, r3, #4, #18 @ extract set bits @@ -506,7 +506,7 @@ ENTRY_NP(armv7_dcache_wbinv_all) sub r2, r2, r0 @ subtract from way decr /* r3 = ways/sets/level, r2 = way decr, r1 = set decr, r0 and ip are free */ -1: mcr p15, 0, r3, c7, c14, 2 @ writeback and invalidate line +1: mcr p15, 0, r3, c7, c14, 2 @ DCCISW (data cache clean and invalidate by set/way) cmp r3, #15 @ are we done with this level (way/set == 0) bls .Lnext_level_wbinv @ yes, go to next level ubfx r0, r3, #4, #18 @ extract set bits
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Thu Aug 23 21:01:43 UTC 2018
Modified Files:
src/sys/arch/arm/arm: cpufunc.c
Log Message:
Whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.172 -r1.173 src/sys/arch/arm/arm/cpufunc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc.c
diff -u src/sys/arch/arm/arm/cpufunc.c:1.172 src/sys/arch/arm/arm/cpufunc.c:1.173
--- src/sys/arch/arm/arm/cpufunc.c:1.172 Wed Aug 15 06:00:02 2018
+++ src/sys/arch/arm/arm/cpufunc.c Thu Aug 23 21:01:43 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.172 2018/08/15 06:00:02 skrll Exp $ */
+/* $NetBSD: cpufunc.c,v 1.173 2018/08/23 21:01:43 skrll Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.172 2018/08/15 06:00:02 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.173 2018/08/23 21:01:43 skrll Exp $");
#include "opt_compat_netbsd.h"
#include "opt_cpuoptions.h"
@@ -2934,7 +2934,7 @@ struct cpu_option armv7_options[] = {
{ "armv7.cache",BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "armv7.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
{ "armv7.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
- { NULL, IGN, IGN, 0}
+{ NULL, IGN, IGN, 0}
};
void
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: skrll Date: Wed Aug 15 05:57:01 UTC 2018 Modified Files: src/sys/arch/arm/arm: arm_machdep.c Log Message: sort #include "opt_..." entries To generate a diff of this commit: cvs rdiff -u -r1.53 -r1.54 src/sys/arch/arm/arm/arm_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/arm_machdep.c diff -u src/sys/arch/arm/arm/arm_machdep.c:1.53 src/sys/arch/arm/arm/arm_machdep.c:1.54 --- src/sys/arch/arm/arm/arm_machdep.c:1.53 Wed Jan 24 09:04:44 2018 +++ src/sys/arch/arm/arm/arm_machdep.c Wed Aug 15 05:57:01 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: arm_machdep.c,v 1.53 2018/01/24 09:04:44 skrll Exp $ */ +/* $NetBSD: arm_machdep.c,v 1.54 2018/08/15 05:57:01 skrll Exp $ */ /* * Copyright (c) 2001 Wasabi Systems, Inc. @@ -71,16 +71,16 @@ * SUCH DAMAGE. */ -#include "opt_execfmt.h" +#include "opt_arm_debug.h" #include "opt_cpuoptions.h" #include "opt_cputypes.h" -#include "opt_arm_debug.h" -#include "opt_multiprocessor.h" +#include "opt_execfmt.h" #include "opt_modular.h" +#include "opt_multiprocessor.h" #include -__KERNEL_RCSID(0, "$NetBSD: arm_machdep.c,v 1.53 2018/01/24 09:04:44 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: arm_machdep.c,v 1.54 2018/08/15 05:57:01 skrll Exp $"); #include #include
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: jakllsch Date: Fri Jun 15 15:59:20 UTC 2018 Modified Files: src/sys/arch/arm/arm: psci.c Log Message: Use correct value for PSCI 0.2+ PSCI_CPU_ON. To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/arm/psci.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/psci.c diff -u src/sys/arch/arm/arm/psci.c:1.1 src/sys/arch/arm/arm/psci.c:1.2 --- src/sys/arch/arm/arm/psci.c:1.1 Wed Jun 28 23:48:23 2017 +++ src/sys/arch/arm/arm/psci.c Fri Jun 15 15:59:20 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: psci.c,v 1.1 2017/06/28 23:48:23 jmcneill Exp $ */ +/* $NetBSD: psci.c,v 1.2 2018/06/15 15:59:20 jakllsch Exp $ */ /*- * Copyright (c) 2017 Jared McNeill @@ -29,7 +29,7 @@ #include "opt_diagnostic.h" #include -__KERNEL_RCSID(0, "$NetBSD: psci.c,v 1.1 2017/06/28 23:48:23 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: psci.c,v 1.2 2018/06/15 15:59:20 jakllsch Exp $"); #include #include @@ -43,9 +43,9 @@ __KERNEL_RCSID(0, "$NetBSD: psci.c,v 1.1 #define PSCI_SYSTEM_OFF 0x8408 #define PSCI_SYSTEM_RESET 0x8409 #if defined(__aarch64__) -#define PSCI_CPU_ON 0xc402 +#define PSCI_CPU_ON 0xc403 #else -#define PSCI_CPU_ON 0x8402 +#define PSCI_CPU_ON 0x8403 #endif static psci_fn psci_call_fn;
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: martin
Date: Fri May 25 15:37:58 UTC 2018
Modified Files:
src/sys/arch/arm/arm: syscall.c
Log Message:
PR kern/53261: handle SYS_syscall indirection in MD code - the generic
version would misalign the argument array.
To generate a diff of this commit:
cvs rdiff -u -r1.64 -r1.65 src/sys/arch/arm/arm/syscall.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/syscall.c
diff -u src/sys/arch/arm/arm/syscall.c:1.64 src/sys/arch/arm/arm/syscall.c:1.65
--- src/sys/arch/arm/arm/syscall.c:1.64 Wed Jan 24 09:04:44 2018
+++ src/sys/arch/arm/arm/syscall.c Fri May 25 15:37:57 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: syscall.c,v 1.64 2018/01/24 09:04:44 skrll Exp $ */
+/* $NetBSD: syscall.c,v 1.65 2018/05/25 15:37:57 martin Exp $ */
/*-
* Copyright (c) 2000, 2003 The NetBSD Foundation, Inc.
@@ -71,7 +71,7 @@
#include
-__KERNEL_RCSID(0, "$NetBSD: syscall.c,v 1.64 2018/01/24 09:04:44 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: syscall.c,v 1.65 2018/05/25 15:37:57 martin Exp $");
#include
#include
@@ -185,9 +185,10 @@ syscall(struct trapframe *tf, lwp_t *l,
struct proc * const p = l->l_proc;
const struct sysent *callp;
int error;
- u_int nargs;
+ u_int nargs, off = 0;
register_t *args;
- uint64_t copyargs64[sizeof(register_t)*(2+SYS_MAXSYSARGS+1)/sizeof(uint64_t)];
+ uint64_t copyargs64[sizeof(register_t) *
+ (2+SYS_MAXSYSARGS+1)/sizeof(uint64_t)];
register_t *copyargs = (register_t *)copyargs64;
register_t rval[2];
ksiginfo_t ksi;
@@ -221,17 +222,29 @@ syscall(struct trapframe *tf, lwp_t *l,
}
code &= (SYS_NSYSENT - 1);
+
+ if (__predict_false(code == SYS_syscall)) {
+ off = 1;
+ code = tf->tf_r0;
+ code &= (SYS_NSYSENT - 1);
+ if (__predict_false(code == SYS_syscall)) {
+ error = EINVAL;
+ goto bad;
+ }
+ }
+
callp = p->p_emul->e_sysent + code;
nargs = callp->sy_narg;
- if (nargs > 4) {
+
+ if ((nargs+off) > 4) {
args = copyargs;
- memcpy(args, >tf_r0, 4 * sizeof(register_t));
- error = copyin((void *)tf->tf_usr_sp, args + 4,
- (nargs - 4) * sizeof(register_t));
+ memcpy(args, >tf_r0+off, (4-off) * sizeof(register_t));
+ error = copyin((void *)tf->tf_usr_sp, args + 4 - off,
+ (nargs - 4 + off) * sizeof(register_t));
if (error)
goto bad;
} else {
- args = >tf_r0;
+ args = >tf_r0 + off;
}
error = sy_invoke(callp, l, args, rval, code);
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: christos
Date: Sat Jan 20 14:43:25 UTC 2018
Modified Files:
src/sys/arch/arm/arm: cpufunc_asm_arm11x6.S
Log Message:
PR/52934: Yasushi Oshima: Apply the erratum fix that was applied to wbinv_range
to isync_range so that we don't hang when we try to sync from execcmd_readvn().
XXX: pullup 8
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S:1.9 src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S:1.10
--- src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S:1.9 Sat Jul 15 02:25:20 2017
+++ src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S Sat Jan 20 09:43:25 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_arm11x6.S,v 1.9 2017/07/15 06:25:20 skrll Exp $ */
+/* $NetBSD: cpufunc_asm_arm11x6.S,v 1.10 2018/01/20 14:43:25 christos Exp $ */
/*
* Copyright (c) 2007 Microsoft
@@ -63,7 +63,7 @@
#include
#include
-RCSID("$NetBSD: cpufunc_asm_arm11x6.S,v 1.9 2017/07/15 06:25:20 skrll Exp $")
+RCSID("$NetBSD: cpufunc_asm_arm11x6.S,v 1.10 2018/01/20 14:43:25 christos Exp $")
#if 0
#define Invalidate_I_cache(Rtmp1, Rtmp2) \
@@ -137,6 +137,11 @@ ENTRY_NP(arm11x6_flush_prefetchbuf)
END(arm11x6_flush_prefetchbuf)
ENTRY_NP(arm11x6_icache_sync_range)
+ ldr r2, .Larm_pcache
+ ldr r2, [r2, #DCACHE_SIZE]
+ cmp r1, r2
+ bge arm11x6_icache_sync_all
+
add r1, r1, r0
sub r1, r1, #1
/* Erratum ARM1136 371025, workaround #2 */
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Thu Jan 18 14:18:23 UTC 2018
Modified Files:
src/sys/arch/arm/arm: syscall.c
Log Message:
Fix test for SMI_IMB{,range} that was broken in 1.46
>From Ramakrishna Rao Desetti
To generate a diff of this commit:
cvs rdiff -u -r1.62 -r1.63 src/sys/arch/arm/arm/syscall.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/syscall.c
diff -u src/sys/arch/arm/arm/syscall.c:1.62 src/sys/arch/arm/arm/syscall.c:1.63
--- src/sys/arch/arm/arm/syscall.c:1.62 Sun Jul 2 16:16:44 2017
+++ src/sys/arch/arm/arm/syscall.c Thu Jan 18 14:18:23 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: syscall.c,v 1.62 2017/07/02 16:16:44 skrll Exp $ */
+/* $NetBSD: syscall.c,v 1.63 2018/01/18 14:18:23 skrll Exp $ */
/*-
* Copyright (c) 2000, 2003 The NetBSD Foundation, Inc.
@@ -71,7 +71,7 @@
#include
-__KERNEL_RCSID(0, "$NetBSD: syscall.c,v 1.62 2017/07/02 16:16:44 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: syscall.c,v 1.63 2018/01/18 14:18:23 skrll Exp $");
#include
#include
@@ -214,8 +214,9 @@ syscall(struct trapframe *tf, lwp_t *l,
/* test new official and old unofficial NetBSD ranges */
if (__predict_false(os_mask != SWI_OS_NETBSD)
&& __predict_false(os_mask != 0)) {
- if (os_mask == SWI_OS_ARM
- && (code == SWI_IMB || code == SWI_IMBrange)) {
+
+ const uint32_t swi = __SHIFTOUT(insn, __BITS(23,0));
+ if (swi == SWI_IMB || swi == SWI_IMBrange) {
userret(l);
return;
}
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: christos Date: Wed Jan 17 02:37:33 UTC 2018 Modified Files: src/sys/arch/arm/arm: cpufunc_asm_xscale.S Log Message: rename DCACHE_SIZE to XSCALE_DCACHE_SIZE to avoid conflict with genassym field offset with the same name. To generate a diff of this commit: cvs rdiff -u -r1.23 -r1.24 src/sys/arch/arm/arm/cpufunc_asm_xscale.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/cpufunc_asm_xscale.S diff -u src/sys/arch/arm/arm/cpufunc_asm_xscale.S:1.23 src/sys/arch/arm/arm/cpufunc_asm_xscale.S:1.24 --- src/sys/arch/arm/arm/cpufunc_asm_xscale.S:1.23 Sat Mar 29 21:15:03 2014 +++ src/sys/arch/arm/arm/cpufunc_asm_xscale.S Tue Jan 16 21:37:32 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: cpufunc_asm_xscale.S,v 1.23 2014/03/30 01:15:03 matt Exp $ */ +/* $NetBSD: cpufunc_asm_xscale.S,v 1.24 2018/01/17 02:37:32 christos Exp $ */ /* * Copyright (c) 2001, 2002 Wasabi Systems, Inc. @@ -78,7 +78,7 @@ /* * Size of the XScale core D-cache. */ -#define DCACHE_SIZE 0x8000 +#define XSCALE_DCACHE_SIZE 0x8000 .Lblock_userspace_access: .word _C_LABEL(block_userspace_access) @@ -255,7 +255,7 @@ _C_LABEL(xscale_cache_clean_addr): .global _C_LABEL(xscale_cache_clean_size) _C_LABEL(xscale_cache_clean_size): - .word DCACHE_SIZE + .word XSCALE_DCACHE_SIZE .global _C_LABEL(xscale_minidata_clean_addr) _C_LABEL(xscale_minidata_clean_addr): @@ -311,7 +311,7 @@ _C_LABEL(xscale_minidata_clean_size): * alternate between them whenever this is done. No one knows \ * why the work-around works (mmm!).\ */\ - eor r0, r0, #(DCACHE_SIZE); \ + eor r0, r0, #(XSCALE_DCACHE_SIZE) ; \ str r0, [r2] ; \ add r0, r0, r1
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Sun Oct 22 07:52:40 UTC 2017
Modified Files:
src/sys/arch/arm/arm: cpufunc.c
Log Message:
KNF
To generate a diff of this commit:
cvs rdiff -u -r1.166 -r1.167 src/sys/arch/arm/arm/cpufunc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc.c
diff -u src/sys/arch/arm/arm/cpufunc.c:1.166 src/sys/arch/arm/arm/cpufunc.c:1.167
--- src/sys/arch/arm/arm/cpufunc.c:1.166 Sun Aug 27 11:44:49 2017
+++ src/sys/arch/arm/arm/cpufunc.c Sun Oct 22 07:52:40 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.166 2017/08/27 11:44:49 skrll Exp $ */
+/* $NetBSD: cpufunc.c,v 1.167 2017/10/22 07:52:40 skrll Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.166 2017/08/27 11:44:49 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.167 2017/10/22 07:52:40 skrll Exp $");
#include "opt_compat_netbsd.h"
#include "opt_cpuoptions.h"
@@ -2194,7 +2194,7 @@ set_cpufuncs(void)
* B. And the answer was ...
*/
panic("No support for this CPU type (%08x) in kernel", cputype);
- return(ARCHITECTURE_NOT_PRESENT);
+ return ARCHITECTURE_NOT_PRESENT;
}
#ifdef CPU_ARM2
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Sun Aug 27 11:44:49 UTC 2017
Modified Files:
src/sys/arch/arm/arm: cpufunc.c
Log Message:
#ifdef whack-a-mole
To generate a diff of this commit:
cvs rdiff -u -r1.165 -r1.166 src/sys/arch/arm/arm/cpufunc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc.c
diff -u src/sys/arch/arm/arm/cpufunc.c:1.165 src/sys/arch/arm/arm/cpufunc.c:1.166
--- src/sys/arch/arm/arm/cpufunc.c:1.165 Sat Aug 26 07:17:12 2017
+++ src/sys/arch/arm/arm/cpufunc.c Sun Aug 27 11:44:49 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.165 2017/08/26 07:17:12 skrll Exp $ */
+/* $NetBSD: cpufunc.c,v 1.166 2017/08/27 11:44:49 skrll Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.165 2017/08/26 07:17:12 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.166 2017/08/27 11:44:49 skrll Exp $");
#include "opt_compat_netbsd.h"
#include "opt_cpuoptions.h"
@@ -1764,6 +1764,7 @@ get_cachetype_table(void)
#endif /* ARM2 || ARM250 || ARM3 || ARM6 || ARM7 || SA110 || SA1100 || SA || IXP12X0 */
+#if defined(CPU_CORTEX) || defined(CPU_PJ4B)
static inline void
set_cpufuncs_mpfixup(void)
{
@@ -1780,6 +1781,7 @@ set_cpufuncs_mpfixup(void)
}
#endif
}
+#endif
/*
* Cannot panic here as we may not have a console yet ...
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Sat Aug 26 07:17:12 UTC 2017
Modified Files:
src/sys/arch/arm/arm: cpufunc.c
Log Message:
Fixup CPU_PJ4B for recent armv7 tlb operation changes.
To generate a diff of this commit:
cvs rdiff -u -r1.164 -r1.165 src/sys/arch/arm/arm/cpufunc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc.c
diff -u src/sys/arch/arm/arm/cpufunc.c:1.164 src/sys/arch/arm/arm/cpufunc.c:1.165
--- src/sys/arch/arm/arm/cpufunc.c:1.164 Thu Aug 24 14:19:36 2017
+++ src/sys/arch/arm/arm/cpufunc.c Sat Aug 26 07:17:12 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.164 2017/08/24 14:19:36 jmcneill Exp $ */
+/* $NetBSD: cpufunc.c,v 1.165 2017/08/26 07:17:12 skrll Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.164 2017/08/24 14:19:36 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.165 2017/08/26 07:17:12 skrll Exp $");
#include "opt_compat_netbsd.h"
#include "opt_cpuoptions.h"
@@ -1364,12 +1364,12 @@ struct cpu_functions pj4bv7_cpufuncs = {
/* TLB functions */
- .cf_tlb_flushID = armv7_tlb_flushID,
- .cf_tlb_flushID_SE = armv7_tlb_flushID_SE,
- .cf_tlb_flushI = armv7_tlb_flushID,
- .cf_tlb_flushI_SE = armv7_tlb_flushID_SE,
- .cf_tlb_flushD = armv7_tlb_flushID,
- .cf_tlb_flushD_SE = armv7_tlb_flushID_SE,
+ .cf_tlb_flushID = armv7up_tlb_flushID,
+ .cf_tlb_flushID_SE = armv7up_tlb_flushID_SE,
+ .cf_tlb_flushI = armv7up_tlb_flushID,
+ .cf_tlb_flushI_SE = armv7up_tlb_flushID_SE,
+ .cf_tlb_flushD = armv7up_tlb_flushID,
+ .cf_tlb_flushD_SE = armv7up_tlb_flushID_SE,
/* Cache operations (see also pj4bv7_setup) */
.cf_icache_sync_all = armv7_idcache_wbinv_all,
@@ -1763,6 +1763,24 @@ get_cachetype_table(void)
#endif /* ARM2 || ARM250 || ARM3 || ARM6 || ARM7 || SA110 || SA1100 || SA || IXP12X0 */
+
+static inline void
+set_cpufuncs_mpfixup(void)
+{
+#ifdef MULTIPROCESSOR
+ /* If MP extensions are present, patch in MP TLB ops */
+ const uint32_t mpidr = armreg_mpidr_read();
+ if ((mpidr & (MPIDR_MP|MPIDR_U)) == MPIDR_MP) {
+ cpufuncs.cf_tlb_flushID = armv7mp_tlb_flushID;
+ cpufuncs.cf_tlb_flushID_SE = armv7mp_tlb_flushID_SE;
+ cpufuncs.cf_tlb_flushI = armv7mp_tlb_flushI;
+ cpufuncs.cf_tlb_flushI_SE = armv7mp_tlb_flushI_SE;
+ cpufuncs.cf_tlb_flushD = armv7mp_tlb_flushD;
+ cpufuncs.cf_tlb_flushD_SE = armv7mp_tlb_flushD_SE;
+ }
+#endif
+}
+
/*
* Cannot panic here as we may not have a console yet ...
*/
@@ -2134,18 +2152,7 @@ set_cpufuncs(void)
#if defined(CPU_CORTEX)
if (CPU_ID_CORTEX_P(cputype)) {
cpufuncs = armv7_cpufuncs;
-#ifdef MULTIPROCESSOR
- /* If MP extensions are present, patch in MP TLB ops */
- const uint32_t mpidr = armreg_mpidr_read();
- if ((mpidr & (MPIDR_MP|MPIDR_U)) == MPIDR_MP) {
- cpufuncs.cf_tlb_flushID = armv7mp_tlb_flushID;
- cpufuncs.cf_tlb_flushID_SE = armv7mp_tlb_flushID_SE;
- cpufuncs.cf_tlb_flushI = armv7mp_tlb_flushI;
- cpufuncs.cf_tlb_flushI_SE = armv7mp_tlb_flushI_SE;
- cpufuncs.cf_tlb_flushD = armv7mp_tlb_flushD;
- cpufuncs.cf_tlb_flushD_SE = armv7mp_tlb_flushD_SE;
- }
-#endif
+ set_cpufuncs_mpfixup();
cpu_do_powersave = 1; /* Enable powersave */
#if defined(CPU_ARMV6) || defined(CPU_PRE_ARMV6)
cpu_armv7_p = true;
@@ -2171,6 +2178,7 @@ set_cpufuncs(void)
cputype == CPU_ID_ARM_88SV581X_V7) &&
(armreg_pfr0_read() & ARM_PFR0_THUMBEE_MASK)) {
cpufuncs = pj4bv7_cpufuncs;
+ set_cpufuncs_mpfixup();
#if defined(CPU_ARMV6) || defined(CPU_PRE_ARMV6)
cpu_armv7_p = true;
#endif
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Sun Jul 23 13:35:15 UTC 2017
Modified Files:
src/sys/arch/arm/arm: arm_machdep.c
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.51 -r1.52 src/sys/arch/arm/arm/arm_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/arm_machdep.c
diff -u src/sys/arch/arm/arm/arm_machdep.c:1.51 src/sys/arch/arm/arm/arm_machdep.c:1.52
--- src/sys/arch/arm/arm/arm_machdep.c:1.51 Tue Apr 4 11:46:12 2017
+++ src/sys/arch/arm/arm/arm_machdep.c Sun Jul 23 13:35:15 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: arm_machdep.c,v 1.51 2017/04/04 11:46:12 sevan Exp $ */
+/* $NetBSD: arm_machdep.c,v 1.52 2017/07/23 13:35:15 skrll Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -80,7 +80,7 @@
#include
-__KERNEL_RCSID(0, "$NetBSD: arm_machdep.c,v 1.51 2017/04/04 11:46:12 sevan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: arm_machdep.c,v 1.52 2017/07/23 13:35:15 skrll Exp $");
#include
#include
@@ -191,7 +191,7 @@ setregs(struct lwp *l, struct exec_packa
tf->tf_spsr = PSR_USR32_MODE | (CPU_IS_ARMV7_P() ? PSR_E_BIT : 0);
#else
tf->tf_spsr = PSR_USR32_MODE;
-#endif /* __ARMEB__ */
+#endif /* __ARMEB__ */
#ifdef THUMB_CODE
if (pack->ep_entry & 1)
@@ -217,7 +217,7 @@ setregs(struct lwp *l, struct exec_packa
void
startlwp(void *arg)
{
- ucontext_t *uc = (ucontext_t *)arg;
+ ucontext_t *uc = (ucontext_t *)arg;
lwp_t *l = curlwp;
int error __diagused;
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Sat Jul 15 06:25:20 UTC 2017
Modified Files:
src/sys/arch/arm/arm: cpufunc_asm_arm11x6.S
Log Message:
Fix a comment
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S:1.8 src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S:1.9
--- src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S:1.8 Wed Jul 12 07:22:31 2017
+++ src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S Sat Jul 15 06:25:20 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_arm11x6.S,v 1.8 2017/07/12 07:22:31 skrll Exp $ */
+/* $NetBSD: cpufunc_asm_arm11x6.S,v 1.9 2017/07/15 06:25:20 skrll Exp $ */
/*
* Copyright (c) 2007 Microsoft
@@ -63,7 +63,7 @@
#include
#include
-RCSID("$NetBSD: cpufunc_asm_arm11x6.S,v 1.8 2017/07/12 07:22:31 skrll Exp $")
+RCSID("$NetBSD: cpufunc_asm_arm11x6.S,v 1.9 2017/07/15 06:25:20 skrll Exp $")
#if 0
#define Invalidate_I_cache(Rtmp1, Rtmp2) \
@@ -73,7 +73,7 @@ RCSID("$NetBSD: cpufunc_asm_arm11x6.S,v
* Workaround for
*
*Erratum 411920 in ARM1136 (fixed in r1p4)
- *Erratum 415045 in ARM1176 (fixed in r0p5?)
+ *Erratum 415045 in ARM1176 (fixed in r0p5)
*
* - value of arg 'reg' Should Be Zero
*/
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: skrll Date: Sat Jul 15 06:20:22 UTC 2017 Modified Files: src/sys/arch/arm/arm: cpufunc_asm_armv6.S Log Message: Spell invalidate correctly in comments. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/arm/cpufunc_asm_armv6.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/cpufunc_asm_armv6.S diff -u src/sys/arch/arm/arm/cpufunc_asm_armv6.S:1.7 src/sys/arch/arm/arm/cpufunc_asm_armv6.S:1.8 --- src/sys/arch/arm/arm/cpufunc_asm_armv6.S:1.7 Fri Aug 1 05:53:31 2014 +++ src/sys/arch/arm/arm/cpufunc_asm_armv6.S Sat Jul 15 06:20:22 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: cpufunc_asm_armv6.S,v 1.7 2014/08/01 05:53:31 skrll Exp $ */ +/* $NetBSD: cpufunc_asm_armv6.S,v 1.8 2017/07/15 06:20:22 skrll Exp $ */ /* * Copyright (c) 2002, 2005 ARM Limited @@ -100,7 +100,7 @@ END(armv6_dcache_wb_range) ENTRY(armv6_dcache_wbinv_range) add r1, r1, r0 sub r1, r1, #1 - mcrr p15, 0, r1, r0, c14 /* clean and invaliate D cache range */ + mcrr p15, 0, r1, r0, c14 /* clean and invalidate D cache range */ mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ RET END(armv6_dcache_wbinv_range) @@ -114,7 +114,7 @@ END(armv6_dcache_wbinv_range) ENTRY(armv6_dcache_inv_range) add r1, r1, r0 sub r1, r1, #1 - mcrr p15, 0, r1, r0, c6 /* invaliate D cache range */ + mcrr p15, 0, r1, r0, c6 /* invalidate D cache range */ mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ RET END(armv6_dcache_inv_range) @@ -123,8 +123,8 @@ END(armv6_dcache_inv_range) ENTRY(armv6_idcache_wbinv_range) add r1, r1, r0 sub r1, r1, #1 - mcrr p15, 0, r1, r0, c5 /* invaliate I cache range */ - mcrr p15, 0, r1, r0, c14 /* clean & invaliate D cache range */ + mcrr p15, 0, r1, r0, c5 /* invalidate I cache range */ + mcrr p15, 0, r1, r0, c14 /* clean & invalidate D cache range */ mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ RET END(armv6_idcache_wbinv_range)
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Sat Jun 3 11:51:59 UTC 2017
Modified Files:
src/sys/arch/arm/arm: disassem.c
Log Message:
Adjust the output of {ldr,str}x instructions slightly and deal with the
writeback bit.
To generate a diff of this commit:
cvs rdiff -u -r1.38 -r1.39 src/sys/arch/arm/arm/disassem.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/disassem.c
diff -u src/sys/arch/arm/arm/disassem.c:1.38 src/sys/arch/arm/arm/disassem.c:1.39
--- src/sys/arch/arm/arm/disassem.c:1.38 Fri Jun 2 21:20:47 2017
+++ src/sys/arch/arm/arm/disassem.c Sat Jun 3 11:51:59 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: disassem.c,v 1.38 2017/06/02 21:20:47 skrll Exp $ */
+/* $NetBSD: disassem.c,v 1.39 2017/06/03 11:51:59 skrll Exp $ */
/*
* Copyright (c) 1996 Mark Brinicombe.
@@ -49,7 +49,7 @@
#include
-__KERNEL_RCSID(0, "$NetBSD: disassem.c,v 1.38 2017/06/02 21:20:47 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: disassem.c,v 1.39 2017/06/03 11:51:59 skrll Exp $");
#include
@@ -203,6 +203,7 @@ static const struct arm32_insn arm32_i[]
/* A5.2 exceptions */
/* A5.2.7 Halfword multiply and multiply accumulate */
+
/* A5.2.9 Extra load/store instructions, unprivileged */
{ 0x0f3000f0, 0x002000b0, "strht", "de" },
@@ -898,15 +899,17 @@ disasm_insn_ldrxstrx(const disasm_interf
di->di_printf("[r%d", (insn >> 16) & 0x0f);
if ((insn & 0x01400f0f) != 0x0140) {
di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]");
- if (!(insn & 0x0080))
-di->di_printf("-");
+ char const *sign = (insn & 0x0080) ? "" : "-";
if (insn & (1 << 22))
-di->di_printf("#0x%02x", offset);
+di->di_printf("#%s0x%02x", sign, offset);
else
-di->di_printf("r%d", (insn & 0x0f));
+di->di_printf("%sr%d", sign, (insn & 0x0f));
}
- if (insn & (1 << 24))
+ if (insn & (1 << 24)) {
di->di_printf("]");
+ if (__SHIFTOUT(insn, __BIT(21)))
+di->di_printf("!");
+ }
}
}
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Fri Jun 2 21:20:47 UTC 2017
Modified Files:
src/sys/arch/arm/arm: disassem.c
Log Message:
Fix the fix by removing redundant lines. Thanks chuq.
To generate a diff of this commit:
cvs rdiff -u -r1.37 -r1.38 src/sys/arch/arm/arm/disassem.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/disassem.c
diff -u src/sys/arch/arm/arm/disassem.c:1.37 src/sys/arch/arm/arm/disassem.c:1.38
--- src/sys/arch/arm/arm/disassem.c:1.37 Fri Jun 2 19:58:31 2017
+++ src/sys/arch/arm/arm/disassem.c Fri Jun 2 21:20:47 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: disassem.c,v 1.37 2017/06/02 19:58:31 skrll Exp $ */
+/* $NetBSD: disassem.c,v 1.38 2017/06/02 21:20:47 skrll Exp $ */
/*
* Copyright (c) 1996 Mark Brinicombe.
@@ -49,7 +49,7 @@
#include
-__KERNEL_RCSID(0, "$NetBSD: disassem.c,v 1.37 2017/06/02 19:58:31 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: disassem.c,v 1.38 2017/06/02 21:20:47 skrll Exp $");
#include
@@ -215,15 +215,11 @@ static const struct arm32_insn arm32_i[]
{ 0x0e1000f0, 0x00b0, "strh", "de" },
{ 0x0e1000f0, 0x001000b0, "ldrh", "de" },
-{ 0x0e5000f0, 0x00d0, "ldrd", "de" },
-{ 0x0e1000f0, 0x001000d0, "ldrsb", "de" },
{ 0x0e1000f0, 0x00d0, "ldrd", "de" },
{ 0x0e1000f0, 0x001000d0, "ldrsb", "de" },
{ 0x0e1000f0, 0x00f0, "strd", "de" },
{ 0x0e1000f0, 0x001000f0, "ldrsh", "de" },
-{ 0x0e1000f0, 0x00f0, "strd", "de" },
-{ 0x0e1000f0, 0x001000f0, "ldrsh", "de" },
/* A5.2.11 MSR (immediate), and hints */
{ 0x0fff, 0x0320f000, "nop", "" },
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Fri Jun 2 19:58:31 UTC 2017
Modified Files:
src/sys/arch/arm/arm: disassem.c
Log Message:
Fix up some instructions. Prompted by chuq.
To generate a diff of this commit:
cvs rdiff -u -r1.36 -r1.37 src/sys/arch/arm/arm/disassem.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/disassem.c
diff -u src/sys/arch/arm/arm/disassem.c:1.36 src/sys/arch/arm/arm/disassem.c:1.37
--- src/sys/arch/arm/arm/disassem.c:1.36 Wed Apr 26 08:20:47 2017
+++ src/sys/arch/arm/arm/disassem.c Fri Jun 2 19:58:31 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: disassem.c,v 1.36 2017/04/26 08:20:47 skrll Exp $ */
+/* $NetBSD: disassem.c,v 1.37 2017/06/02 19:58:31 skrll Exp $ */
/*
* Copyright (c) 1996 Mark Brinicombe.
@@ -49,7 +49,7 @@
#include
-__KERNEL_RCSID(0, "$NetBSD: disassem.c,v 1.36 2017/04/26 08:20:47 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: disassem.c,v 1.37 2017/06/02 19:58:31 skrll Exp $");
#include
@@ -203,6 +203,12 @@ static const struct arm32_insn arm32_i[]
/* A5.2 exceptions */
/* A5.2.7 Halfword multiply and multiply accumulate */
+/* A5.2.9 Extra load/store instructions, unprivileged */
+
+{ 0x0f3000f0, 0x002000b0, "strht", "de" },
+{ 0x0f3000f0, 0x003000b0, "ldrht", "de" },
+{ 0x0f3000f0, 0x003000d0, "ldrsbt", "de" },
+{ 0x0f3000f0, 0x003000f0, "ldrsht", "de" },
/* A5.2.8 Extra load/store instructions */
@@ -210,12 +216,12 @@ static const struct arm32_insn arm32_i[]
{ 0x0e1000f0, 0x001000b0, "ldrh", "de" },
{ 0x0e5000f0, 0x00d0, "ldrd", "de" },
-{ 0x0e5000f0, 0x001000d0, "ldrsb", "de" },
-{ 0x0e5000f0, 0x004000d0, "ldrd", "de" },
-{ 0x0e5000f0, 0x005000d0, "ldrsb", "de" },
+{ 0x0e1000f0, 0x001000d0, "ldrsb", "de" },
+{ 0x0e1000f0, 0x00d0, "ldrd", "de" },
+{ 0x0e1000f0, 0x001000d0, "ldrsb", "de" },
-{ 0x0e1000f0, 0x00f0, "ldrd", "de" },
-{ 0x0e1000f0, 0x001000f0, "ldrsb", "de" },
+{ 0x0e1000f0, 0x00f0, "strd", "de" },
+{ 0x0e1000f0, 0x001000f0, "ldrsh", "de" },
{ 0x0e1000f0, 0x00f0, "strd", "de" },
{ 0x0e1000f0, 0x001000f0, "ldrsh", "de" },
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Fri May 12 05:46:39 UTC 2017
Modified Files:
src/sys/arch/arm/arm: ast.c
Log Message:
KASSERT -> MASSERTMSG
To generate a diff of this commit:
cvs rdiff -u -r1.28 -r1.29 src/sys/arch/arm/arm/ast.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/ast.c
diff -u src/sys/arch/arm/arm/ast.c:1.28 src/sys/arch/arm/arm/ast.c:1.29
--- src/sys/arch/arm/arm/ast.c:1.28 Fri Apr 17 17:28:33 2015
+++ src/sys/arch/arm/arm/ast.c Fri May 12 05:46:39 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: ast.c,v 1.28 2015/04/17 17:28:33 matt Exp $ */
+/* $NetBSD: ast.c,v 1.29 2017/05/12 05:46:39 skrll Exp $ */
/*
* Copyright (c) 1994,1995 Mark Brinicombe
@@ -41,7 +41,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: ast.c,v 1.28 2015/04/17 17:28:33 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ast.c,v 1.29 2017/05/12 05:46:39 skrll Exp $");
#include "opt_ddb.h"
@@ -80,7 +80,9 @@ userret(struct lwp *l)
#ifdef __HAVE_PREEMPTION
kpreempt_disable();
#endif
- KASSERT(curcpu()->ci_pmap_cur == l->l_proc->p_vmspace->vm_map.pmap);
+ KASSERTMSG(curcpu()->ci_pmap_cur == l->l_proc->p_vmspace->vm_map.pmap,
+ "%p vs %p", curcpu()->ci_pmap_cur,
+ l->l_proc->p_vmspace->vm_map.pmap);
if (__predict_false(armreg_ttbcr_read() & TTBCR_S_PD0)) {
pmap_activate(l);
}
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: skrll Date: Sat May 6 13:05:59 UTC 2017 Modified Files: src/sys/arch/arm/arm: undefined.c Log Message: KNF To generate a diff of this commit: cvs rdiff -u -r1.58 -r1.59 src/sys/arch/arm/arm/undefined.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/undefined.c diff -u src/sys/arch/arm/arm/undefined.c:1.58 src/sys/arch/arm/arm/undefined.c:1.59 --- src/sys/arch/arm/arm/undefined.c:1.58 Mon Feb 27 06:46:59 2017 +++ src/sys/arch/arm/arm/undefined.c Sat May 6 13:05:59 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: undefined.c,v 1.58 2017/02/27 06:46:59 chs Exp $ */ +/* $NetBSD: undefined.c,v 1.59 2017/05/06 13:05:59 skrll Exp $ */ /* * Copyright (c) 2001 Ben Harris. @@ -47,15 +47,15 @@ #define FAST_FPE #include "opt_ddb.h" -#include "opt_kgdb.h" #include "opt_dtrace.h" +#include "opt_kgdb.h" #include #ifdef KGDB #include #endif -__KERNEL_RCSID(0, "$NetBSD: undefined.c,v 1.58 2017/02/27 06:46:59 chs Exp $"); +__KERNEL_RCSID(0, "$NetBSD: undefined.c,v 1.59 2017/05/06 13:05:59 skrll Exp $"); #include #include
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Wed Apr 26 08:20:47 UTC 2017
Modified Files:
src/sys/arch/arm/arm: disassem.c
Log Message:
Move mcrr/mrrc earlier so they match before stc/ldc
To generate a diff of this commit:
cvs rdiff -u -r1.35 -r1.36 src/sys/arch/arm/arm/disassem.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/disassem.c
diff -u src/sys/arch/arm/arm/disassem.c:1.35 src/sys/arch/arm/arm/disassem.c:1.36
--- src/sys/arch/arm/arm/disassem.c:1.35 Sat Mar 11 12:19:30 2017
+++ src/sys/arch/arm/arm/disassem.c Wed Apr 26 08:20:47 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: disassem.c,v 1.35 2017/03/11 12:19:30 skrll Exp $ */
+/* $NetBSD: disassem.c,v 1.36 2017/04/26 08:20:47 skrll Exp $ */
/*
* Copyright (c) 1996 Mark Brinicombe.
@@ -49,7 +49,7 @@
#include
-__KERNEL_RCSID(0, "$NetBSD: disassem.c,v 1.35 2017/03/11 12:19:30 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: disassem.c,v 1.36 2017/04/26 08:20:47 skrll Exp $");
#include
@@ -149,10 +149,10 @@ static const struct arm32_insn arm32_i[]
{ 0xfe5fffe0, 0xf84d0500, "srs", "XnW!m" },
{ 0xfe50, 0xf8100a00, "rfe", "XnW" },
{ 0xfe00, 0xfa00, "blx", "t" }, /* Before b and bl */
-{ 0xfe100090, 0xfc00, "stc2", "L#v" },
-{ 0x0e100090, 0x0c00, "stc", "L#v" },
{ 0x0ff0, 0x0c40, "mcrr", "#&" },
{ 0x0ff0, 0x0c50, "mrrc", "#&" },
+{ 0xfe100090, 0xfc00, "stc2", "L#v" },
+{ 0x0e100090, 0x0c00, "stc", "L#v" },
{ 0xfe100090, 0xfc10, "ldc2", "L#v" },
{ 0x0e100090, 0x0c10, "ldc", "L#v" },
{ 0xff10, 0xfe00, "cdp2", "#y" },
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Tue Apr 25 09:02:05 UTC 2017
Modified Files:
src/sys/arch/arm/arm: db_trace.c
Log Message:
Report trapframe where possible
To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/arm/arm/db_trace.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/db_trace.c
diff -u src/sys/arch/arm/arm/db_trace.c:1.31 src/sys/arch/arm/arm/db_trace.c:1.32
--- src/sys/arch/arm/arm/db_trace.c:1.31 Sat Jan 24 15:44:32 2015
+++ src/sys/arch/arm/arm/db_trace.c Tue Apr 25 09:02:04 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: db_trace.c,v 1.31 2015/01/24 15:44:32 skrll Exp $ */
+/* $NetBSD: db_trace.c,v 1.32 2017/04/25 09:02:04 skrll Exp $ */
/*
* Copyright (c) 2000, 2001 Ben Harris
@@ -31,7 +31,7 @@
#include
-__KERNEL_RCSID(0, "$NetBSD: db_trace.c,v 1.31 2015/01/24 15:44:32 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_trace.c,v 1.32 2017/04/25 09:02:04 skrll Exp $");
#include
#include
@@ -86,6 +86,7 @@ db_stack_trace_print(db_expr_t addr, boo
db_expr_t count, const char *modif,
void (*pr)(const char *, ...))
{
+ struct trapframe *tf = NULL;
uint32_t *frame, *lastframe;
const char *cp = modif;
char c;
@@ -140,6 +141,7 @@ db_stack_trace_print(db_expr_t addr, boo
}
(*pr)("lid %d ", l.l_lid);
pcb = lwp_getpcb();
+ tf = lwp_trapframe();
#ifndef _KERNEL
struct pcb pcbb;
db_read_bytes((db_addr_t)pcb, sizeof(*pcb),
@@ -258,6 +260,9 @@ db_stack_trace_print(db_expr_t addr, boo
break;
}
} else if (INKERNEL((int)lastframe)) {
+ if (trace_thread) {
+(*pr)("--- tf %p ---\n", tf);
+ }
/* switch from user to kernel */
if (kernel_only)
break; /* kernel stack only */
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: sevan
Date: Tue Apr 4 11:46:13 UTC 2017
Modified Files:
src/sys/arch/arm/arm: arm_machdep.c
Log Message:
Define NCPUINFO and set it to 1 or MAXCPUS whether on single or multiprocessor
system.
Use NCPUINFO as the array size for *cpu_info[].
Closes PR port-hpcarm/52138
Patch by skrll
ok pgoyette
To generate a diff of this commit:
cvs rdiff -u -r1.50 -r1.51 src/sys/arch/arm/arm/arm_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/arm_machdep.c
diff -u src/sys/arch/arm/arm/arm_machdep.c:1.50 src/sys/arch/arm/arm/arm_machdep.c:1.51
--- src/sys/arch/arm/arm/arm_machdep.c:1.50 Thu Mar 16 16:13:20 2017
+++ src/sys/arch/arm/arm/arm_machdep.c Tue Apr 4 11:46:12 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: arm_machdep.c,v 1.50 2017/03/16 16:13:20 chs Exp $ */
+/* $NetBSD: arm_machdep.c,v 1.51 2017/04/04 11:46:12 sevan Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -80,7 +80,7 @@
#include
-__KERNEL_RCSID(0, "$NetBSD: arm_machdep.c,v 1.50 2017/03/16 16:13:20 chs Exp $");
+__KERNEL_RCSID(0, "$NetBSD: arm_machdep.c,v 1.51 2017/04/04 11:46:12 sevan Exp $");
#include
#include
@@ -121,10 +121,14 @@ struct cpu_info cpu_info_store = {
};
#ifdef MULTIPROCESSOR
-struct cpu_info *cpu_info[MAXCPUS] = {
+#define NCPUINFO MAXCPUS
+#else
+#define NCPUINFO 1
+#endif
+
+struct cpu_info *cpu_info[NCPUINFO] = {
[0] = _info_store
};
-#endif
const pcu_ops_t * const pcu_ops_md_defs[PCU_UNIT_COUNT] = {
#if defined(FPU_VFP)
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Sat Mar 11 12:19:30 UTC 2017
Modified Files:
src/sys/arch/arm/arm: disassem.c
Log Message:
Fixup the catchall for the media instructions that are currently unhandled
so that swi, etc can match
To generate a diff of this commit:
cvs rdiff -u -r1.34 -r1.35 src/sys/arch/arm/arm/disassem.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/disassem.c
diff -u src/sys/arch/arm/arm/disassem.c:1.34 src/sys/arch/arm/arm/disassem.c:1.35
--- src/sys/arch/arm/arm/disassem.c:1.34 Mon Dec 14 15:29:45 2015
+++ src/sys/arch/arm/arm/disassem.c Sat Mar 11 12:19:30 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: disassem.c,v 1.34 2015/12/14 15:29:45 skrll Exp $ */
+/* $NetBSD: disassem.c,v 1.35 2017/03/11 12:19:30 skrll Exp $ */
/*
* Copyright (c) 1996 Mark Brinicombe.
@@ -49,7 +49,7 @@
#include
-__KERNEL_RCSID(0, "$NetBSD: disassem.c,v 1.34 2015/12/14 15:29:45 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: disassem.c,v 1.35 2017/03/11 12:19:30 skrll Exp $");
#include
@@ -169,7 +169,7 @@ static const struct arm32_insn arm32_i[]
{ 0x0fe00070, 0x07e00050, "ubfx", "dmir" },
{ 0xfff000f0, 0xe7f0, "und", "x" }, /* Special immediate? */
-{ 0x0610, 0x0610, "und", "x" }, /* Remove when done with media */
+{ 0x0e10, 0x0610, "und", "x" }, /* Remove when done with media */
{ 0x0d70, 0x0420, "strt", "daW" },
{ 0x0d70, 0x0430, "ldrt", "daW" },
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: skrll Date: Tue Feb 21 07:40:28 UTC 2017 Modified Files: src/sys/arch/arm/arm: process_machdep.c Log Message: KNF To generate a diff of this commit: cvs rdiff -u -r1.30 -r1.31 src/sys/arch/arm/arm/process_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/process_machdep.c diff -u src/sys/arch/arm/arm/process_machdep.c:1.30 src/sys/arch/arm/arm/process_machdep.c:1.31 --- src/sys/arch/arm/arm/process_machdep.c:1.30 Wed Aug 13 21:41:32 2014 +++ src/sys/arch/arm/arm/process_machdep.c Tue Feb 21 07:40:28 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: process_machdep.c,v 1.30 2014/08/13 21:41:32 matt Exp $ */ +/* $NetBSD: process_machdep.c,v 1.31 2017/02/21 07:40:28 skrll Exp $ */ /* * Copyright (c) 1993 The Regents of the University of California. @@ -133,7 +133,7 @@ #include -__KERNEL_RCSID(0, "$NetBSD: process_machdep.c,v 1.30 2014/08/13 21:41:32 matt Exp $"); +__KERNEL_RCSID(0, "$NetBSD: process_machdep.c,v 1.31 2017/02/21 07:40:28 skrll Exp $"); #include #include @@ -165,7 +165,7 @@ process_read_regs(struct lwp *l, struct regs->r_pc |= 1; #endif - return(0); + return 0; } int @@ -209,7 +209,7 @@ process_write_regs(struct lwp *l, const tf->tf_r15 = regs->r_pc; #endif - return(0); + return 0; } int @@ -224,7 +224,7 @@ process_write_fpregs(struct lwp *l, cons pcb->pcb_vfp = regs->fpr_vfp; pcb->pcb_vfp.vfp_fpexc &= ~VFP_FPEXC_EN; #endif - return(0); + return 0; } int @@ -248,5 +248,5 @@ process_set_pc(struct lwp *l, void *addr tf->tf_r15 = (tf->tf_r15 & ~R15_PC) | (register_t)addr; #endif - return (0); + return 0; }
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Mon Feb 20 17:25:41 UTC 2017
Modified Files:
src/sys/arch/arm/arm: undefined.c
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.56 -r1.57 src/sys/arch/arm/arm/undefined.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/undefined.c
diff -u src/sys/arch/arm/arm/undefined.c:1.56 src/sys/arch/arm/arm/undefined.c:1.57
--- src/sys/arch/arm/arm/undefined.c:1.56 Wed Apr 15 13:22:50 2015
+++ src/sys/arch/arm/arm/undefined.c Mon Feb 20 17:25:41 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: undefined.c,v 1.56 2015/04/15 13:22:50 matt Exp $ */
+/* $NetBSD: undefined.c,v 1.57 2017/02/20 17:25:41 skrll Exp $ */
/*
* Copyright (c) 2001 Ben Harris.
@@ -55,7 +55,7 @@
#include
#endif
-__KERNEL_RCSID(0, "$NetBSD: undefined.c,v 1.56 2015/04/15 13:22:50 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: undefined.c,v 1.57 2017/02/20 17:25:41 skrll Exp $");
#include
#include
@@ -432,8 +432,8 @@ undefinedinstruction(trapframe_t *tf)
if (uh == NULL) {
/* Fault has not been handled */
- ksiginfo_t ksi;
-
+ ksiginfo_t ksi;
+
#ifdef VERBOSE_ARM32
s = spltty();
@@ -454,7 +454,7 @@ undefinedinstruction(trapframe_t *tf)
splx(s);
#endif
-
+
if ((fault_code & FAULT_USER) == 0) {
#ifdef DDB
db_printf("Undefined instruction %#x in kernel at %#lx (LR %#x SP %#x)\n",
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: jakllsch Date: Sat Jan 28 13:21:11 UTC 2017 Modified Files: src/sys/arch/arm/arm: cpufunc.c Log Message: Drop inadvertent redundant CPU_CONTROL_MMU_ENABLE ((1 < 22)) for PJ4Bv7. This was intended to be CPU_CONTROL_UNAL_ENABLE, which is already handled. Should fix PR kern/51921. To generate a diff of this commit: cvs rdiff -u -r1.162 -r1.163 src/sys/arch/arm/arm/cpufunc.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/cpufunc.c diff -u src/sys/arch/arm/arm/cpufunc.c:1.162 src/sys/arch/arm/arm/cpufunc.c:1.163 --- src/sys/arch/arm/arm/cpufunc.c:1.162 Tue Oct 18 13:58:52 2016 +++ src/sys/arch/arm/arm/cpufunc.c Sat Jan 28 13:21:11 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: cpufunc.c,v 1.162 2016/10/18 13:58:52 kiyohara Exp $ */ +/* $NetBSD: cpufunc.c,v 1.163 2017/01/28 13:21:11 jakllsch Exp $ */ /* * arm7tdmi support code Copyright (c) 2001 John Fremlin @@ -49,7 +49,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.162 2016/10/18 13:58:52 kiyohara Exp $"); +__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.163 2017/01/28 13:21:11 jakllsch Exp $"); #include "opt_compat_netbsd.h" #include "opt_cpuoptions.h" @@ -3076,7 +3076,7 @@ pj4bv7_setup(char *args) cpuctrl |= CPU_CONTROL_IC_ENABLE; cpuctrl |= (0xf << 3); cpuctrl |= CPU_CONTROL_BPRD_ENABLE; - cpuctrl |= (0x5 << 16) | (1 < 22); + cpuctrl |= (0x5 << 16); cpuctrl |= CPU_CONTROL_XP_ENABLE; #ifndef ARM_HAS_VBAR
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: kiyohara Date: Sat Jan 7 15:22:11 UTC 2017 Modified Files: src/sys/arch/arm/arm: cpufunc_asm_pj4b.S Log Message: Add a white-space into comment and `*/'. To generate a diff of this commit: cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/cpufunc_asm_pj4b.S diff -u src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.11 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.12 --- src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.11 Wed May 20 02:59:57 2015 +++ src/sys/arch/arm/arm/cpufunc_asm_pj4b.S Sat Jan 7 15:22:11 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: cpufunc_asm_pj4b.S,v 1.11 2015/05/20 02:59:57 hsuenaga Exp $ */ +/* $NetBSD: cpufunc_asm_pj4b.S,v 1.12 2017/01/07 15:22:11 kiyohara Exp $ */ /*** Copyright (C) Marvell International Ltd. and its affiliates @@ -43,7 +43,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI #define MV_FMC0_SMP (1 << 1) /* SMP/nAMP enable */ #define MV_FMC0_PARITY (1 << 2) /* Enable L1 Cache Parity */ -#define MV_FMC0_LFDIS (1 << 7) /* Disable DC Speculative linefill*/ +#define MV_FMC0_LFDIS (1 << 7) /* Disable DC Speculative linefill */ #define MV_FMC0_FW (1 << 8) /* Cache & TLB maintenance broadcast */ #define MPIDR_CPUID_MASK (0x3 << 0) /* CPUID */
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: kiyohara
Date: Tue Oct 18 13:58:53 UTC 2016
Modified Files:
src/sys/arch/arm/arm: cpufunc.c
Log Message:
Indent.
To generate a diff of this commit:
cvs rdiff -u -r1.161 -r1.162 src/sys/arch/arm/arm/cpufunc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc.c
diff -u src/sys/arch/arm/arm/cpufunc.c:1.161 src/sys/arch/arm/arm/cpufunc.c:1.162
--- src/sys/arch/arm/arm/cpufunc.c:1.161 Mon May 30 17:18:38 2016
+++ src/sys/arch/arm/arm/cpufunc.c Tue Oct 18 13:58:52 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.161 2016/05/30 17:18:38 dholland Exp $ */
+/* $NetBSD: cpufunc.c,v 1.162 2016/10/18 13:58:52 kiyohara Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.161 2016/05/30 17:18:38 dholland Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.162 2016/10/18 13:58:52 kiyohara Exp $");
#include "opt_compat_netbsd.h"
#include "opt_cpuoptions.h"
@@ -2158,13 +2158,13 @@ set_cpufuncs(void)
cputype == CPU_ID_ARM_88SV581X_V6 ||
cputype == CPU_ID_ARM_88SV581X_V7) &&
(armreg_pfr0_read() & ARM_PFR0_THUMBEE_MASK)) {
- cpufuncs = pj4bv7_cpufuncs;
+ cpufuncs = pj4bv7_cpufuncs;
#if defined(CPU_ARMV6) || defined(CPU_PRE_ARMV6)
- cpu_armv7_p = true;
+ cpu_armv7_p = true;
#endif
- get_cachetype_cp15();
- pmap_pte_init_armv7();
- return 0;
+ get_cachetype_cp15();
+ pmap_pte_init_armv7();
+ return 0;
}
#endif /* CPU_PJ4B */
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: dholland
Date: Mon May 30 17:18:38 UTC 2016
Modified Files:
src/sys/arch/arm/arm: cpufunc.c
Log Message:
PR 50669 David Binderman: remove dead code
To generate a diff of this commit:
cvs rdiff -u -r1.160 -r1.161 src/sys/arch/arm/arm/cpufunc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc.c
diff -u src/sys/arch/arm/arm/cpufunc.c:1.160 src/sys/arch/arm/arm/cpufunc.c:1.161
--- src/sys/arch/arm/arm/cpufunc.c:1.160 Sat Jan 23 21:39:17 2016
+++ src/sys/arch/arm/arm/cpufunc.c Mon May 30 17:18:38 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.160 2016/01/23 21:39:17 christos Exp $ */
+/* $NetBSD: cpufunc.c,v 1.161 2016/05/30 17:18:38 dholland Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.160 2016/01/23 21:39:17 christos Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.161 2016/05/30 17:18:38 dholland Exp $");
#include "opt_compat_netbsd.h"
#include "opt_cpuoptions.h"
@@ -2330,8 +2330,7 @@ early_abort_fixup(void *arg)
registers[base] += offset;
DFC_PRINTF(("r%d=%08x\n", base, registers[base]));
}
- } else if ((fault_instruction & 0x0e00) == 0x0c00)
- return ABORT_FIXUP_FAILED;
+ }
if ((frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE) {
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: christos
Date: Wed Mar 2 19:25:32 UTC 2016
Modified Files:
src/sys/arch/arm/arm: bootconfig.c
Log Message:
PR/50881: David Binderman: Remove redundant code.
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/arm/bootconfig.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/bootconfig.c
diff -u src/sys/arch/arm/arm/bootconfig.c:1.8 src/sys/arch/arm/arm/bootconfig.c:1.9
--- src/sys/arch/arm/arm/bootconfig.c:1.8 Mon Jan 5 19:43:21 2015
+++ src/sys/arch/arm/arm/bootconfig.c Wed Mar 2 14:25:32 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: bootconfig.c,v 1.8 2015/01/06 00:43:21 jmcneill Exp $ */
+/* $NetBSD: bootconfig.c,v 1.9 2016/03/02 19:25:32 christos Exp $ */
/*
* Copyright (c) 1994-1998 Mark Brinicombe.
@@ -40,7 +40,7 @@
#include
-__KERNEL_RCSID(0, "$NetBSD: bootconfig.c,v 1.8 2015/01/06 00:43:21 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bootconfig.c,v 1.9 2016/03/02 19:25:32 christos Exp $");
#include
@@ -89,8 +89,7 @@ get_bootconf_option(char *opts, const ch
++ptr;
if (*ptr == '=' ||
- (*ptr != '=' &&
- ((type & BOOTOPT_TYPE_MASK) == BOOTOPT_TYPE_BOOLEAN))) {
+ (type & BOOTOPT_TYPE_MASK) == BOOTOPT_TYPE_BOOLEAN) {
/* compare the option */
if (strncmp(optstart, opt, (ptr - optstart)) == 0) {
/* found */
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Mon Dec 14 15:29:45 UTC 2015
Modified Files:
src/sys/arch/arm/arm: disassem.c
Log Message:
Move mcrr and mrrc up the list so they match ahead of ldc/ldc2
To generate a diff of this commit:
cvs rdiff -u -r1.33 -r1.34 src/sys/arch/arm/arm/disassem.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/disassem.c
diff -u src/sys/arch/arm/arm/disassem.c:1.33 src/sys/arch/arm/arm/disassem.c:1.34
--- src/sys/arch/arm/arm/disassem.c:1.33 Sat May 2 16:18:49 2015
+++ src/sys/arch/arm/arm/disassem.c Mon Dec 14 15:29:45 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: disassem.c,v 1.33 2015/05/02 16:18:49 skrll Exp $ */
+/* $NetBSD: disassem.c,v 1.34 2015/12/14 15:29:45 skrll Exp $ */
/*
* Copyright (c) 1996 Mark Brinicombe.
@@ -49,7 +49,7 @@
#include
-__KERNEL_RCSID(0, "$NetBSD: disassem.c,v 1.33 2015/05/02 16:18:49 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: disassem.c,v 1.34 2015/12/14 15:29:45 skrll Exp $");
#include
@@ -151,10 +151,10 @@ static const struct arm32_insn arm32_i[]
{ 0xfe00, 0xfa00, "blx", "t" }, /* Before b and bl */
{ 0xfe100090, 0xfc00, "stc2", "L#v" },
{ 0x0e100090, 0x0c00, "stc", "L#v" },
-{ 0xfe100090, 0xfc10, "ldc2", "L#v" },
-{ 0x0e100090, 0x0c10, "ldc", "L#v" },
{ 0x0ff0, 0x0c40, "mcrr", "#&" },
{ 0x0ff0, 0x0c50, "mrrc", "#&" },
+{ 0xfe100090, 0xfc10, "ldc2", "L#v" },
+{ 0x0e100090, 0x0c10, "ldc", "L#v" },
{ 0xff10, 0xfe00, "cdp2", "#y" },
{ 0x0f10, 0x0e00, "cdp", "#y" },
{ 0xff100010, 0xfe10, "mcr2", "#z" },
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Thu Dec 10 22:04:54 UTC 2015
Modified Files:
src/sys/arch/arm/arm: cpufunc.c
Log Message:
PR port-arm/50512: Source code condition impossible
Fix condition which broke ARM1136 function selection when ARM1176 support
was added
To generate a diff of this commit:
cvs rdiff -u -r1.158 -r1.159 src/sys/arch/arm/arm/cpufunc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc.c
diff -u src/sys/arch/arm/arm/cpufunc.c:1.158 src/sys/arch/arm/arm/cpufunc.c:1.159
--- src/sys/arch/arm/arm/cpufunc.c:1.158 Wed Nov 25 08:39:45 2015
+++ src/sys/arch/arm/arm/cpufunc.c Thu Dec 10 22:04:54 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.158 2015/11/25 08:39:45 skrll Exp $ */
+/* $NetBSD: cpufunc.c,v 1.159 2015/12/10 22:04:54 skrll Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.158 2015/11/25 08:39:45 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.159 2015/12/10 22:04:54 skrll Exp $");
#include "opt_compat_netbsd.h"
#include "opt_cpuoptions.h"
@@ -1927,7 +1927,7 @@ set_cpufuncs(void)
cputype == CPU_ID_ARM1176JZS) {
cpufuncs = arm11_cpufuncs;
#if defined(CPU_ARM1136)
- if (cputype == CPU_ID_ARM1136JS &&
+ if (cputype == CPU_ID_ARM1136JS ||
cputype == CPU_ID_ARM1136JSR1) {
cpufuncs = arm1136_cpufuncs;
if (cputype == CPU_ID_ARM1136JS)
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: skrll Date: Sun Jun 7 12:01:41 UTC 2015 Modified Files: src/sys/arch/arm/arm: cpufunc_asm_armv7.S Log Message: Dont use magic number. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.24 -r1.25 src/sys/arch/arm/arm/cpufunc_asm_armv7.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/cpufunc_asm_armv7.S diff -u src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.24 src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.25 --- src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.24 Sat May 30 21:25:22 2015 +++ src/sys/arch/arm/arm/cpufunc_asm_armv7.S Sun Jun 7 12:01:41 2015 @@ -45,12 +45,31 @@ ENTRY(armv7_wait) bx lr END(armv7_wait) + +#define TTBR_C (1 0) +#define TTBR_S (1 1) +#define TTBR_IMP (1 2) +#define TTBR_RGN_MASK (3 3) +#define TTBR_RGN_NC (0 3) +#define TTBR_RGN_WBWA (1 3) +#define TTBR_RGN_WT (2 3) +#define TTBR_RGN_WBNWA (3 3) +#define TTBR_NOS (1 5) +#define TTBR_IRGN_MASK ((1 6) | (1 0)) +#define TTBR_IRGN_NC ((0 6) | (0 0)) +#define TTBR_IRGN_WBWA ((0 6) | (1 0)) +#define TTBR_IRGN_WT ((1 6) | (0 0)) +#define TTBR_IRGN_WBNWA ((1 6) | (1 0)) + +#define TTBR_UPATTR (TTBR_S | TTBR_RGN_WBNWA | TTBR_C) +#define TTBR_MPATTR (TTBR_S | TTBR_RGN_WBNWA /* | TTBR_NOS */ | TTBR_IRGN_WBNWA) + ENTRY(armv7_context_switch) dsb@ data synchronization barrier mrc p15, 0, ip, c0, c0, 5 @ get MPIDR cmp ip, #0 - orrlt r0, r0, #0x5b @ MP, cachable (Normal WB) - orrge r0, r0, #0x1b @ Non-MP, cacheable, normal WB + orrlt r0, r0, #TTBR_MPATTR @ MP, cachable (Normal WB) + orrge r0, r0, #TTBR_UPATTR @ Non-MP, cacheable, normal WB mcr p15, 0, r0, c2, c0, 0 @ set the new TTBR 0 #ifdef ARM_MMU_EXTENDED cmp r1, #0 @@ -126,8 +145,8 @@ END(armv7_tlb_flushID) ENTRY_NP(armv7_setttb) mrc p15, 0, ip, c0, c0, 5 @ get MPIDR cmp ip, #0 - orrlt r0, r0, #0x5b @ MP, cachable (Normal WB) - orrge r0, r0, #0x1b @ Non-MP, cacheable, normal WB + orrlt r0, r0, #TTBR_MPATTR @ MP, cachable (Normal WB) + orrge r0, r0, #TTBR_UPATTR @ Non-MP, cacheable, normal WB mcr p15, 0, r0, c2, c0, 0 @ load new TTBR 0 #ifdef ARM_MMU_EXTENDED cmp r1, #0
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: hsuenaga
Date: Wed Jun 3 02:30:11 UTC 2015
Modified Files:
src/sys/arch/arm/arm: cpufunc.c
Log Message:
initialize sdcache operations for PJ4B.
otherwise the kernel crashes without 'options L2CACHE_ENABLE.'
To generate a diff of this commit:
cvs rdiff -u -r1.154 -r1.155 src/sys/arch/arm/arm/cpufunc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc.c
diff -u src/sys/arch/arm/arm/cpufunc.c:1.154 src/sys/arch/arm/arm/cpufunc.c:1.155
--- src/sys/arch/arm/arm/cpufunc.c:1.154 Thu May 14 05:39:32 2015
+++ src/sys/arch/arm/arm/cpufunc.c Wed Jun 3 02:30:11 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.154 2015/05/14 05:39:32 hsuenaga Exp $ */
+/* $NetBSD: cpufunc.c,v 1.155 2015/06/03 02:30:11 hsuenaga Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: cpufunc.c,v 1.154 2015/05/14 05:39:32 hsuenaga Exp $);
+__KERNEL_RCSID(0, $NetBSD: cpufunc.c,v 1.155 2015/06/03 02:30:11 hsuenaga Exp $);
#include opt_compat_netbsd.h
#include opt_cpuoptions.h
@@ -1380,6 +1380,10 @@ struct cpu_functions pj4bv7_cpufuncs = {
.cf_dcache_inv_range = armv7_dcache_inv_range,
.cf_dcache_wb_range = armv7_dcache_wb_range,
+ .cf_sdcache_wbinv_range = (void *)cpufunc_nullop,
+ .cf_sdcache_inv_range = (void *)cpufunc_nullop,
+ .cf_sdcache_wb_range = (void *)cpufunc_nullop,
+
.cf_idcache_wbinv_all = armv7_idcache_wbinv_all,
.cf_idcache_wbinv_range = armv7_idcache_wbinv_range,
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: skrll Date: Sat May 30 21:23:17 UTC 2015 Modified Files: src/sys/arch/arm/arm: cpufunc_asm_armv7.S Log Message: Provide a armv7_dcache_l1inv_all To generate a diff of this commit: cvs rdiff -u -r1.22 -r1.23 src/sys/arch/arm/arm/cpufunc_asm_armv7.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/cpufunc_asm_armv7.S diff -u src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.22 src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.23 --- src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.22 Sat May 16 07:22:37 2015 +++ src/sys/arch/arm/arm/cpufunc_asm_armv7.S Sat May 30 21:23:17 2015 @@ -339,6 +339,53 @@ ENTRY_NP(armv7_icache_inv_all) bx lr @ return END(armv7_icache_inv_all) +/* * LINTSTUB: void armv7_dcache_l1inv_all(void); */ +ENTRY_NP(armv7_cache_l1inv_all) + mrc p15, 1, r0, c0, c0, 1 @ read CLIDR + and r0, r0, #0x7 @ check L1 + bxeq lr @ return if no L1 cache + mov r3, #0 @ start with L1 + mcr p15, 2, r3, c0, c0, 0 @ select cache level + isb + mrc p15, 1, r0, c0, c0, 0 @ read CCSIDR + + ubfx ip, r0, #0, #3 @ get linesize from CCSIDR + add ip, ip, #4 @ apply bias + ubfx r2, r0, #13, #15 @ get numsets - 1 from CCSIDR + lsl r2, r2, ip @ shift to set position + orr r3, r3, r2 @ merge set into way/set/level + mov r1, #1 + lsl r1, r1, ip @ r1 = set decr + + ubfx ip, r0, #3, #10 @ get numways - 1 from [to be discarded] CCSIDR + clz r2, ip @ number of bits to MSB of way + lsl ip, ip, r2 @ shift by that into way position + mov r0, #1 @ + lsl r2, r0, r2 @ r2 now contains the way decr + mov r0, r3 @ get sets/level (no way yet) + orr r3, r3, ip @ merge way into way/set/level + bfc r0, #0, #4 @ clear low 4 bits (level) to get numset - 1 + sub r2, r2, r0 @ subtract from way decr + + /* r3 = ways/sets/level, r2 = way decr, r1 = set decr, r0 and ip are free */ +1: mcr p15, 0, r3, c7, c6, 2 @ invalidate line + cmp r3, #15 @ are we done with this level (way/set == 0) + bls .Ldone_l1inv @ yes, we've finished + ubfx r0, r3, #4, #18 @ extract set bits + cmp r0, #0 @ compare + subne r3, r3, r1 @ non-zero?, decrement set # + subeq r3, r3, r2 @ zero?, decrement way # and restore set count + b 1b + +.Ldone_l1inv: + dsb + mov r0, #0 @ default back to cache level 0 + mcr p15, 2, r0, c0, c0, 0 @ select cache level + dsb + isb + bx lr +END(armv7_dcache_l1inv_all) + /* * LINTSTUB: void armv7_dcache_inv_all(void); */ ENTRY_NP(armv7_dcache_inv_all) mrc p15, 1, r0, c0, c0, 1 @ read CLIDR
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: skrll Date: Sat May 30 21:25:22 UTC 2015 Modified Files: src/sys/arch/arm/arm: cpufunc_asm_armv7.S Log Message: Typo in previous To generate a diff of this commit: cvs rdiff -u -r1.23 -r1.24 src/sys/arch/arm/arm/cpufunc_asm_armv7.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/cpufunc_asm_armv7.S diff -u src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.23 src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.24 --- src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.23 Sat May 30 21:23:17 2015 +++ src/sys/arch/arm/arm/cpufunc_asm_armv7.S Sat May 30 21:25:22 2015 @@ -340,7 +340,7 @@ ENTRY_NP(armv7_icache_inv_all) END(armv7_icache_inv_all) /* * LINTSTUB: void armv7_dcache_l1inv_all(void); */ -ENTRY_NP(armv7_cache_l1inv_all) +ENTRY_NP(armv7_dcache_l1inv_all) mrc p15, 1, r0, c0, c0, 1 @ read CLIDR and r0, r0, #0x7 @ check L1 bxeq lr @ return if no L1 cache
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: skrll Date: Sat May 16 07:22:37 UTC 2015 Modified Files: src/sys/arch/arm/arm: cpufunc_asm_armv7.S Log Message: Add MULTIPROCESSOR tlb flushes to armv7_tlb_flushID. Also, invalidate the branch predictor. This function is only used by db_write_bytes and kobj_machdep To generate a diff of this commit: cvs rdiff -u -r1.21 -r1.22 src/sys/arch/arm/arm/cpufunc_asm_armv7.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/cpufunc_asm_armv7.S diff -u src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.21 src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.22 --- src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.21 Sun Nov 9 09:21:57 2014 +++ src/sys/arch/arm/arm/cpufunc_asm_armv7.S Sat May 16 07:22:37 2015 @@ -108,8 +108,15 @@ END(armv7_tlb_flushD) STRONG_ALIAS(armv7_tlb_flushI, armv7_tlb_flushID) ENTRY(armv7_tlb_flushID) + dsb mov r0, #0 +#ifdef MULTIPROCESSOR + mcr p15, 0, r0, c8, c3, 0 @ flush entire I+D tlb, IS + mcr p15, 0, r0, c7, c1, 6 @ branch predictor invalidate, IS +#else mcr p15, 0, r0, c8, c7, 0 @ flush entire I+D tlb + mcr p15, 0, r0, c7, c5, 6 @ branch predictor invalidate +#endif dsb@ data synchronization barrier isb bx lr
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: matt Date: Thu May 14 17:15:56 UTC 2015 Modified Files: src/sys/arch/arm/arm: cpufunc_asm_pj4b.S Log Message: Use movw/movw To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/cpufunc_asm_pj4b.S diff -u src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.8 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.9 --- src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.8 Thu May 14 05:39:32 2015 +++ src/sys/arch/arm/arm/cpufunc_asm_pj4b.S Thu May 14 17:15:56 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: cpufunc_asm_pj4b.S,v 1.8 2015/05/14 05:39:32 hsuenaga Exp $ */ +/* $NetBSD: cpufunc_asm_pj4b.S,v 1.9 2015/05/14 17:15:56 matt Exp $ */ /*** Copyright (C) Marvell International Ltd. and its affiliates @@ -41,9 +41,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI #include arm/asm.h #include arm/locore.h -.Lpj4b_l2_barrier_reg: - .word _C_LABEL(armadaxp_l2_barrier_reg) - /* LINTSTUB: void pj4b_cpu_sleep(int); */ ENTRY(pj4b_cpu_sleep) dsb @@ -92,7 +89,8 @@ END(pj4b_config) /* LINTSTUB: void pj4b_io_coherency_barrier(vaddr_t, paddr_t, vsize_t); */ ENTRY_NP(pj4b_io_coherency_barrier) - ldr r0, .Lpj4b_l2_barrier_reg + movw r0, #:lower16:_C_LABEL(armadaxp_l2_barrier_reg) + movt r0, #:upper16:_C_LABEL(armadaxp_l2_barrier_reg) ldr r0, [r0] @ MVSOC_MLMB_CIB_BARRIER mov r1, #1 @ MVSOC_MLMB_CIB_BARRIER_TRIGGER str r1, [r0]
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Sat May 2 16:20:41 UTC 2015
Modified Files:
src/sys/arch/arm/arm: arm_machdep.c
Log Message:
Remove unintended commit
To generate a diff of this commit:
cvs rdiff -u -r1.48 -r1.49 src/sys/arch/arm/arm/arm_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/arm_machdep.c
diff -u src/sys/arch/arm/arm/arm_machdep.c:1.48 src/sys/arch/arm/arm/arm_machdep.c:1.49
--- src/sys/arch/arm/arm/arm_machdep.c:1.48 Sat May 2 16:18:49 2015
+++ src/sys/arch/arm/arm/arm_machdep.c Sat May 2 16:20:41 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: arm_machdep.c,v 1.48 2015/05/02 16:18:49 skrll Exp $ */
+/* $NetBSD: arm_machdep.c,v 1.49 2015/05/02 16:20:41 skrll Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -80,7 +80,7 @@
#include sys/param.h
-__KERNEL_RCSID(0, $NetBSD: arm_machdep.c,v 1.48 2015/05/02 16:18:49 skrll Exp $);
+__KERNEL_RCSID(0, $NetBSD: arm_machdep.c,v 1.49 2015/05/02 16:20:41 skrll Exp $);
#include sys/exec.h
#include sys/proc.h
@@ -187,7 +187,7 @@ setregs(struct lwp *l, struct exec_packa
tf-tf_spsr = PSR_USR32_MODE | (CPU_IS_ARMV7_P() ? PSR_E_BIT : 0);
#else
tf-tf_spsr = PSR_USR32_MODE;
-#endif /* __ARMEB__ */
+#endif /* __ARMEB__ */
#ifdef THUMB_CODE
if (pack-ep_entry 1)
@@ -213,7 +213,7 @@ setregs(struct lwp *l, struct exec_packa
void
startlwp(void *arg)
{
- ucontext_t *uc = (ucontext_t *)arg;
+ ucontext_t *uc = (ucontext_t *)arg;
lwp_t *l = curlwp;
int error __diagused;
@@ -243,11 +243,9 @@ cpu_need_resched(struct cpu_info *ci, in
*/
return;
}
-#if 0
- /* XXXNH??? */
if (ci-ci_want_resched !immed)
return;
-#endif
+
if (l == ci-ci_data.cpu_idlelwp) {
#ifdef MULTIPROCESSOR
/*
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Sat May 2 16:18:49 UTC 2015
Modified Files:
src/sys/arch/arm/arm: arm_machdep.c disassem.c
Log Message:
Move /* A5.2.10 Synchronisation primitives */ block earlier so it
matches correctly
To generate a diff of this commit:
cvs rdiff -u -r1.47 -r1.48 src/sys/arch/arm/arm/arm_machdep.c
cvs rdiff -u -r1.32 -r1.33 src/sys/arch/arm/arm/disassem.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/arm_machdep.c
diff -u src/sys/arch/arm/arm/arm_machdep.c:1.47 src/sys/arch/arm/arm/arm_machdep.c:1.48
--- src/sys/arch/arm/arm/arm_machdep.c:1.47 Wed Apr 15 21:26:48 2015
+++ src/sys/arch/arm/arm/arm_machdep.c Sat May 2 16:18:49 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: arm_machdep.c,v 1.47 2015/04/15 21:26:48 matt Exp $ */
+/* $NetBSD: arm_machdep.c,v 1.48 2015/05/02 16:18:49 skrll Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -80,7 +80,7 @@
#include sys/param.h
-__KERNEL_RCSID(0, $NetBSD: arm_machdep.c,v 1.47 2015/04/15 21:26:48 matt Exp $);
+__KERNEL_RCSID(0, $NetBSD: arm_machdep.c,v 1.48 2015/05/02 16:18:49 skrll Exp $);
#include sys/exec.h
#include sys/proc.h
@@ -187,7 +187,7 @@ setregs(struct lwp *l, struct exec_packa
tf-tf_spsr = PSR_USR32_MODE | (CPU_IS_ARMV7_P() ? PSR_E_BIT : 0);
#else
tf-tf_spsr = PSR_USR32_MODE;
-#endif /* __ARMEB__ */
+#endif /* __ARMEB__ */
#ifdef THUMB_CODE
if (pack-ep_entry 1)
@@ -213,7 +213,7 @@ setregs(struct lwp *l, struct exec_packa
void
startlwp(void *arg)
{
- ucontext_t *uc = (ucontext_t *)arg;
+ ucontext_t *uc = (ucontext_t *)arg;
lwp_t *l = curlwp;
int error __diagused;
@@ -243,9 +243,11 @@ cpu_need_resched(struct cpu_info *ci, in
*/
return;
}
+#if 0
+ /* XXXNH??? */
if (ci-ci_want_resched !immed)
return;
-
+#endif
if (l == ci-ci_data.cpu_idlelwp) {
#ifdef MULTIPROCESSOR
/*
Index: src/sys/arch/arm/arm/disassem.c
diff -u src/sys/arch/arm/arm/disassem.c:1.32 src/sys/arch/arm/arm/disassem.c:1.33
--- src/sys/arch/arm/arm/disassem.c:1.32 Tue Mar 31 16:15:07 2015
+++ src/sys/arch/arm/arm/disassem.c Sat May 2 16:18:49 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: disassem.c,v 1.32 2015/03/31 16:15:07 skrll Exp $ */
+/* $NetBSD: disassem.c,v 1.33 2015/05/02 16:18:49 skrll Exp $ */
/*
* Copyright (c) 1996 Mark Brinicombe.
@@ -49,7 +49,7 @@
#include sys/param.h
-__KERNEL_RCSID(0, $NetBSD: disassem.c,v 1.32 2015/03/31 16:15:07 skrll Exp $);
+__KERNEL_RCSID(0, $NetBSD: disassem.c,v 1.33 2015/05/02 16:18:49 skrll Exp $);
#include sys/systm.h
@@ -247,6 +247,18 @@ static const struct arm32_insn arm32_i[]
{ 0x0ff0, 0x0300, movw, dZ },
{ 0x0ff0, 0x0340, movt, dZ },
+/* A5.2.10 Synchronisation primitives */
+{ 0x0ff00ff0, 0x0190, swp, dmo },
+{ 0x0ff00ff0, 0x01400090, swpb, dmo },
+{ 0x0ff00fff, 0x01900f9f, ldrex, da },
+{ 0x0ff00fff, 0x01b00f9f, ldrexd, da },
+{ 0x0ff00fff, 0x01d00f9f, ldrexb, da },
+{ 0x0ff00fff, 0x01f00f9f, ldrexh, da },
+{ 0x0ff00ff0, 0x01800f90, strex, dma },
+{ 0x0ff00ff0, 0x01a00f90, strexd, dma },
+{ 0x0ff00ff0, 0x01c00f90, strexb, dma },
+{ 0x0ff00ff0, 0x01e00f90, strexh, dma },
+
/* A5.2 non-exceptions */
/* A5.2.1, A5.2.2, and A5.2.3 Data-processing */
@@ -275,18 +287,6 @@ static const struct arm32_insn arm32_i[]
{ 0x0fe000f0, 0x00a00090, umlal, Sdnms },
{ 0x0fe000f0, 0x00e00090, smlal, Sdnms },
-/* A5.2.10 Synchronisation primitives */
-{ 0x0ff00ff0, 0x0190, swp, dmo },
-{ 0x0ff00ff0, 0x01400090, swpb, dmo },
-{ 0x0ff00fff, 0x01900f9f, ldrex, da },
-{ 0x0ff00fff, 0x01b00f9f, ldrexd, da },
-{ 0x0ff00fff, 0x01d00f9f, ldrexb, da },
-{ 0x0ff00fff, 0x01f00f9f, ldrexh, da },
-{ 0x0ff00ff0, 0x01800f90, strex, dma },
-{ 0x0ff00ff0, 0x01a00f90, strexd, dma },
-{ 0x0ff00ff0, 0x01c00f90, strexb, dma },
-{ 0x0ff00ff0, 0x01e00f90, strexh, dma },
-
/* */
{ 0x0ff08f10, 0x0e000100, adf, PRfgh },
{ 0x0ff08f10, 0x0e100100, muf, PRfgh },
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: hsuenaga
Date: Fri Apr 17 13:39:02 UTC 2015
Modified Files:
src/sys/arch/arm/arm: cpufunc.c
Log Message:
don't call L2 maintance function if L2 cache is disabled.
To generate a diff of this commit:
cvs rdiff -u -r1.152 -r1.153 src/sys/arch/arm/arm/cpufunc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc.c
diff -u src/sys/arch/arm/arm/cpufunc.c:1.152 src/sys/arch/arm/arm/cpufunc.c:1.153
--- src/sys/arch/arm/arm/cpufunc.c:1.152 Wed Apr 15 10:52:18 2015
+++ src/sys/arch/arm/arm/cpufunc.c Fri Apr 17 13:39:01 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.152 2015/04/15 10:52:18 hsuenaga Exp $ */
+/* $NetBSD: cpufunc.c,v 1.153 2015/04/17 13:39:01 hsuenaga Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: cpufunc.c,v 1.152 2015/04/15 10:52:18 hsuenaga Exp $);
+__KERNEL_RCSID(0, $NetBSD: cpufunc.c,v 1.153 2015/04/17 13:39:01 hsuenaga Exp $);
#include opt_compat_netbsd.h
#include opt_cpuoptions.h
@@ -1381,7 +1381,9 @@ struct cpu_functions pj4bv7_cpufuncs = {
.cf_dcache_inv_range = armv7_dcache_inv_range,
.cf_dcache_wb_range = armv7_dcache_wb_range,
-#if !defined(AURORA_IO_CACHE_COHERENCY) defined(ARMADAXP)
+#if defined(L2CACHE_ENABLE) \
+!defined(AURORA_IO_CACHE_COHERENCY) \
+defined(ARMADAXP)
.cf_sdcache_wbinv_range = armadaxp_sdcache_wbinv_range,
.cf_sdcache_inv_range = armadaxp_sdcache_inv_range,
.cf_sdcache_wb_range = armadaxp_sdcache_wb_range,
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: matt
Date: Wed Apr 15 13:22:50 UTC 2015
Modified Files:
src/sys/arch/arm/arm: undefined.c
Log Message:
Remove FAST_FPE code
To generate a diff of this commit:
cvs rdiff -u -r1.55 -r1.56 src/sys/arch/arm/arm/undefined.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/undefined.c
diff -u src/sys/arch/arm/arm/undefined.c:1.55 src/sys/arch/arm/arm/undefined.c:1.56
--- src/sys/arch/arm/arm/undefined.c:1.55 Tue Oct 14 22:23:22 2014
+++ src/sys/arch/arm/arm/undefined.c Wed Apr 15 13:22:50 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: undefined.c,v 1.55 2014/10/14 22:23:22 skrll Exp $ */
+/* $NetBSD: undefined.c,v 1.56 2015/04/15 13:22:50 matt Exp $ */
/*
* Copyright (c) 2001 Ben Harris.
@@ -55,7 +55,7 @@
#include sys/kgdb.h
#endif
-__KERNEL_RCSID(0, $NetBSD: undefined.c,v 1.55 2014/10/14 22:23:22 skrll Exp $);
+__KERNEL_RCSID(0, $NetBSD: undefined.c,v 1.56 2015/04/15 13:22:50 matt Exp $);
#include sys/kmem.h
#include sys/queue.h
@@ -475,24 +475,5 @@ undefinedinstruction(trapframe_t *tf)
if ((fault_code FAULT_USER) == 0)
return;
-#ifdef FAST_FPE
- /* Optimised exit code */
- {
- /*
- * Check for reschedule request, at the moment there is only
- * 1 ast so this code should always be run
- */
- if (curcpu()-ci_want_resched) {
- /*
- * We are being preempted.
- */
- preempt();
- }
-
- /* Invoke MI userret code */
- mi_userret(l);
- }
-#else
userret(l);
-#endif
}
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: matt
Date: Wed Apr 8 16:37:32 UTC 2015
Modified Files:
src/sys/arch/arm/arm: arm_machdep.c
Log Message:
Small tweaks for preemption.
To generate a diff of this commit:
cvs rdiff -u -r1.44 -r1.45 src/sys/arch/arm/arm/arm_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/arm_machdep.c
diff -u src/sys/arch/arm/arm/arm_machdep.c:1.44 src/sys/arch/arm/arm/arm_machdep.c:1.45
--- src/sys/arch/arm/arm/arm_machdep.c:1.44 Wed Apr 8 07:29:44 2015
+++ src/sys/arch/arm/arm/arm_machdep.c Wed Apr 8 16:37:32 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: arm_machdep.c,v 1.44 2015/04/08 07:29:44 matt Exp $ */
+/* $NetBSD: arm_machdep.c,v 1.45 2015/04/08 16:37:32 matt Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -80,7 +80,7 @@
#include sys/param.h
-__KERNEL_RCSID(0, $NetBSD: arm_machdep.c,v 1.44 2015/04/08 07:29:44 matt Exp $);
+__KERNEL_RCSID(0, $NetBSD: arm_machdep.c,v 1.45 2015/04/08 16:37:32 matt Exp $);
#include sys/exec.h
#include sys/proc.h
@@ -266,7 +266,7 @@ cpu_need_resched(struct cpu_info *ci, in
#ifdef __HAVE_PREEMPTION
atomic_or_uint(l-l_dopreempt, DOPREEMPT_ACTIVE);
if (ci == cur_ci) {
- softint_trigger(SOFTINT_KPREEMPT);
+ ci-ci_astpending |= 2;
} else {
ipi = IPI_KPREEMPT;
goto send_ipi;
@@ -274,7 +274,7 @@ cpu_need_resched(struct cpu_info *ci, in
#endif /* __HAVE_PREEMPTION */
return;
}
- ci-ci_astpending = 1;
+ ci-ci_astpending |= 1;
#ifdef MULTIPROCESSOR
if (ci == curcpu() || !immed)
return;
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: skrll
Date: Tue Mar 31 16:15:07 UTC 2015
Modified Files:
src/sys/arch/arm/arm: disassem.c
Log Message:
More instructions. Lots left to do.
To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/arm/arm/disassem.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/disassem.c
diff -u src/sys/arch/arm/arm/disassem.c:1.31 src/sys/arch/arm/arm/disassem.c:1.32
--- src/sys/arch/arm/arm/disassem.c:1.31 Sun Jan 18 18:23:25 2015
+++ src/sys/arch/arm/arm/disassem.c Tue Mar 31 16:15:07 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: disassem.c,v 1.31 2015/01/18 18:23:25 skrll Exp $ */
+/* $NetBSD: disassem.c,v 1.32 2015/03/31 16:15:07 skrll Exp $ */
/*
* Copyright (c) 1996 Mark Brinicombe.
@@ -49,7 +49,7 @@
#include sys/param.h
-__KERNEL_RCSID(0, $NetBSD: disassem.c,v 1.31 2015/01/18 18:23:25 skrll Exp $);
+__KERNEL_RCSID(0, $NetBSD: disassem.c,v 1.32 2015/03/31 16:15:07 skrll Exp $);
#include sys/systm.h
@@ -71,16 +71,21 @@ __KERNEL_RCSID(0, $NetBSD: disassem.c,v
* the instruction. The only exception is the writeback flag which
* follows a operand.
*
- *
+ * !c - cps flags and mode
+ * !d - debug option (bit 0-3)
+ * !l - dmb/dsb limitation
+ * !m - mode
* 2 - print Operand 2 of a data processing instruction
* a - address operand of ldr/str instruction
* b - branch address
* c - comment field bits(0-23)
* d - destination register (bits 12-15)
- * e - address operand of ldrh/strh instruction
+ * e - address operand of ldrx/strx instruction
* f - 1st fp operand (register) (bits 12-14)
* g - 2nd fp operand (register) (bits 16-18)
* h - 3rd fp operand (register/immediate) (bits 0-4)
+ * i - lsb operand (bits 7-11)
+ * j - msb operand (bits 6,7,12-14)
* k - breakpoint comment (bits 0-3, 8-19)
* l - register list for ldm/stm instruction
* m - m register (bits 0-3)
@@ -88,6 +93,7 @@ __KERNEL_RCSID(0, $NetBSD: disassem.c,v
* o - indirect register rn (bits 16-19) (used by swap)
* p - saved or current status register
* q - neon N register (7, 19-16)
+ * r - width minus 1 (bits 16-20)
* s - s register (bits 8-11)
* t - thumb branch address (bits 24, 0-23)
* u - neon M register (5, 3-0)
@@ -96,6 +102,7 @@ __KERNEL_RCSID(0, $NetBSD: disassem.c,v
* x - instruction in hex
* y - co-processor data processing registers
* z - co-processor register transfer registers
+ * C - cps effect
* D - destination-is-r15 (P) flag on TST, TEQ, CMP, CMN
* F - PSR transfer fields
* I - NEON operand size
@@ -121,60 +128,128 @@ struct arm32_insn {
};
static const struct arm32_insn arm32_i[] = {
-{ 0x0fff, 0x0ff0, imb, c }, /* Before swi */
-{ 0x0fff, 0x0ff1, imbrange, c }, /* Before swi */
-{ 0x0fff, 0x0320f003, yield, }, /* Before swi */
-{ 0x0fff, 0x0320f002, wfe, }, /* Before swi */
-{ 0x0fff, 0x0320f003, wfi, }, /* Before swi */
-{ 0x0f00, 0x0f00, swi, c },
+/* A5.7 Unconditional instructions */
+/*
+ * A5.7.1 Memory hints, Advanced SIMD instructions, and
+ * miscellaneous instructions
+ */
+{ 0xfff10020, 0xf100, cps, C!c },
+{ 0xfff100f0, 0xf101, setend\tle, },
+{ 0xfff102f0, 0xf1010200, setend\tbe, },
+/* pli */
+/* pld */
+{ 0x, 0xf57ff01f, clrex, },
+{ 0xfff0, 0xf57ff040, dsb,!l },
+{ 0xfff0, 0xf57ff050, dmb,!l },
+{ 0xfff0, 0xf57ff060, isb, },
+/* pli */
+/* pld */
+
+//{ 0x0e10, 0x0800, stm, XnWl },
+{ 0xfe5fffe0, 0xf84d0500, srs, XnW!m },
+{ 0xfe50, 0xf8100a00, rfe, XnW },
{ 0xfe00, 0xfa00, blx, t }, /* Before b and bl */
-{ 0x0f00, 0x0a00, b, b },
-{ 0x0f00, 0x0b00, bl, b },
-{ 0x0fe000f0, 0x0090, mul, Snms },
-{ 0x0fe000f0, 0x00200090, mla, Snmsd },
-{ 0x0fe000f0, 0x00800090, umull, Sdnms },
-{ 0x0fe000f0, 0x00c00090, smull, Sdnms },
-{ 0x0fe000f0, 0x00a00090, umlal, Sdnms },
-{ 0x0fe000f0, 0x00e00090, smlal, Sdnms },
+{ 0xfe100090, 0xfc00, stc2, L#v },
+{ 0x0e100090, 0x0c00, stc, L#v },
+{ 0xfe100090, 0xfc10, ldc2, L#v },
+{ 0x0e100090, 0x0c10, ldc, L#v },
+{ 0x0ff0, 0x0c40, mcrr, # },
+{ 0x0ff0, 0x0c50, mrrc, # },
+{ 0xff10, 0xfe00, cdp2, #y },
+{ 0x0f10, 0x0e00, cdp, #y },
+{ 0xff100010, 0xfe10, mcr2, #z },
+{ 0x0f100010, 0x0e10, mcr, #z },
+{ 0xff100010, 0xfe100010, mrc2, #z },
+{ 0x0f100010, 0x0e100010, mrc, #z },
+
+/* A5.4 Media instructions */
+{ 0x0fe00070, 0x07c00050, sbfx, dmir },
+{ 0x0fe0007f, 0x07c0001f, bfc,dij },
+{ 0x0fe00070, 0x07c00010, bfi,dmij },
+{ 0x0fe00070, 0x07e00050, ubfx, dmir },
+{ 0xfff000f0, 0xe7f0, und, x }, /* Special immediate? */
+
+{ 0x0610, 0x0610, und, x }, /* Remove
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: hsuenaga Date: Thu Mar 26 08:50:42 UTC 2015 Modified Files: src/sys/arch/arm/arm: cpufunc_asm_pj4b.S Log Message: set ttbr0/1 using correct register(r2). To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/cpufunc_asm_pj4b.S diff -u src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.5 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.6 --- src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.5 Wed Oct 29 16:22:31 2014 +++ src/sys/arch/arm/arm/cpufunc_asm_pj4b.S Thu Mar 26 08:50:42 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: cpufunc_asm_pj4b.S,v 1.5 2014/10/29 16:22:31 skrll Exp $ */ +/* $NetBSD: cpufunc_asm_pj4b.S,v 1.6 2015/03/26 08:50:42 hsuenaga Exp $ */ /*** Copyright (C) Marvell International Ltd. and its affiliates @@ -58,10 +58,10 @@ ENTRY(pj4b_setttb) #else bic r2, r0, #0x18 #endif - mcr p15, 0, r0, c2, c0, 0 /* load TTBR0 */ + mcr p15, 0, r2, c2, c0, 0 /* load TTBR0 */ #ifdef ARM_MMU_EXTENDED cmp r1, #0 - mcreq p15, 0, r0, c2, c0, 1 /* load TTBR1 */ + mcreq p15, 0, r2, c2, c0, 1 /* load TTBR1 */ #else mov r0, #0 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: christos
Date: Sat Mar 7 18:52:47 UTC 2015
Modified Files:
src/sys/arch/arm/arm: linux_syscall.c
Log Message:
adjust to new trace_{enter,exit}
To generate a diff of this commit:
cvs rdiff -u -r1.26 -r1.27 src/sys/arch/arm/arm/linux_syscall.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/linux_syscall.c
diff -u src/sys/arch/arm/arm/linux_syscall.c:1.26 src/sys/arch/arm/arm/linux_syscall.c:1.27
--- src/sys/arch/arm/arm/linux_syscall.c:1.26 Thu Apr 3 12:22:20 2014
+++ src/sys/arch/arm/arm/linux_syscall.c Sat Mar 7 13:52:46 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: linux_syscall.c,v 1.26 2014/04/03 16:22:20 rjs Exp $ */
+/* $NetBSD: linux_syscall.c,v 1.27 2015/03/07 18:52:46 christos Exp $ */
/*-
* Copyright (c) 2000, 2003 The NetBSD Foundation, Inc.
@@ -69,7 +69,7 @@
#include sys/param.h
-__KERNEL_RCSID(0, $NetBSD: linux_syscall.c,v 1.26 2014/04/03 16:22:20 rjs Exp $);
+__KERNEL_RCSID(0, $NetBSD: linux_syscall.c,v 1.27 2015/03/07 18:52:46 christos Exp $);
#include sys/device.h
#include sys/errno.h
@@ -182,7 +182,7 @@ linux_syscall_fancy(trapframe_t *frame,
args = frame-tf_r0;
callp = p-p_emul-e_sysent + code;
- if ((error = trace_enter(code, args, callp-sy_narg)) != 0)
+ if ((error = trace_enter(code, callp, args)) != 0)
goto out;
rval[0] = 0;
@@ -209,7 +209,7 @@ out:
break;
}
- trace_exit(code, rval, error);
+ trace_exit(code, callp, args, rval, error);
userret(l);
}
