CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Wed Jun 23 15:11:40 UTC 2021

Modified Files:
src/sys/arch/mips/include: vmparam.h

Log Message:
Remove an unused #define.


To generate a diff of this commit:
cvs rdiff -u -r1.65 -r1.66 src/sys/arch/mips/include/vmparam.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/vmparam.h
diff -u src/sys/arch/mips/include/vmparam.h:1.65 src/sys/arch/mips/include/vmparam.h:1.66
--- src/sys/arch/mips/include/vmparam.h:1.65	Fri Feb 26 02:18:29 2021
+++ src/sys/arch/mips/include/vmparam.h	Wed Jun 23 15:11:40 2021
@@ -1,4 +1,4 @@
-/*	$NetBSD: vmparam.h,v 1.65 2021/02/26 02:18:29 simonb Exp $	*/
+/*	$NetBSD: vmparam.h,v 1.66 2021/06/23 15:11:40 simonb Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -198,7 +198,6 @@
 
 /* VM_PHYSSEG_MAX defined by platform-dependent code. */
 #define	VM_PHYSSEG_STRAT	VM_PSTRAT_BSEARCH
-#define	VM_PHYSSEG_NOADD	/* can add RAM after vm_mem_init */
 
 #ifndef VM_NFREELIST
 #define	VM_NFREELIST		16	/* 16 distinct memory segments */

CVS commit: src/sys/arch/mips/include

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Tue May 18 06:38:24 UTC 2021

Modified Files:
src/sys/arch/mips/include: db_machdep.h

Log Message:
Remove argument names from function declaration prototypes.


To generate a diff of this commit:
cvs rdiff -u -r1.37 -r1.38 src/sys/arch/mips/include/db_machdep.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/db_machdep.h
diff -u src/sys/arch/mips/include/db_machdep.h:1.37 src/sys/arch/mips/include/db_machdep.h:1.38
--- src/sys/arch/mips/include/db_machdep.h:1.37	Mon Mar 29 03:09:41 2021
+++ src/sys/arch/mips/include/db_machdep.h	Tue May 18 06:38:24 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: db_machdep.h,v 1.37 2021/03/29 03:09:41 simonb Exp $ */
+/* $NetBSD: db_machdep.h,v 1.38 2021/05/18 06:38:24 skrll Exp $ */
 
 /*
  * Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
@@ -91,7 +91,7 @@ db_addr_t	db_disasm_insn(int insn, db_ad
  * Entrypoints to DDB for kernel, keyboard drivers, init hook
  */
 void 	kdb_kbd_trap(db_regs_t *);
-int 	kdb_trap(int type, struct reg *);
+int 	kdb_trap(int, struct reg *);
 
 static inline void
 db_set_ddb_regs(int type, struct reg *regs)
@@ -103,7 +103,7 @@ db_set_ddb_regs(int type, struct reg *re
  * Helper functions for fetching 32-bit and 64-bit kernel memory.
  */
 bool		kdbpeek(vaddr_t, unsigned *);
-mips_reg_t	kdbrpeek(vaddr_t addr, size_t n);
+mips_reg_t	kdbrpeek(vaddr_t, size_t);
 
 
 /*

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Sat May 15 02:37:07 UTC 2021

Modified Files:
src/sys/arch/mips/include: types.h

Log Message:
The MIPS O64 ABI uses full 64-bit FP regs.


To generate a diff of this commit:
cvs rdiff -u -r1.75 -r1.76 src/sys/arch/mips/include/types.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/types.h
diff -u src/sys/arch/mips/include/types.h:1.75 src/sys/arch/mips/include/types.h:1.76
--- src/sys/arch/mips/include/types.h:1.75	Mon Mar 29 02:07:43 2021
+++ src/sys/arch/mips/include/types.h	Sat May 15 02:37:07 2021
@@ -1,4 +1,4 @@
-/*	$NetBSD: types.h,v 1.75 2021/03/29 02:07:43 simonb Exp $	*/
+/*	$NetBSD: types.h,v 1.76 2021/05/15 02:37:07 simonb Exp $	*/
 
 /*-
  * Copyright (c) 1992, 1993
@@ -49,13 +49,10 @@ typedef __uint64_t		__fpregister64_t;
 typedef	unsigned int		__cpu_simple_lock_nv_t;
 #if defined(__mips_o32)
 typedef __register32_t		__register_t;
+typedef __fpregister32_t	__fpregister_t;
 #else
 typedef __register64_t		__register_t;
-#endif
-#if defined(__mips_o64) || defined(__mips_o32)
-typedef	__fpregister32_t	__fpregister_t;
-#else
-typedef	__fpregister64_t	__fpregister_t;
+typedef __fpregister64_t	__fpregister_t;
 #endif
 
 /*

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Wed May 12 03:53:37 UTC 2021

Modified Files:
src/sys/arch/mips/include: locore.h

Log Message:
Whitespace nit.


To generate a diff of this commit:
cvs rdiff -u -r1.117 -r1.118 src/sys/arch/mips/include/locore.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/locore.h
diff -u src/sys/arch/mips/include/locore.h:1.117 src/sys/arch/mips/include/locore.h:1.118
--- src/sys/arch/mips/include/locore.h:1.117	Tue Mar  2 08:16:52 2021
+++ src/sys/arch/mips/include/locore.h	Wed May 12 03:53:37 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.117 2021/03/02 08:16:52 skrll Exp $ */
+/* $NetBSD: locore.h,v 1.118 2021/05/12 03:53:37 simonb Exp $ */
 
 /*
  * This file should not be included by MI code!!!
@@ -306,7 +306,7 @@ struct mips_options {
 #endif
 #define	MIPS_HAS_LLADDR		((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
 #define	MIPS_HAS_DSP		(mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP)
-# define MIPS_HAS_USERLOCAL	(mips_options.mips_cpu_flags & CPU_MIPS_HAVE_USERLOCAL)
+#define MIPS_HAS_USERLOCAL	(mips_options.mips_cpu_flags & CPU_MIPS_HAVE_USERLOCAL)
 
 /* This test is ... rather bogus */
 #define	CPUISMIPS3	((mips_options.mips_cpu_arch & \

CVS commit: src/sys/arch/mips/include

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Sat May  8 13:09:58 UTC 2021

Modified Files:
src/sys/arch/mips/include: mips_param.h

Log Message:
KNG


To generate a diff of this commit:
cvs rdiff -u -r1.48 -r1.49 src/sys/arch/mips/include/mips_param.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/mips_param.h
diff -u src/sys/arch/mips/include/mips_param.h:1.48 src/sys/arch/mips/include/mips_param.h:1.49
--- src/sys/arch/mips/include/mips_param.h:1.48	Mon Apr 26 13:29:51 2021
+++ src/sys/arch/mips/include/mips_param.h	Sat May  8 13:09:58 2021
@@ -1,4 +1,4 @@
-/*	$NetBSD: mips_param.h,v 1.48 2021/04/26 13:29:51 christos Exp $	*/
+/*	$NetBSD: mips_param.h,v 1.49 2021/05/08 13:09:58 skrll Exp $	*/
 
 /*-
  * Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -104,7 +104,7 @@
 
 #define	SEGSHIFT	(PGSHIFT + PTPLENGTH)	/* LOG2(NBSEG) */
 #define	NBSEG		(1 << SEGSHIFT)	/* bytes/segment */
-#define	SEGOFSET	(NBSEG-1)	/* byte offset into segment */
+#define	SEGOFSET	(NBSEG - 1)	/* byte offset into segment */
 
 #ifdef _LP64
 #define	SEGLENGTH	(PGSHIFT - 3)

CVS commit: src/sys/arch/mips/include

[Christos Zoulas]

Module Name:src
Committed By:   christos
Date:   Mon Apr 26 13:29:51 UTC 2021

Modified Files:
src/sys/arch/mips/include: mips_param.h

Log Message:
Make MACHINE_ARCH for n64 binaries mipsn64e[bl] instead of mips64e[bl] to
differentiate them from n32/o32 binaries.


To generate a diff of this commit:
cvs rdiff -u -r1.47 -r1.48 src/sys/arch/mips/include/mips_param.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/mips_param.h
diff -u src/sys/arch/mips/include/mips_param.h:1.47 src/sys/arch/mips/include/mips_param.h:1.48
--- src/sys/arch/mips/include/mips_param.h:1.47	Wed Aug 26 06:51:45 2020
+++ src/sys/arch/mips/include/mips_param.h	Mon Apr 26 09:29:51 2021
@@ -1,4 +1,4 @@
-/*	$NetBSD: mips_param.h,v 1.47 2020/08/26 10:51:45 simonb Exp $	*/
+/*	$NetBSD: mips_param.h,v 1.48 2021/04/26 13:29:51 christos Exp $	*/
 
 /*-
  * Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -29,27 +29,28 @@
  * No reason this can't be common
  */
 #if defined(__MIPSEB__)
-# if defined(__mips_n32) || defined(__mips_n64)
-#  define	_MACHINE_ARCH	mips64eb
-#  define	MACHINE_ARCH	"mips64eb"
-#  define	_MACHINE32_ARCH	mipseb
-#  define	MACHINE32_ARCH	"mipseb"
-# else
-#  define	_MACHINE_ARCH	mipseb
-#  define	MACHINE_ARCH	"mipseb"
-# endif
+# define _MACHINE_SUFFIX eb
+# define MACHINE_SUFFIX "eb"
 #elif defined(__MIPSEL__)
-# if defined(__mips_n32) || defined(__mips_n64)
-#  define	_MACHINE_ARCH	mips64el
-#  define	MACHINE_ARCH	"mips64el"
-#  define	_MACHINE32_ARCH	mipsel
-#  define	MACHINE32_ARCH	"mipsel"
-# else
-#  define	_MACHINE_ARCH	mipsel
-#  define	MACHINE_ARCH	"mipsel"
-#endif
+# define _MACHINE_SUFFIX el
+# define MACHINE_SUFFIX "el"
 #else
-#error neither __MIPSEL__ nor __MIPSEB__ are defined.
+# error neither __MIPSEL__ nor __MIPSEB__ are defined.
+#endif
+
+#if defined(__mips_n32) || defined(__mips_n64)
+# if defined(__mips_n32)
+#  define	_MACHINE_ARCH	mips64##_MACHINE_SUFFIX
+#  define	MACHINE_ARCH	"mips64" MACHINE_SUFFIX
+# else /* __mips_n64 */
+#  define	_MACHINE_ARCH	mipsn64##_MACHINE_SUFFIX
+#  define	MACHINE_ARCH	"mipsn64" MACHINE_SUFFIX
+# endif
+# define	_MACHINE32_ARCH	mips##_MACHINE_SUFFIX
+# define	MACHINE32_ARCH	"mips" MACHINE_SUFFIX
+#else /* o32 */
+# define	_MACHINE_ARCH	mips##_MACHINE_SUFFIX
+# define	MACHINE_ARCH	"mips" MACHINE_SUFFIX
 #endif
 
 /*

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Mon Mar 29 03:07:33 UTC 2021

Modified Files:
src/sys/arch/mips/include: db_machdep.h

Log Message:
Move the cpu_reset_address() declaration inside #ifdef _KERNEL, add a
comment.


To generate a diff of this commit:
cvs rdiff -u -r1.35 -r1.36 src/sys/arch/mips/include/db_machdep.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/db_machdep.h
diff -u src/sys/arch/mips/include/db_machdep.h:1.35 src/sys/arch/mips/include/db_machdep.h:1.36
--- src/sys/arch/mips/include/db_machdep.h:1.35	Mon Mar 29 03:03:48 2021
+++ src/sys/arch/mips/include/db_machdep.h	Mon Mar 29 03:07:33 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: db_machdep.h,v 1.35 2021/03/29 03:03:48 simonb Exp $ */
+/* $NetBSD: db_machdep.h,v 1.36 2021/03/29 03:07:33 simonb Exp $ */
 
 /*
  * Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
@@ -128,10 +128,15 @@ bool ddb_running_on_any_cpu_p(void);
 void db_resume_others(void);
 void db_mips_stack_trace(void *, void *, void (*pr)(const char *, ...));
 
-extern void (*cpu_reset_address)(void);
 
 #ifdef _KERNEL
 /*
+ * Optional function to perform machine- or cpu-specific reset.
+ * Called from ddb "machine reset".
+ */
+extern void (*cpu_reset_address)(void);
+
+/*
  * We have machine-dependent commands.
  */
 #define	DB_MACHINE_COMMANDS

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Mon Mar 29 03:03:48 UTC 2021

Modified Files:
src/sys/arch/mips/include: db_machdep.h

Log Message:
Whitespace nits.


To generate a diff of this commit:
cvs rdiff -u -r1.34 -r1.35 src/sys/arch/mips/include/db_machdep.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/db_machdep.h
diff -u src/sys/arch/mips/include/db_machdep.h:1.34 src/sys/arch/mips/include/db_machdep.h:1.35
--- src/sys/arch/mips/include/db_machdep.h:1.34	Wed Feb 10 07:19:54 2021
+++ src/sys/arch/mips/include/db_machdep.h	Mon Mar 29 03:03:48 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: db_machdep.h,v 1.34 2021/02/10 07:19:54 simonb Exp $ */
+/* $NetBSD: db_machdep.h,v 1.35 2021/03/29 03:03:48 simonb Exp $ */
 
 /*
  * Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
@@ -83,11 +83,10 @@ extern db_regs_t	ddb_regs;	/* register s
 #define	IS_WATCHPOINT_TRAP(type, code)	(0)	/* XXX mips3 watchpoint */
 
 /*
- * Interface to  disassembly (shared with mdb)
+ * Interface to disassembly (shared with mdb)
  */
 db_addr_t	db_disasm_insn(int insn, db_addr_t loc, bool altfmt);
 
-
 /*
  * Entrypoints to DDB for kernel, keyboard drivers, init hook
  */

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Mon Mar 29 02:07:43 UTC 2021

Modified Files:
src/sys/arch/mips/include: types.h

Log Message:
Provide vm_offset_t and vm_size_t typedefs - used by dtrace.


To generate a diff of this commit:
cvs rdiff -u -r1.74 -r1.75 src/sys/arch/mips/include/types.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/types.h
diff -u src/sys/arch/mips/include/types.h:1.74 src/sys/arch/mips/include/types.h:1.75
--- src/sys/arch/mips/include/types.h:1.74	Sat Jan 23 19:38:53 2021
+++ src/sys/arch/mips/include/types.h	Mon Mar 29 02:07:43 2021
@@ -1,4 +1,4 @@
-/*	$NetBSD: types.h,v 1.74 2021/01/23 19:38:53 christos Exp $	*/
+/*	$NetBSD: types.h,v 1.75 2021/03/29 02:07:43 simonb Exp $	*/
 
 /*-
  * Copyright (c) 1992, 1993
@@ -98,6 +98,9 @@ typedef __uint32_t	vsize_t;
 #define	PRIdVSIZE	PRId32
 #endif
 
+typedef	vaddr_t	vm_offset_t;	/* deprecated (cddl/FreeBSD compat) */
+typedef	vsize_t	vm_size_t;	/* deprecated (cddl/FreeBSD compat) */
+
 
 typedef int		mips_prid_t;
 /* Make sure this is signed; we need pointers to be sign-extended. */

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Mon Mar 29 01:47:46 UTC 2021

Modified Files:
src/sys/arch/mips/include: cpu.h

Log Message:
Include #include  to get lwp_trapframe() definition.
Needed for dtrace.


To generate a diff of this commit:
cvs rdiff -u -r1.131 -r1.132 src/sys/arch/mips/include/cpu.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/cpu.h
diff -u src/sys/arch/mips/include/cpu.h:1.131 src/sys/arch/mips/include/cpu.h:1.132
--- src/sys/arch/mips/include/cpu.h:1.131	Mon Aug 17 03:19:35 2020
+++ src/sys/arch/mips/include/cpu.h	Mon Mar 29 01:47:45 2021
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpu.h,v 1.131 2020/08/17 03:19:35 mrg Exp $	*/
+/*	$NetBSD: cpu.h,v 1.132 2021/03/29 01:47:45 simonb Exp $	*/
 
 /*-
  * Copyright (c) 1992, 1993
@@ -53,6 +53,8 @@
 #include "opt_multiprocessor.h"
 #endif
 
+#include 
+
 #include 
 #include 
 #include 

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Mon Mar 29 01:46:26 UTC 2021

Modified Files:
src/sys/arch/mips/include: frame.h

Log Message:
Add an lwp_trapframe() interface to return an LWP's user trapframe.
Needed by dtrace.


To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/mips/include/frame.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/frame.h
diff -u src/sys/arch/mips/include/frame.h:1.11 src/sys/arch/mips/include/frame.h:1.12
--- src/sys/arch/mips/include/frame.h:1.11	Wed Mar 24 05:35:05 2021
+++ src/sys/arch/mips/include/frame.h	Mon Mar 29 01:46:26 2021
@@ -1,4 +1,4 @@
-/*	$NetBSD: frame.h,v 1.11 2021/03/24 05:35:05 simonb Exp $	*/
+/*	$NetBSD: frame.h,v 1.12 2021/03/29 01:46:26 simonb Exp $	*/
 
 /*
  * Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -42,6 +42,8 @@
 #include 
 
 void *getframe(struct lwp *, int, int *);
+#define	lwp_trapframe(l)	((l)->l_md.md_utf)
+
 #if defined(COMPAT_16) || defined(COMPAT_ULTRIX)
 void sendsig_sigcontext(const ksiginfo_t *, const sigset_t *);
 #endif

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Wed Mar 24 05:35:06 UTC 2021

Modified Files:
src/sys/arch/mips/include: frame.h

Log Message:
We don't really need a comment at the end of the file saying "this is
the end of the file".


To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/mips/include/frame.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/frame.h
diff -u src/sys/arch/mips/include/frame.h:1.10 src/sys/arch/mips/include/frame.h:1.11
--- src/sys/arch/mips/include/frame.h:1.10	Sun Jul 26 08:08:41 2020
+++ src/sys/arch/mips/include/frame.h	Wed Mar 24 05:35:05 2021
@@ -1,4 +1,4 @@
-/*	$NetBSD: frame.h,v 1.10 2020/07/26 08:08:41 simonb Exp $	*/
+/*	$NetBSD: frame.h,v 1.11 2021/03/24 05:35:05 simonb Exp $	*/
 
 /*
  * Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -49,5 +49,3 @@ void sendsig_sigcontext(const ksiginfo_t
 #endif /* _LOCORE */
 
 #endif /* _MIPS_FRAME_H_ */
-
-/* End of frame.h */

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Tue Mar 23 11:56:55 UTC 2021

Modified Files:
src/sys/arch/mips/include: Makefile.inc

Log Message:
Remove addition of -msym32 to CFLAGS. Hinders rather than helps build
MIPS modules.


To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/mips/include/Makefile.inc

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/Makefile.inc
diff -u src/sys/arch/mips/include/Makefile.inc:1.10 src/sys/arch/mips/include/Makefile.inc:1.11
--- src/sys/arch/mips/include/Makefile.inc:1.10	Thu Jun  9 05:43:51 2016
+++ src/sys/arch/mips/include/Makefile.inc	Tue Mar 23 11:56:55 2021
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile.inc,v 1.10 2016/06/09 05:43:51 martin Exp $
+# $NetBSD: Makefile.inc,v 1.11 2021/03/23 11:56:55 simonb Exp $
 
 CFLAGS+=	-G 0 -ffixed-24
 
@@ -8,8 +8,4 @@ CFLAGS+=	-mno-abicalls
 AFLAGS+=	-mno-abicalls
 .endif
 
-.if ${MACHINE_ARCH} == "mips64eb" || ${MACHINE_ARCH} == "mips64el"
-CFLAGS+=	-msym32
-.endif
-
 AFLAGS+=	-x assembler-with-cpp ${AOPTS}

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Thu Mar 18 23:18:36 UTC 2021

Modified Files:
src/sys/arch/mips/include: ptrace.h

Log Message:
Add PTRACE_ILLEGAL_ASM using the MIPS32r6/MIPS64r6 backwards and
forwards compatible "sigrie" instruction to generate a Reserved
Instruction trap.


To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/mips/include/ptrace.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/ptrace.h
diff -u src/sys/arch/mips/include/ptrace.h:1.18 src/sys/arch/mips/include/ptrace.h:1.19
--- src/sys/arch/mips/include/ptrace.h:1.18	Sun Jul 26 08:08:41 2020
+++ src/sys/arch/mips/include/ptrace.h	Thu Mar 18 23:18:36 2021
@@ -1,4 +1,4 @@
-/*	$NetBSD: ptrace.h,v 1.18 2020/07/26 08:08:41 simonb Exp $	*/
+/*	$NetBSD: ptrace.h,v 1.19 2021/03/18 23:18:36 simonb Exp $	*/
 
 /*
  * Copyright (c) 1992, 1993
@@ -67,6 +67,21 @@
 #define	PTRACE_REG_SP(r)	(r)->r_regs[29]
 #define	PTRACE_REG_INTRV(r)	(r)->r_regs[2]
 
+/*
+ * The sigrie is defined in the MIPS32r6 and MIPS64r6 specs to
+ * generate a Reserved Instruction trap but uses a previously
+ * reserved instruction encoding and is thus both backwards and
+ * forwards compatible.
+ */
+#define	PTRACE_ILLEGAL_ASM	do {	\
+		asm volatile(		\
+			".set	push;		"			\
+			".set	mips32r6;	"			\
+			"sigrie	0;		"			\
+			".set	pop;		"			\
+		);			\
+	} while (0);
+
 #define	PTRACE_BREAKPOINT	((const uint8_t[]) { 0x00, 0x00, 0x00, 0x0d })
 #define	PTRACE_BREAKPOINT_ASM	__asm __volatile("break")
 #define	PTRACE_BREAKPOINT_SIZE	4

CVS commit: src/sys/arch/mips/include

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Tue Mar  2 08:16:53 UTC 2021

Modified Files:
src/sys/arch/mips/include: locore.h

Log Message:
Ensure the "memory" clobber is on inline assembly store operations

No binary change of note with this change in MALTA32


To generate a diff of this commit:
cvs rdiff -u -r1.116 -r1.117 src/sys/arch/mips/include/locore.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/locore.h
diff -u src/sys/arch/mips/include/locore.h:1.116 src/sys/arch/mips/include/locore.h:1.117
--- src/sys/arch/mips/include/locore.h:1.116	Sat Aug 22 09:08:21 2020
+++ src/sys/arch/mips/include/locore.h	Tue Mar  2 08:16:52 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.116 2020/08/22 09:08:21 simonb Exp $ */
+/* $NetBSD: locore.h,v 1.117 2021/03/02 08:16:52 skrll Exp $ */
 
 /*
  * This file should not be included by MI code!!!
@@ -539,7 +539,7 @@ static inline void
 mips_sb(register_t addr, uint8_t val)
 {
 #if defined(__mips_n32)
-	__asm volatile("sb\t%1, 0(%0)" :: "d"(addr), "r"(val));
+	__asm volatile("sb\t%1, 0(%0)" :: "d"(addr), "r"(val) : "memory");
 #else
 	*(volatile uint8_t *)addr = val;
 #endif
@@ -549,7 +549,7 @@ static inline void
 mips_sh(register_t addr, uint16_t val)
 {
 #if defined(__mips_n32)
-	__asm volatile("sh\t%1, 0(%0)" :: "d"(addr), "r"(val));
+	__asm volatile("sh\t%1, 0(%0)" :: "d"(addr), "r"(val) : "memory");
 #else
 	*(volatile uint16_t *)addr = val;
 #endif
@@ -559,7 +559,7 @@ static inline void
 mips_sw(register_t addr, uint32_t val)
 {
 #if defined(__mips_n32)
-	__asm volatile("sw\t%1, 0(%0)" :: "d"(addr), "r"(val));
+	__asm volatile("sw\t%1, 0(%0)" :: "d"(addr), "r"(val) : "memory");
 #else
 	*(volatile uint32_t *)addr = val;
 #endif
@@ -570,7 +570,7 @@ static inline void
 mips3_sd(register_t addr, uint64_t val)
 {
 #if defined(__mips_n32)
-	__asm volatile("sd\t%1, 0(%0)" :: "d"(addr), "r"(val));
+	__asm volatile("sd\t%1, 0(%0)" :: "d"(addr), "r"(val) : "memory");
 #else
 	*(volatile uint64_t *)addr = val;
 #endif

CVS commit: src/sys/arch/mips/include

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Thu Feb 18 20:37:02 UTC 2021

Modified Files:
src/sys/arch/mips/include: profile.h

Log Message:
Revert previous... somehow the register names aren't available apparently


To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/mips/include/profile.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/profile.h
diff -u src/sys/arch/mips/include/profile.h:1.24 src/sys/arch/mips/include/profile.h:1.25
--- src/sys/arch/mips/include/profile.h:1.24	Wed Feb 17 08:09:22 2021
+++ src/sys/arch/mips/include/profile.h	Thu Feb 18 20:37:02 2021
@@ -1,4 +1,4 @@
-/*	$NetBSD: profile.h,v 1.24 2021/02/17 08:09:22 skrll Exp $	*/
+/*	$NetBSD: profile.h,v 1.25 2021/02/18 20:37:02 skrll Exp $	*/
 
 /*
  * Copyright (c) 1992, 1993
@@ -57,7 +57,7 @@
 #ifdef _KERNEL
 # define _PROF_CPLOAD	""
 #else
-# define _PROF_CPLOAD	".cpload t9;"
+# define _PROF_CPLOAD	".cpload $25;"
 #endif
 
 

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Thu Feb 18 12:28:02 UTC 2021

Modified Files:
src/sys/arch/mips/include: asm.h

Log Message:
Add an abicalls version of asm mcount prologue.  XXX not tested because
profiled programs fail to link, but fixes build.  Thanks dholland@ for
help analysing this.

While here, rename _KERN_MCOUNT to _MIPS_ASM_MCOUNT - it's not kernel
specific.


To generate a diff of this commit:
cvs rdiff -u -r1.64 -r1.65 src/sys/arch/mips/include/asm.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/asm.h
diff -u src/sys/arch/mips/include/asm.h:1.64 src/sys/arch/mips/include/asm.h:1.65
--- src/sys/arch/mips/include/asm.h:1.64	Tue Feb 16 06:06:58 2021
+++ src/sys/arch/mips/include/asm.h	Thu Feb 18 12:28:01 2021
@@ -1,4 +1,4 @@
-/*	$NetBSD: asm.h,v 1.64 2021/02/16 06:06:58 simonb Exp $	*/
+/*	$NetBSD: asm.h,v 1.65 2021/02/18 12:28:01 simonb Exp $	*/
 
 /*
  * Copyright (c) 1992, 1993
@@ -76,9 +76,9 @@
 /*
  * The old ABI version must also decrement two less words off the
  * stack and the final addiu to t9 must always equal the size of this
- * _KERN_MCOUNT.
+ * _MIPS_ASM_MCOUNT.
  */
-#define	_KERN_MCOUNT		\
+#define	_MIPS_ASM_MCOUNT	\
 	.set	push;		\
 	.set	noreorder;	\
 	.set	noat;		\
@@ -98,9 +98,25 @@
 #else/* New (n32/n64) ABI */
 /*
  * The new ABI version just needs to put the return address in AT and
- * call _mcount().
+ * call _mcount().  For the no abicalls case, skip the reloc dance.
  */
-#define	_KERN_MCOUNT		\
+#ifdef __mips_abicalls
+#define	_MIPS_ASM_MCOUNT	\
+	.set	push;		\
+	.set	noreorder;	\
+	.set	noat;		\
+	subu	sp,16;		\
+	sw	t9,8(sp);	\
+	move	AT,ra;		\
+	lui	t9,%hi(_mcount); \
+	addiu	t9,t9,%lo(_mcount);\
+	jalr	t9;		\
+	 nop;			\
+	lw	t9,8(sp);	\
+	addiu	sp,16;		\
+	.set	pop;
+#else /* !__mips_abicalls */
+#define	_MIPS_ASM_MCOUNT	\
 	.set	push;		\
 	.set	noreorder;	\
 	.set	noat;		\
@@ -108,10 +124,11 @@
 	jal	_mcount;	\
 	 nop;			\
 	.set	pop;
+#endif /* !__mips_abicalls */
 #endif /* n32/n64 */
 
 #ifdef GPROF
-#define	MCOUNT _KERN_MCOUNT
+#define	MCOUNT _MIPS_ASM_MCOUNT
 #else
 #define	MCOUNT
 #endif

CVS commit: src/sys/arch/mips/include

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Wed Feb 17 08:09:22 UTC 2021

Modified Files:
src/sys/arch/mips/include: profile.h

Log Message:
Use the register name and not its number in _PROF_CPLOAD.

"yes please!" from simon@


To generate a diff of this commit:
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/mips/include/profile.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/profile.h
diff -u src/sys/arch/mips/include/profile.h:1.23 src/sys/arch/mips/include/profile.h:1.24
--- src/sys/arch/mips/include/profile.h:1.23	Tue Feb 16 06:06:58 2021
+++ src/sys/arch/mips/include/profile.h	Wed Feb 17 08:09:22 2021
@@ -1,4 +1,4 @@
-/*	$NetBSD: profile.h,v 1.23 2021/02/16 06:06:58 simonb Exp $	*/
+/*	$NetBSD: profile.h,v 1.24 2021/02/17 08:09:22 skrll Exp $	*/
 
 /*
  * Copyright (c) 1992, 1993
@@ -57,7 +57,7 @@
 #ifdef _KERNEL
 # define _PROF_CPLOAD	""
 #else
-# define _PROF_CPLOAD	".cpload $25;"
+# define _PROF_CPLOAD	".cpload t9;"
 #endif
 
 

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Tue Feb 16 05:11:27 UTC 2021

Modified Files:
src/sys/arch/mips/include: intr.h

Log Message:
Add no-profiled attribute for splhigh_noprof() and splx_noprof().


To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/mips/include/intr.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/intr.h
diff -u src/sys/arch/mips/include/intr.h:1.12 src/sys/arch/mips/include/intr.h:1.13
--- src/sys/arch/mips/include/intr.h:1.12	Mon Aug 17 14:17:49 2020
+++ src/sys/arch/mips/include/intr.h	Tue Feb 16 05:11:26 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: intr.h,v 1.12 2020/08/17 14:17:49 skrll Exp $ */
+/* $NetBSD: intr.h,v 1.13 2021/02/16 05:11:26 simonb Exp $ */
 
 /*-
  * Copyright (c) 2009, 2010 The NetBSD Foundation, Inc.
@@ -125,7 +125,7 @@ extern	struct ipl_sr_map ipl_sr_map;
 #endif /* __INTR_PRIVATE */
 
 int	splhigh(void);
-int	splhigh_noprof(void);
+int	__noprofile splhigh_noprof(void);
 int	splsched(void);
 int	splvm(void);
 int	splsoftserial(void);
@@ -134,7 +134,7 @@ int	splsoftbio(void);
 int	splsoftclock(void);
 int	splraise(int);
 void	splx(int);
-void	splx_noprof(int);
+void	__noprofile splx_noprof(int);
 void	spl0(void);
 int	splintr(uint32_t *);
 void	_setsoftintr(uint32_t);

CVS commit: src/sys/arch/mips/include

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Thu Feb  4 08:51:42 UTC 2021

Modified Files:
src/sys/arch/mips/include: asm.h

Log Message:
Use t9 instead of $25 in the SETUP_GP64 macro to hopefully make things
a bit clearer.  Same libc binary after.


To generate a diff of this commit:
cvs rdiff -u -r1.62 -r1.63 src/sys/arch/mips/include/asm.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/asm.h
diff -u src/sys/arch/mips/include/asm.h:1.62 src/sys/arch/mips/include/asm.h:1.63
--- src/sys/arch/mips/include/asm.h:1.62	Sat Sep 26 08:19:11 2020
+++ src/sys/arch/mips/include/asm.h	Thu Feb  4 08:51:42 2021
@@ -1,4 +1,4 @@
-/*	$NetBSD: asm.h,v 1.62 2020/09/26 08:19:11 simonb Exp $	*/
+/*	$NetBSD: asm.h,v 1.63 2021/02/04 08:51:42 skrll Exp $	*/
 
 /*
  * Copyright (c) 1992, 1993
@@ -619,7 +619,7 @@ _C_LABEL(x):
 #define	SETUP_GPX(r)		/* o32 specific */
 #define	SETUP_GPX_L(r,lbl)	/* o32 specific */
 #define	SAVE_GP(x)		/* o32 specific */
-#define	SETUP_GP64(a,b)		.cpsetup $25, a, b
+#define	SETUP_GP64(a,b)		.cpsetup t9, a, b
 #define	SETUP_GPX64(a,b)	\
 .set push;			\
 move	b,ra;			\

CVS commit: src/sys/arch/mips/include

[Christos Zoulas]

Module Name:src
Committed By:   christos
Date:   Sun Dec  6 03:46:23 UTC 2020

Modified Files:
src/sys/arch/mips/include: proc.h types.h

Log Message:
don't expose vaddr_t to userland.


To generate a diff of this commit:
cvs rdiff -u -r1.32 -r1.33 src/sys/arch/mips/include/proc.h
cvs rdiff -u -r1.72 -r1.73 src/sys/arch/mips/include/types.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/proc.h
diff -u src/sys/arch/mips/include/proc.h:1.32 src/sys/arch/mips/include/proc.h:1.33
--- src/sys/arch/mips/include/proc.h:1.32	Fri Sep  4 04:17:53 2020
+++ src/sys/arch/mips/include/proc.h	Sat Dec  5 22:46:23 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: proc.h,v 1.32 2020/09/04 08:17:53 mrg Exp $	*/
+/*	$NetBSD: proc.h,v 1.33 2020/12/06 03:46:23 christos Exp $	*/
 
 /*
  * Copyright (c) 1992, 1993
@@ -49,7 +49,7 @@ struct trapframe;
 
 struct mdlwp {
 	struct trapframe *md_utf;	/* trapframe from userspace */
-	vaddr_t	md_ss_addr;		/* single step address for ptrace */
+	__vaddr_t md_ss_addr;		/* single step address for ptrace */
 	int	md_ss_instr;		/* single step instruction for ptrace */
 	volatile int md_astpending;	/* AST pending on return to userland */
 	int	md_upte[UPAGES_MAX];	/* ptes for mapping u page */
@@ -57,7 +57,7 @@ struct mdlwp {
 
 struct mdproc {
 	/* syscall entry for this process */
-	void	(*md_syscall)(struct lwp *, u_int, u_int, vaddr_t);
+	void	(*md_syscall)(struct lwp *, u_int, u_int, __vaddr_t);
 	int	md_abi;			/* which ABI is this process using? */
 };
 

Index: src/sys/arch/mips/include/types.h
diff -u src/sys/arch/mips/include/types.h:1.72 src/sys/arch/mips/include/types.h:1.73
--- src/sys/arch/mips/include/types.h:1.72	Sun Aug 16 23:19:35 2020
+++ src/sys/arch/mips/include/types.h	Sat Dec  5 22:46:23 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: types.h,v 1.72 2020/08/17 03:19:35 mrg Exp $	*/
+/*	$NetBSD: types.h,v 1.73 2020/12/06 03:46:23 christos Exp $	*/
 
 /*-
  * Copyright (c) 1992, 1993
@@ -64,6 +64,11 @@ typedef	__fpregister64_t	__fpregister_t;
  * the rest of the operating system as possible.
  */
 
+#ifdef _LP64
+typedef __uint64_t	__vaddr_t;
+#else
+typedef __uint32_t	__vaddr_t;
+#endif
 
 #if defined(_KERNEL) || defined(_KMEMUSER) || defined(_KERNTYPES) || defined(_STANDALONE)
 #if defined(_MIPS_PADDR_T_64BIT) || defined(_LP64)

CVS commit: src/sys/arch/mips/include

[Martin Husemann]

Module Name:src
Committed By:   martin
Date:   Sat Oct  3 09:56:00 UTC 2020

Modified Files:
src/sys/arch/mips/include: mcontext.h

Log Message:
Add missing __BEGIN_DECLS/__END_DECLS to force function declarations into
the "C" namespace.


To generate a diff of this commit:
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/mips/include/mcontext.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/mcontext.h
diff -u src/sys/arch/mips/include/mcontext.h:1.23 src/sys/arch/mips/include/mcontext.h:1.24
--- src/sys/arch/mips/include/mcontext.h:1.23	Sun Jul 26 08:08:41 2020
+++ src/sys/arch/mips/include/mcontext.h	Sat Oct  3 09:56:00 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: mcontext.h,v 1.23 2020/07/26 08:08:41 simonb Exp $	*/
+/*	$NetBSD: mcontext.h,v 1.24 2020/10/03 09:56:00 martin Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2002 The NetBSD Foundation, Inc.
@@ -196,6 +196,8 @@ typedef struct {
 __CTASSERT(TLS_TP_OFFSET + sizeof(struct tls_tcb) < 0x8000);
 __CTASSERT(TLS_TP_OFFSET % sizeof(struct tls_tcb) == 0);
 
+__BEGIN_DECLS
+
 static __inline struct tls_tcb *
 __lwp_gettcb_fast(void)
 {
@@ -233,6 +235,7 @@ __lwp_settcb(struct tls_tcb *__tcb)
 	__tcb += TLS_TP_OFFSET / sizeof(*__tcb) + 1;
 	_lwp_setprivate(__tcb);
 }
+__END_DECLS
 #endif
 
 #endif	/* _MIPS_MCONTEXT_H_ */

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Sat Sep 26 08:19:11 UTC 2020

Modified Files:
src/sys/arch/mips/include: asm.h

Log Message:
Add EXPORT_OBJECT - export definition of symbol of symbol type Object,
visible to ksyms(4) address search.


To generate a diff of this commit:
cvs rdiff -u -r1.61 -r1.62 src/sys/arch/mips/include/asm.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/asm.h
diff -u src/sys/arch/mips/include/asm.h:1.61 src/sys/arch/mips/include/asm.h:1.62
--- src/sys/arch/mips/include/asm.h:1.61	Wed Aug 12 08:56:37 2020
+++ src/sys/arch/mips/include/asm.h	Sat Sep 26 08:19:11 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: asm.h,v 1.61 2020/08/12 08:56:37 skrll Exp $	*/
+/*	$NetBSD: asm.h,v 1.62 2020/09/26 08:19:11 simonb Exp $	*/
 
 /*
  * Copyright (c) 1992, 1993
@@ -237,6 +237,14 @@ _C_LABEL(x):
 _C_LABEL(x):
 
 /*
+ * EXPORT_OBJECT -- export definition of symbol of symbol
+ * type Object, visible to ksyms(4) address search.
+ */
+#define	EXPORT_OBJECT(x)		\
+	EXPORT(x);			\
+	.type	_C_LABEL(x), @object;
+
+/*
  * VECTOR
  *	exception vector entrypoint
  *	XXX: regmask should be used to generate .mask

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Sat Sep 26 04:31:53 UTC 2020

Modified Files:
src/sys/arch/mips/include: pcb.h

Log Message:
Whitespace consistency nit.


To generate a diff of this commit:
cvs rdiff -u -r1.26 -r1.27 src/sys/arch/mips/include/pcb.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/pcb.h
diff -u src/sys/arch/mips/include/pcb.h:1.26 src/sys/arch/mips/include/pcb.h:1.27
--- src/sys/arch/mips/include/pcb.h:1.26	Mon Aug 17 04:15:33 2020
+++ src/sys/arch/mips/include/pcb.h	Sat Sep 26 04:31:53 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: pcb.h,v 1.26 2020/08/17 04:15:33 mrg Exp $	*/
+/*	$NetBSD: pcb.h,v 1.27 2020/09/26 04:31:53 simonb Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -57,7 +57,7 @@ struct pcb_faultinfo {
  */
 struct pcb {
 	mips_label_t pcb_context;	/* kernel context for resume */
-	void *	pcb_onfault;		/* for copyin/copyout faults */
+	void *pcb_onfault;		/* for copyin/copyout faults */
 	uint32_t pcb_ppl;		/* previous priority level */
 	struct fpreg pcb_fpregs;	/* saved floating point registers */
 	struct dspreg pcb_dspregs;	/* saved DSP registers */

CVS commit: src/sys/arch/mips/include

[matthew green]

Module Name:src
Committed By:   mrg
Date:   Fri Sep  4 08:17:53 UTC 2020

Modified Files:
src/sys/arch/mips/include: proc.h

Log Message:
include machine/vmparam.h vs mips/vmparam.h to make sure we get
platform-specific defines first.

fixes build issue for playstation2.


To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/mips/include/proc.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/proc.h
diff -u src/sys/arch/mips/include/proc.h:1.31 src/sys/arch/mips/include/proc.h:1.32
--- src/sys/arch/mips/include/proc.h:1.31	Wed Aug 26 10:51:45 2020
+++ src/sys/arch/mips/include/proc.h	Fri Sep  4 08:17:53 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: proc.h,v 1.31 2020/08/26 10:51:45 simonb Exp $	*/
+/*	$NetBSD: proc.h,v 1.32 2020/09/04 08:17:53 mrg Exp $	*/
 
 /*
  * Copyright (c) 1992, 1993
@@ -38,7 +38,7 @@
 #define	_MIPS_PROC_H_
 
 #include 
-#include 
+#include 
 
 struct lwp;
 

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Wed Aug 26 10:51:45 UTC 2020

Modified Files:
src/sys/arch/mips/include: mips_param.h proc.h

Log Message:
Define a UPAGES_MAX constant to size the a md_upte array in MIPS's
struct mdlwp.  This is exposed to userland, so we can't use something
based on PAGE_SIZE.


To generate a diff of this commit:
cvs rdiff -u -r1.46 -r1.47 src/sys/arch/mips/include/mips_param.h
cvs rdiff -u -r1.30 -r1.31 src/sys/arch/mips/include/proc.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/mips_param.h
diff -u src/sys/arch/mips/include/mips_param.h:1.46 src/sys/arch/mips/include/mips_param.h:1.47
--- src/sys/arch/mips/include/mips_param.h:1.46	Sun Aug 23 10:23:38 2020
+++ src/sys/arch/mips/include/mips_param.h	Wed Aug 26 10:51:45 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: mips_param.h,v 1.46 2020/08/23 10:23:38 simonb Exp $	*/
+/*	$NetBSD: mips_param.h,v 1.47 2020/08/26 10:51:45 simonb Exp $	*/
 
 /*-
  * Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -130,6 +130,7 @@
 #define	USPACE		MAX(__MIN_USPACE, PAGE_SIZE)
 #define	UPAGES		(USPACE / PAGE_SIZE) /* number of pages for u-area */
 #define	USPACE_ALIGN	USPACE		/* make sure it starts on a even VA */
+#define	UPAGES_MAX	8		/* a (constant) max for userland use */
 
 /*
  * Minimum and maximum sizes of the kernel malloc arena in PAGE_SIZE-sized

Index: src/sys/arch/mips/include/proc.h
diff -u src/sys/arch/mips/include/proc.h:1.30 src/sys/arch/mips/include/proc.h:1.31
--- src/sys/arch/mips/include/proc.h:1.30	Sun Aug 23 10:23:38 2020
+++ src/sys/arch/mips/include/proc.h	Wed Aug 26 10:51:45 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: proc.h,v 1.30 2020/08/23 10:23:38 simonb Exp $	*/
+/*	$NetBSD: proc.h,v 1.31 2020/08/26 10:51:45 simonb Exp $	*/
 
 /*
  * Copyright (c) 1992, 1993
@@ -52,7 +52,7 @@ struct mdlwp {
 	vaddr_t	md_ss_addr;		/* single step address for ptrace */
 	int	md_ss_instr;		/* single step instruction for ptrace */
 	volatile int md_astpending;	/* AST pending on return to userland */
-	int	md_upte[UPAGES];	/* ptes for mapping u page */
+	int	md_upte[UPAGES_MAX];	/* ptes for mapping u page */
 };
 
 struct mdproc {

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Sat Aug 22 09:08:21 UTC 2020

Modified Files:
src/sys/arch/mips/include: locore.h

Log Message:
Invert the MIPS-I non-4kB page size check.  The previous check doesn't
fail if both MIPS1 and MIPS3_PLUS are defined.  Explictly check against
MIPS1.


To generate a diff of this commit:
cvs rdiff -u -r1.115 -r1.116 src/sys/arch/mips/include/locore.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/locore.h
diff -u src/sys/arch/mips/include/locore.h:1.115 src/sys/arch/mips/include/locore.h:1.116
--- src/sys/arch/mips/include/locore.h:1.115	Mon Aug 17 03:19:35 2020
+++ src/sys/arch/mips/include/locore.h	Sat Aug 22 09:08:21 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.115 2020/08/17 03:19:35 mrg Exp $ */
+/* $NetBSD: locore.h,v 1.116 2020/08/22 09:08:21 simonb Exp $ */
 
 /*
  * This file should not be included by MI code!!!
@@ -89,8 +89,8 @@ typedef uint32_t pt_entry_t;
 #undef MIPS3_PLUS
 #endif
 
-#if !defined(MIPS3_PLUS) && (ENABLE_MIPS_8KB_PAGE + ENABLE_MIPS_16KB_PAGE) > 0
-#error MIPS1 does not support non-4KB page sizes.
+#if defined(MIPS1) && (ENABLE_MIPS_8KB_PAGE + ENABLE_MIPS_16KB_PAGE) > 0
+#error MIPS1 only supports a 4kB page size.
 #endif
 
 /* XXX some .S files look for MIPS3_PLUS */

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Sat Aug 22 03:41:33 UTC 2020

Modified Files:
src/sys/arch/mips/include: cpuregs.h

Log Message:
Remove bogus duplicate MIPS_COP_0_CONTEXT definition, it's not a MIPS32/64
specific reg and we already define MIPS_COP_0_TLB_CONTEXT elsewhere.


To generate a diff of this commit:
cvs rdiff -u -r1.108 -r1.109 src/sys/arch/mips/include/cpuregs.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/cpuregs.h
diff -u src/sys/arch/mips/include/cpuregs.h:1.108 src/sys/arch/mips/include/cpuregs.h:1.109
--- src/sys/arch/mips/include/cpuregs.h:1.108	Sun Aug  2 23:04:23 2020
+++ src/sys/arch/mips/include/cpuregs.h	Sat Aug 22 03:41:33 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpuregs.h,v 1.108 2020/08/02 23:04:23 simonb Exp $	*/
+/*	$NetBSD: cpuregs.h,v 1.109 2020/08/22 03:41:33 simonb Exp $	*/
 
 /*
  * Copyright (c) 2009 Miodrag Vallat.
@@ -615,7 +615,6 @@
 #define	MIPS_COP_0_ERROR_PC	_(30)
 
 /* MIPS32/64 */
-#define	MIPS_COP_0_CONTEXT	_(4)
 #define	MIPS_COP_0_CTXCONFIG	_(4), 1
 #define	MIPS_COP_0_USERLOCAL	_(4), 2
 #define	MIPS_COP_0_XCTXCONFIG	_(4), 3		/* MIPS64 */

CVS commit: src/sys/arch/mips/include

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Mon Aug 17 14:17:49 UTC 2020

Modified Files:
src/sys/arch/mips/include: intr.h

Log Message:
Disable __HAVE_PREEMPTION.  It is currently marked

#if defined(MULTIPROCESSOR) && defined(__HAVE_FAST_SOFTINTS)

but has no chance of working on OCTEON due to at least the spl functions


To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/mips/include/intr.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/intr.h
diff -u src/sys/arch/mips/include/intr.h:1.11 src/sys/arch/mips/include/intr.h:1.12
--- src/sys/arch/mips/include/intr.h:1.11	Sun Jul 26 08:08:41 2020
+++ src/sys/arch/mips/include/intr.h	Mon Aug 17 14:17:49 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: intr.h,v 1.11 2020/07/26 08:08:41 simonb Exp $ */
+/* $NetBSD: intr.h,v 1.12 2020/08/17 14:17:49 skrll Exp $ */
 
 /*-
  * Copyright (c) 2009, 2010 The NetBSD Foundation, Inc.
@@ -112,10 +112,12 @@ typedef struct {
 
 #ifdef _KERNEL
 
+#if 0
 #if defined(MULTIPROCESSOR) && defined(__HAVE_FAST_SOFTINTS)
 #define	__HAVE_PREEMPTION	1
 #define	SOFTINT_KPREEMPT	(SOFTINT_COUNT+0)
 #endif
+#endif
 
 #ifdef __INTR_PRIVATE
 extern	struct splsw	mips_splsw;

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Sat Aug 15 04:27:28 UTC 2020

Modified Files:
src/sys/arch/mips/include: mips_opcode.h

Log Message:
Fix value for SCE/SWE instructions.
Problem noticed by mrg@.


To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/mips/include/mips_opcode.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/mips_opcode.h
diff -u src/sys/arch/mips/include/mips_opcode.h:1.22 src/sys/arch/mips/include/mips_opcode.h:1.23
--- src/sys/arch/mips/include/mips_opcode.h:1.22	Sun Jul 26 08:08:41 2020
+++ src/sys/arch/mips/include/mips_opcode.h	Sat Aug 15 04:27:28 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: mips_opcode.h,v 1.22 2020/07/26 08:08:41 simonb Exp $	*/
+/*	$NetBSD: mips_opcode.h,v 1.23 2020/08/15 04:27:28 simonb Exp $	*/
 
 /*-
  * Copyright (c) 1992, 1993
@@ -316,8 +316,8 @@ typedef union {
 #define	OP_CACHEE	033		/* EVA */
 #define	OP_SBE		034		/* EVA */
 #define	OP_SHE		035		/* EVA */
-#define	OP_SCE		035		/* EVA */
-#define	OP_SWE		035		/* EVA */
+#define	OP_SCE		036		/* EVA */
+#define	OP_SWE		037		/* EVA */
 #define	OP_BSHFL	040		/* MIPS32/64 r2 */
 #define	OP_SWLE		041		/* EVA */
 #define	OP_SWRE		042		/* EVA */

CVS commit: src/sys/arch/mips/include

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Wed Aug 12 08:56:37 UTC 2020

Modified Files:
src/sys/arch/mips/include: asm.h

Log Message:
Provide assmebler versions of BITS(3) macros.  These are only good for
32 bit masks


To generate a diff of this commit:
cvs rdiff -u -r1.60 -r1.61 src/sys/arch/mips/include/asm.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/asm.h
diff -u src/sys/arch/mips/include/asm.h:1.60 src/sys/arch/mips/include/asm.h:1.61
--- src/sys/arch/mips/include/asm.h:1.60	Mon Aug 10 14:37:38 2020
+++ src/sys/arch/mips/include/asm.h	Wed Aug 12 08:56:37 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: asm.h,v 1.60 2020/08/10 14:37:38 skrll Exp $	*/
+/*	$NetBSD: asm.h,v 1.61 2020/08/12 08:56:37 skrll Exp $	*/
 
 /*
  * Copyright (c) 1992, 1993
@@ -57,6 +57,13 @@
 #include 		/* for API selection */
 #include 
 
+#define	__BIT(n)	(1 << (n))
+#define	__BITS(hi,lo)	((~((~0)<<((hi)+1)))&((~0)<<(lo)))
+
+#define	__LOWEST_SET_BIT(__mask) __mask) - 1) & (__mask)) ^ (__mask))
+#define	__SHIFTOUT(__x, __mask) (((__x) & (__mask)) / __LOWEST_SET_BIT(__mask))
+#define	__SHIFTIN(__x, __mask) ((__x) * __LOWEST_SET_BIT(__mask))
+
 /*
  * Define -pg profile entry code.
  * Must always be noreorder, must never use a macro instruction

CVS commit: src/sys/arch/mips/include

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Sun Aug  9 08:13:09 UTC 2020

Modified Files:
src/sys/arch/mips/include: asm.h

Log Message:
Use compiler defines to determine which LLSCSYNC, et al
to provide.

This should fix mips builds.


To generate a diff of this commit:
cvs rdiff -u -r1.58 -r1.59 src/sys/arch/mips/include/asm.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/asm.h
diff -u src/sys/arch/mips/include/asm.h:1.58 src/sys/arch/mips/include/asm.h:1.59
--- src/sys/arch/mips/include/asm.h:1.58	Thu Aug  6 10:00:20 2020
+++ src/sys/arch/mips/include/asm.h	Sun Aug  9 08:13:09 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: asm.h,v 1.58 2020/08/06 10:00:20 skrll Exp $	*/
+/*	$NetBSD: asm.h,v 1.59 2020/08/09 08:13:09 skrll Exp $	*/
 
 /*
  * Copyright (c) 1992, 1993
@@ -54,10 +54,6 @@
 #ifndef _MIPS_ASM_H
 #define	_MIPS_ASM_H
 
-#include "opt_cputype.h"
-#include "opt_lockdebug.h"
-#include "opt_multiprocessor.h"
-
 #include 		/* for API selection */
 #include 
 
@@ -517,23 +513,17 @@ _C_LABEL(x):
 #define	NOP_L		/* nothing */
 #endif
 
-#if defined(MULTIPROCESSOR)
-#if defined(MIPS64_OCTEON)
+/* compiler define */
+#if defined(__OCTEON__)
 /* early cnMIPS have erratum which means 2 */
 #define	LLSCSYNC	sync 4; sync 4
 #define	SYNC		sync 4		/* sync 4 == syncw - sync all writes */
 #define	BDSYNC		sync 4		/* sync 4 == syncw - sync all writes */
 #else
-#define	LLSCSYNC	/* nothing (something?) */
+#define	LLSCSYNC	sync
 #define	SYNC		sync
 #define	BDSYNC		sync
 #endif
-#else
-#define	LLSCSYNC	/* nothing */
-#define	SYNC		/* nothing */
-#define	BDSYNC		nop
-#endif /* defined(MULTIPROCESSOR) */
-
 
 /* CPU dependent hook for cp0 load delays */
 #if defined(MIPS1) || defined(MIPS2) || defined(MIPS3)

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Wed Aug  5 05:24:44 UTC 2020

Modified Files:
src/sys/arch/mips/include: lock.h

Log Message:
Indent branch delay slots in asm code (from skrll@).
Be consistent within this file with how asm code is formatted.


To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/mips/include/lock.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/lock.h
diff -u src/sys/arch/mips/include/lock.h:1.20 src/sys/arch/mips/include/lock.h:1.21
--- src/sys/arch/mips/include/lock.h:1.20	Sun Sep 17 00:01:07 2017
+++ src/sys/arch/mips/include/lock.h	Wed Aug  5 05:24:44 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: lock.h,v 1.20 2017/09/17 00:01:07 christos Exp $	*/
+/*	$NetBSD: lock.h,v 1.21 2020/08/05 05:24:44 simonb Exp $	*/
 
 /*-
  * Copyright (c) 2001, 2007 The NetBSD Foundation, Inc.
@@ -78,15 +78,15 @@ __cpu_simple_lock_try(__cpu_simple_lock_
 		"	.set mips2		\n"
 		"1:	ll	%0, %4		\n"
 		"	bnez	%0, 2f		\n"
-		"	nop	   # BDslot	\n"
+		"	 nop			\n"
 		"	li	%0, %3		\n"
 		"	sc	%0, %2		\n"
 		"	beqz	%0, 2f		\n"
-		"	nop	   # BDslot	\n"
+		"	 nop			\n"
 		"	li	%1, 1		\n"
 		"	sync			\n"
 		"	j	3f		\n"
-		"	nop			\n"
+		"	 nop			\n"
 		"	nop			\n"
 		"2:	li	%1, 0		\n"
 		"3:\n"
@@ -121,11 +121,11 @@ static __inline void
 mb_read(void)
 {
 	__asm volatile(
-	"	.set push\n"
-	"	.set mips2\n"
-	"	sync\n"
-	"	.set pop"
-	::: "memory"
+		"	.set push		\n"
+		"	.set mips2		\n"
+		"	sync			\n"
+		"	.set pop"
+		::: "memory"
 	);
 }
 

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Sun Aug  2 23:20:25 UTC 2020

Modified Files:
src/sys/arch/mips/include: mipsNN.h

Log Message:
Document the PerfCntCrl registers (CP0 Register 25, Selects 0, 2, 4, 6).


To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/mips/include/mipsNN.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/mipsNN.h
diff -u src/sys/arch/mips/include/mipsNN.h:1.11 src/sys/arch/mips/include/mipsNN.h:1.12
--- src/sys/arch/mips/include/mipsNN.h:1.11	Fri Jul 31 03:35:05 2020
+++ src/sys/arch/mips/include/mipsNN.h	Sun Aug  2 23:20:25 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: mipsNN.h,v 1.11 2020/07/31 03:35:05 simonb Exp $	*/
+/*	$NetBSD: mipsNN.h,v 1.12 2020/08/02 23:20:25 simonb Exp $	*/
 
 /*
  * Copyright 2000, 2001
@@ -473,6 +473,48 @@
 
 
 /*
+ * Values in PerfCntCrl Register (CP0 Register 25, Selects 0, 2, 4, 6)
+ */
+
+/* "M" (R): next PerCntCtl register present. */
+#define	MIPSNN_PERFCTL_M__BIT(31)
+
+/* "W" (R): Width - is a 64-bit counter. */
+#define	MIPSNN_PERFCTL_W__BIT(30)
+
+/* "Impl" (RAZ): Impl - implementation dependent field. */
+#define	MIPSNN_PERFCTL_IMPL__BITS(29,25)
+
+/* "EC" (Z): Reserved for Virtualisation Mode. */
+#define	MIPSNN_PERFCTL_EC__BITS(24,23)
+
+/* "PCTD" (RW): Performance Counter Trace Disable. */
+#define	MIPSNN_PERFCTL_PCTD__BIT(15)
+
+/*
+ * "EVENT" (RW): Event number.  Note: The MIPS32/MIPS64 PRA specs define
+ * EventExt from 14:11 and Event from 10:5.  For ease of use, we define a
+ * single 10 bit Event field.
+ */
+#define	MIPSNN_PERFCTL_EVENT__BITS(14,5)
+
+/* "IE" (RW): Interrupt Enable. */
+#define	MIPSNN_PERFCTL_IE__BIT(4)
+
+/* "U" (RW): Enables event counting in user mode. */
+#define	MIPSNN_PERFCTL_U__BIT(3)
+
+/* "S" (RW): Enables event counting in supervisor mode. */
+#define	MIPSNN_PERFCTL_S__BIT(2)
+
+/* "K" (RW): Enables event counting in kernel mode. */
+#define	MIPSNN_PERFCTL_K__BIT(1)
+
+/* "EXL" (RW): Enables event counting when EXL bit in Status is one. */
+#define	MIPSNN_PERFCTL_EXL__BIT(0)
+
+
+/*
  * Values in Configuration Register 6 (CP0 Register 16, Select 6)
  * for RMI XLP processors
  */

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Sun Aug  2 23:04:23 UTC 2020

Modified Files:
src/sys/arch/mips/include: cpuregs.h

Log Message:
Add a few more perfcnt CP0 registers.


To generate a diff of this commit:
cvs rdiff -u -r1.107 -r1.108 src/sys/arch/mips/include/cpuregs.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/cpuregs.h
diff -u src/sys/arch/mips/include/cpuregs.h:1.107 src/sys/arch/mips/include/cpuregs.h:1.108
--- src/sys/arch/mips/include/cpuregs.h:1.107	Fri Jul 31 02:56:48 2020
+++ src/sys/arch/mips/include/cpuregs.h	Sun Aug  2 23:04:23 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpuregs.h,v 1.107 2020/07/31 02:56:48 simonb Exp $	*/
+/*	$NetBSD: cpuregs.h,v 1.108 2020/08/02 23:04:23 simonb Exp $	*/
 
 /*
  * Copyright (c) 2009 Miodrag Vallat.
@@ -547,6 +547,10 @@
  * 25/1	MIPS_COP_0_PERFCNT0_CNT	..ii Performance Counter 0 value register.
  * 25/2	MIPS_COP_0_PERFCNT1_CTL	..ii Performance Counter 1 control register.
  * 25/3	MIPS_COP_0_PERFCNT1_CNT	..ii Performance Counter 1 value register.
+ * 25/4	MIPS_COP_0_PERFCNT0_CTL	..ii Performance Counter 2 control register.
+ * 25/5	MIPS_COP_0_PERFCNT0_CNT	..ii Performance Counter 2 value register.
+ * 25/6	MIPS_COP_0_PERFCNT1_CTL	..ii Performance Counter 3 control register.
+ * 25/7	MIPS_COP_0_PERFCNT1_CNT	..ii Performance Counter 3 value register.
  * 26	MIPS_COP_0_ECC		.3ii ECC / Error Control register.
  * 27	MIPS_COP_0_CACHE_ERR	.3ii Cache Error register.
  * 27	MIPS_COP_0_CACHE_ERR_I	...6 [CAVIUM] Cache Error register (instr).
@@ -657,6 +661,10 @@
 #define	MIPS_COP_0_PERFCNT0_CNT	_(25), 1
 #define	MIPS_COP_0_PERFCNT1_CTL	_(25), 2
 #define	MIPS_COP_0_PERFCNT1_CNT	_(25), 3
+#define	MIPS_COP_0_PERFCNT2_CTL	_(25), 4
+#define	MIPS_COP_0_PERFCNT2_CNT	_(25), 5
+#define	MIPS_COP_0_PERFCNT3_CTL	_(25), 6
+#define	MIPS_COP_0_PERFCNT3_CNT	_(25), 7
 #define	MIPS_COP_0_DATA_LO	_(28), 1
 #define	MIPS_COP_0_DATA_HI	_(29), 3
 #define	MIPS_COP_0_DATA_HI_DATA	_(29)

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Fri Jul 31 08:54:09 UTC 2020

Modified Files:
src/sys/arch/mips/include: locore.h

Log Message:
Fix a tyop.  Thankfully this #define was unused.


To generate a diff of this commit:
cvs rdiff -u -r1.112 -r1.113 src/sys/arch/mips/include/locore.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/locore.h
diff -u src/sys/arch/mips/include/locore.h:1.112 src/sys/arch/mips/include/locore.h:1.113
--- src/sys/arch/mips/include/locore.h:1.112	Fri Jul 31 03:03:04 2020
+++ src/sys/arch/mips/include/locore.h	Fri Jul 31 08:54:09 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.112 2020/07/31 03:03:04 simonb Exp $ */
+/* $NetBSD: locore.h,v 1.113 2020/07/31 08:54:09 simonb Exp $ */
 
 /*
  * This file should not be included by MI code!!!
@@ -806,7 +806,7 @@ void mips_machdep_cache_config(void);
 #define	TF_RA		_R_RA
 #define	TF_SR		_R_SR
 #define	TF_MULLO	_R_MULLO
-#define	TF_MULHI	_R_MULLO
+#define	TF_MULHI	_R_MULHI
 #define	TF_EPC		_R_PC		/* may be changed by trap() call */
 
 #define	TF_NREGS	(sizeof(struct reg) / sizeof(mips_reg_t))

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Fri Jul 31 03:35:05 UTC 2020

Modified Files:
src/sys/arch/mips/include: mipsNN.h

Log Message:
Rename MIPSNN_CFG4_MMU_EXT_DEF_MMU_SIZE_EXT to MIPSNN_CFG4_MMU_SIZE_EXT.


To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/mips/include/mipsNN.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/mipsNN.h
diff -u src/sys/arch/mips/include/mipsNN.h:1.10 src/sys/arch/mips/include/mipsNN.h:1.11
--- src/sys/arch/mips/include/mipsNN.h:1.10	Fri Jul 31 02:34:38 2020
+++ src/sys/arch/mips/include/mipsNN.h	Fri Jul 31 03:35:05 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: mipsNN.h,v 1.10 2020/07/31 02:34:38 simonb Exp $	*/
+/*	$NetBSD: mipsNN.h,v 1.11 2020/07/31 03:35:05 simonb Exp $	*/
 
 /*
  * Copyright 2000, 2001
@@ -324,7 +324,7 @@
 #define	  MIPSNN_CFG4_MMU_EXT_DEF_VTLB			  3
 
 /* "MMUSizeExt" (R): Extension of Config1[MMUSize-1] field. */
-#define	MIPSNN_CFG4_MMU_EXT_DEF_MMU_SIZE_EXT		__BITS(7,0)
+#define	MIPSNN_CFG4_MMU_SIZE_EXT		__BITS(7,0)
 
 /* "FTLBPageSize" (R/RW): Indicates the Page Size of the FTLB Array Entries. */
 #define	MIPSNN_CFG4_FTLB_FTLB_PAGE_SIZE		__BITS(10,8)

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Fri Jul 31 03:03:04 UTC 2020

Modified Files:
src/sys/arch/mips/include: locore.h

Log Message:
CP0 Config6 and Config7 aren't probeable.  Adjust comments for these two.


To generate a diff of this commit:
cvs rdiff -u -r1.111 -r1.112 src/sys/arch/mips/include/locore.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/locore.h
diff -u src/sys/arch/mips/include/locore.h:1.111 src/sys/arch/mips/include/locore.h:1.112
--- src/sys/arch/mips/include/locore.h:1.111	Mon Jul 27 08:25:28 2020
+++ src/sys/arch/mips/include/locore.h	Fri Jul 31 03:03:04 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.111 2020/07/27 08:25:28 skrll Exp $ */
+/* $NetBSD: locore.h,v 1.112 2020/07/31 03:03:04 simonb Exp $ */
 
 /*
  * This file should not be included by MI code!!!
@@ -876,8 +876,8 @@ struct pridtab {
 #define	 MIPS_CP0FL_CONFIG3	__BIT(9)  /* XXX probeable - shouldn't be hard coded */
 #define	 MIPS_CP0FL_CONFIG4	__BIT(10) /* XXX probeable - shouldn't be hard coded */
 #define	 MIPS_CP0FL_CONFIG5	__BIT(11) /* XXX probeable - shouldn't be hard coded */
-#define	 MIPS_CP0FL_CONFIG6	__BIT(12) /* XXX probeable - shouldn't be hard coded */
-#define	 MIPS_CP0FL_CONFIG7	__BIT(13) /* XXX probeable - shouldn't be hard coded */
+#define	 MIPS_CP0FL_CONFIG6	__BIT(12)
+#define	 MIPS_CP0FL_CONFIG7	__BIT(13)
 
 /*
  * cpu_cidflags defines, by company

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Fri Jul 31 02:56:49 UTC 2020

Modified Files:
src/sys/arch/mips/include: cpuregs.h

Log Message:
Add two cnMIPS III COP0 register names.


To generate a diff of this commit:
cvs rdiff -u -r1.106 -r1.107 src/sys/arch/mips/include/cpuregs.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/cpuregs.h
diff -u src/sys/arch/mips/include/cpuregs.h:1.106 src/sys/arch/mips/include/cpuregs.h:1.107
--- src/sys/arch/mips/include/cpuregs.h:1.106	Wed Jul 29 09:00:05 2020
+++ src/sys/arch/mips/include/cpuregs.h	Fri Jul 31 02:56:48 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpuregs.h,v 1.106 2020/07/29 09:00:05 simonb Exp $	*/
+/*	$NetBSD: cpuregs.h,v 1.107 2020/07/31 02:56:48 simonb Exp $	*/
 
 /*
  * Copyright (c) 2009 Miodrag Vallat.
@@ -529,7 +529,9 @@
  * 16/4	MIPS_COP_0_CONFIG4	..33 Configuration register 6.
  * 16/5	MIPS_COP_0_CONFIG5	..33 Configuration register 7.
  * 16/6	MIPS_COP_0_CONFIG6	..33 Configuration register 6.
+ * 16/6	MIPS_COP_0_CVMMEMCTL2	...6 [CAVIUM] CvmMemCtl2 register.
  * 16/7	MIPS_COP_0_CONFIG7	..33 Configuration register 7.
+ * 16/7	MIPS_COP_0_CVMVMCONFIG	...6 [CAVIUM] CvmVMConfig register.
  * 17	MIPS_COP_0_LLADDR	.336 Load Linked Address.
  * 18	MIPS_COP_0_WATCH_LO	.336 WatchLo register.
  * 18/1	MIPS_COP_0_WATCH_LO2	..ii WatchLo 1 register.
@@ -643,7 +645,9 @@
 #define	MIPS_COP_0_CONFIG4	_(16), 4
 #define	MIPS_COP_0_CONFIG5	_(16), 5
 #define	MIPS_COP_0_CONFIG6	_(16), 6
+#define	MIPS_COP_0_CVMMEMCTL2	_(16), 6	/* CAVIUM */
 #define	MIPS_COP_0_CONFIG7	_(16), 7
+#define	MIPS_COP_0_CVMVMCONFIG	_(16), 7	/* CAVIUM */
 #define	MIPS_COP_0_OSSCRATCH	_(22)		/* RMI */
 #define	MIPS_COP_0_DIAG		_(22)		/* LOONGSON2 */
 #define	MIPS_COP_0_MCD		_(22)		/* CAVIUM */

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Fri Jul 31 02:34:38 UTC 2020

Modified Files:
src/sys/arch/mips/include: mipsNN.h

Log Message:
Bit definitions Config4 and Config5 registers.


To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/mips/include/mipsNN.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/mipsNN.h
diff -u src/sys/arch/mips/include/mipsNN.h:1.9 src/sys/arch/mips/include/mipsNN.h:1.10
--- src/sys/arch/mips/include/mipsNN.h:1.9	Sun Jul 26 08:08:41 2020
+++ src/sys/arch/mips/include/mipsNN.h	Fri Jul 31 02:34:38 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: mipsNN.h,v 1.9 2020/07/26 08:08:41 simonb Exp $	*/
+/*	$NetBSD: mipsNN.h,v 1.10 2020/07/31 02:34:38 simonb Exp $	*/
 
 /*
  * Copyright 2000, 2001
@@ -256,7 +256,7 @@
 /* "MCU" (R): MCU ASE extension present. */
 #define	MIPSNN_CFG3_MCU		0x0002
 
-/* "ISAOnExc" (R): ISA used on exception. */
+/* "ISAOnExc" (R/RW): ISA used on exception. */
 #define	MIPSNN_CFG3_ISAOnExc	0x0001	/* microMIPS used on entrance to exception vector */
 
 /* "ISA" (R): Instruction Set Availability. */
@@ -299,6 +299,180 @@
 #define	MIPSNN_CFG3_TL		0x0001
 
 /*
+ * Values in Configuration Register 4 (CP0 Register 16, Select 4)
+ */
+
+/* "M" (R): Configuration Register 5 present. */
+#define	MIPSNN_CFG4_M	__BIT(31)
+
+/* "IE" (R): TLB invalidate instruction support/configuration. */
+#define	MIPSNN_CFG4_IE	__BITS(30,29)
+
+/* "AE" (R): Extend EntryHi[ASID] to 10 bits. */
+#define	MIPSNN_CFG4_AE	__BIT(28)
+
+/* "VTLBSizeExt" (R): TLB invalidate instruction support/configuration. */
+#define	MIPSNN_CFG4_VTLB_SE__BITS(27,24)
+
+/* "KScrExist" (R): Number of kernel mode scratch registers available. */
+#define	MIPSNN_CFG4_KSCR_EXIST__BITS(23,16)
+
+/* "MMUExtDef" (R): MMU extension definition. */
+#define	MIPSNN_CFG4_MMU_EXT_DEF__BITS(15,14)
+#define	  MIPSNN_CFG4_MMU_EXT_DEF_MMU			  1
+#define	  MIPSNN_CFG4_MMU_EXT_DEF_FLTB			  2
+#define	  MIPSNN_CFG4_MMU_EXT_DEF_VTLB			  3
+
+/* "MMUSizeExt" (R): Extension of Config1[MMUSize-1] field. */
+#define	MIPSNN_CFG4_MMU_EXT_DEF_MMU_SIZE_EXT		__BITS(7,0)
+
+/* "FTLBPageSize" (R/RW): Indicates the Page Size of the FTLB Array Entries. */
+#define	MIPSNN_CFG4_FTLB_FTLB_PAGE_SIZE		__BITS(10,8)
+#define	  MIPSNN_CFG4_FTLB_FTLB_PAGE_SIZE_1K	  0
+#define	  MIPSNN_CFG4_FTLB_FTLB_PAGE_SIZE_4K	  1
+#define	  MIPSNN_CFG4_FTLB_FTLB_PAGE_SIZE_16K	  2
+#define	  MIPSNN_CFG4_FTLB_FTLB_PAGE_SIZE_64K	  3
+#define	  MIPSNN_CFG4_FTLB_FTLB_PAGE_SIZE_256K	  4
+#define	  MIPSNN_CFG4_FTLB_FTLB_PAGE_SIZE_1G	  5
+#define	  MIPSNN_CFG4_FTLB_FTLB_PAGE_SIZE_4G	  6
+/* "FTLBWays" (R): Indicates the Set Associativity of the FTLB Array. */
+#define	MIPSNN_CFG4_FTLB_FTLB_WAYS		__BITS(7,4)
+#define	  MIPSNN_CFG4_FTLB_FTLB_WAYS_2		  0
+#define	  MIPSNN_CFG4_FTLB_FTLB_WAYS_3		  1
+#define	  MIPSNN_CFG4_FTLB_FTLB_WAYS_4		  2
+#define	  MIPSNN_CFG4_FTLB_FTLB_WAYS_5		  3
+#define	  MIPSNN_CFG4_FTLB_FTLB_WAYS_6		  4
+#define	  MIPSNN_CFG4_FTLB_FTLB_WAYS_7		  5
+#define	  MIPSNN_CFG4_FTLB_FTLB_WAYS_8		  6
+/* "FTLBSets" (R): Indicates the number of Set per Way within the FTLB Array. */
+#define	MIPSNN_CFG4_FTLB_FTLB_SETS		__BITS(3,0)
+#define	  MIPSNN_CFG4_FTLB_FTLB_SETS_1		  0
+#define	  MIPSNN_CFG4_FTLB_FTLB_SETS_2		  1
+#define	  MIPSNN_CFG4_FTLB_FTLB_SETS_4		  2
+#define	  MIPSNN_CFG4_FTLB_FTLB_SETS_8		  3
+#define	  MIPSNN_CFG4_FTLB_FTLB_SETS_16		  4
+#define	  MIPSNN_CFG4_FTLB_FTLB_SETS_32		  5
+#define	  MIPSNN_CFG4_FTLB_FTLB_SETS_64		  6
+#define	  MIPSNN_CFG4_FTLB_FTLB_SETS_128	  7
+#define	  MIPSNN_CFG4_FTLB_FTLB_SETS_256	  8
+#define	  MIPSNN_CFG4_FTLB_FTLB_SETS_512	  9
+#define	  MIPSNN_CFG4_FTLB_FTLB_SETS_1024	  10
+#define	  MIPSNN_CFG4_FTLB_FTLB_SETS_2048	  11
+#define	  MIPSNN_CFG4_FTLB_FTLB_SETS_4096	  12
+#define	  MIPSNN_CFG4_FTLB_FTLB_SETS_8192	  13
+#define	  MIPSNN_CFG4_FTLB_FTLB_SETS_16384	  14
+#define	  MIPSNN_CFG4_FTLB_FTLB_SETS_32768	  15
+
+/* "MMUSizeExt" (R): Extension of Config1[MMUSize-1] field. */
+#define	MIPSNN_CFG4_FVTLB_VTLB_SIZE_EXT		__BITS(27,24)
+/* "FTLBPageSize" (R/RW): Indicates the Page Size of the FTLB Array Entries. */
+#define	MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE	__BITS(12,8)
+#define	  MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_1K	  0
+#define	  MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_4K	  1
+#define	  MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_16K	  2
+#define	  MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_64K	  3
+#define	  MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_256K	  4
+#define	  MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_1M	  5
+#define	  MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_4M	  6
+#define	  MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_16M	  7
+#define	  MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_64M	  8
+#define	  MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_256M	  9
+#define	  MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_1G	  10
+#define	  MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_4G	  11
+#define	  MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_16G	  12

CVS commit: src/sys/arch/mips/include

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Thu Jul 30 06:54:07 UTC 2020

Modified Files:
src/sys/arch/mips/include: types.h

Log Message:
Sort the #define __HAVEs. NFCI.


To generate a diff of this commit:
cvs rdiff -u -r1.70 -r1.71 src/sys/arch/mips/include/types.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/types.h
diff -u src/sys/arch/mips/include/types.h:1.70 src/sys/arch/mips/include/types.h:1.71
--- src/sys/arch/mips/include/types.h:1.70	Thu Apr 30 20:48:10 2020
+++ src/sys/arch/mips/include/types.h	Thu Jul 30 06:54:07 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: types.h,v 1.70 2020/04/30 20:48:10 skrll Exp $	*/
+/*	$NetBSD: types.h,v 1.71 2020/07/30 06:54:07 skrll Exp $	*/
 
 /*-
  * Copyright (c) 1992, 1993
@@ -142,28 +142,32 @@ typedef __uint32_t tlb_asid_t;
 #define	PCU_UNIT_COUNT	2
 #endif
 
-
 #define	__SIMPLELOCK_LOCKED	1
 #define	__SIMPLELOCK_UNLOCKED	0
 
-#define	__HAVE_FAST_SOFTINTS
-#define	__HAVE_SYSCALL_INTERN
-#define	__HAVE_CPU_LWP_SETPRIVATE
-#define	__HAVE_CPU_DATA_FIRST
-#define	__HAVE_MD_CPU_OFFLINE
+#define	__HAVE_COMMON___TLS_GET_ADDR
 #define	__HAVE_CPU_COUNTER
+#define	__HAVE_CPU_DATA_FIRST
+#define	__HAVE_CPU_LWP_SETPRIVATE
 #define	__HAVE_CPU_UAREA_ROUTINES
-#define	__HAVE_COMMON___TLS_GET_ADDR
+#define	__HAVE_FAST_SOFTINTS
+#define	__HAVE_MD_CPU_OFFLINE
+#define	__HAVE_MM_MD_DIRECT_MAPPED_PHYS
+#define	__HAVE_MM_MD_KERNACC
+#define	__HAVE_MM_MD_CACHE_ALIASING
+#define	__HAVE_SYSCALL_INTERN
+#define	__HAVE_TLS_VARIANT_I
+#define	__HAVE_UCAS_FULL
 #define	__HAVE___LWP_GETTCB_FAST
 #define	__HAVE___LWP_SETTCB
-#define	__HAVE_TLS_VARIANT_I
+
+/* XXX temporary */
+#define	__HAVE_UNLOCKED_PMAP
 
 #if !defined(__mips_o32)
 #define	__HAVE_ATOMIC64_OPS
 #endif
 
-#define	__HAVE_UCAS_FULL
-
 #if defined(_KERNEL)
 #define	__HAVE_RAS
 #if defined(_LP64)
@@ -171,11 +175,5 @@ typedef __uint32_t tlb_asid_t;
 #endif
 #endif /* _KERNEL */
 
-#define	__HAVE_MM_MD_DIRECT_MAPPED_PHYS
-#define	__HAVE_MM_MD_KERNACC
-#define	__HAVE_MM_MD_CACHE_ALIASING
-
-/* XXX temporary */
-#define	__HAVE_UNLOCKED_PMAP
 
 #endif	/* _MIPS_TYPES_H_ */

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Wed Jul 29 09:00:05 UTC 2020

Modified Files:
src/sys/arch/mips/include: cpuregs.h

Log Message:
Add definitions for the CP0 WatchLo/WatchHi registers.


To generate a diff of this commit:
cvs rdiff -u -r1.105 -r1.106 src/sys/arch/mips/include/cpuregs.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/cpuregs.h
diff -u src/sys/arch/mips/include/cpuregs.h:1.105 src/sys/arch/mips/include/cpuregs.h:1.106
--- src/sys/arch/mips/include/cpuregs.h:1.105	Sun Jul 26 08:08:41 2020
+++ src/sys/arch/mips/include/cpuregs.h	Wed Jul 29 09:00:05 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpuregs.h,v 1.105 2020/07/26 08:08:41 simonb Exp $	*/
+/*	$NetBSD: cpuregs.h,v 1.106 2020/07/29 09:00:05 simonb Exp $	*/
 
 /*
  * Copyright (c) 2009 Miodrag Vallat.
@@ -842,6 +842,24 @@
 #endif
 
 /*
+ * WatchLo/WatchHi watchpoint registers
+ */
+#define	MIPS_WATCHLO_VADDR32		__BITS(31,3)	/* 32-bit addr */
+#define	MIPS_WATCHLO_VADDR64		__BITS(63,3)	/* 64-bit addr */
+#define	MIPS_WATCHLO_INSN		__BIT(2)
+#define	MIPS_WATCHLO_DATA_READ		__BIT(1)
+#define	MIPS_WATCHLO_DATA_WRITE		__BIT(0)
+
+#define	MIPS_WATCHHI_M			__BIT(31)	/* next watch reg implemented */
+#define	MIPS_WATCHHI_G			__BIT(30)	/* use WatchLo vaddr */
+#define	MIPS_WATCHHI_EAS		__BITS(25,24)	/* extended ASID */
+#define	MIPS_WATCHHI_ASID		__BITS(23,16)
+#define	MIPS_WATCHHI_MASK		__BITS(11,3)
+#define	MIPS_WATCHHI_INSN		MIPS_WATCHLO_INSN
+#define	MIPS_WATCHHI_DATA_READ		MIPS_WATCHLO_DATA_READ
+#define	MIPS_WATCHHI_DATA_WRITE		MIPS_WATCHLO_DATA_WRITE
+
+/*
  * RDHWR register numbers
  */
 #define	MIPS_HWR_CPUNUM			_(0)

CVS commit: src/sys/arch/mips/include

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Mon Jul 27 10:59:11 UTC 2020

Modified Files:
src/sys/arch/mips/include: cache.h

Log Message:
s/MODULE/_MODULE/

spotted by chuq@


To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/mips/include/cache.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/cache.h
diff -u src/sys/arch/mips/include/cache.h:1.15 src/sys/arch/mips/include/cache.h:1.16
--- src/sys/arch/mips/include/cache.h:1.15	Sun Jul 26 08:08:41 2020
+++ src/sys/arch/mips/include/cache.h	Mon Jul 27 10:59:10 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: cache.h,v 1.15 2020/07/26 08:08:41 simonb Exp $	*/
+/*	$NetBSD: cache.h,v 1.16 2020/07/27 10:59:10 skrll Exp $	*/
 
 /*
  * Copyright 2001 Wasabi Systems, Inc.
@@ -228,7 +228,7 @@ struct mips_cache_info {
 
 #if (MIPS1 + MIPS64_RMIXL + MIPS64R2_RMIXL + MIPS64_OCTEON) > 0 && \
 (MIPS3 + MIPS4) == 0 \
- && !defined(MODULE)
+ && !defined(_MODULE)
 #define	MIPS_CACHE_ALIAS_MASK		0
 #define	MIPS_CACHE_VIRTUAL_ALIAS	false
 #else

CVS commit: src/sys/arch/mips/include

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Mon Jul 27 08:25:28 UTC 2020

Modified Files:
src/sys/arch/mips/include: locore.h

Log Message:
Fix typo _MODULAR -> _MODULE.  Hopefully this fixes the builds.


To generate a diff of this commit:
cvs rdiff -u -r1.110 -r1.111 src/sys/arch/mips/include/locore.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/locore.h
diff -u src/sys/arch/mips/include/locore.h:1.110 src/sys/arch/mips/include/locore.h:1.111
--- src/sys/arch/mips/include/locore.h:1.110	Sun Jul 26 08:08:41 2020
+++ src/sys/arch/mips/include/locore.h	Mon Jul 27 08:25:28 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.110 2020/07/26 08:08:41 simonb Exp $ */
+/* $NetBSD: locore.h,v 1.111 2020/07/27 08:25:28 skrll Exp $ */
 
 /*
  * This file should not be included by MI code!!!
@@ -28,7 +28,7 @@
 #ifndef _MIPS_LOCORE_H
 #define	_MIPS_LOCORE_H
 
-#if defined(_KERNEL_OPT)
+#if !defined(_MODULE) && defined(_KERNEL_OPT)
 #include "opt_cputype.h"
 #endif
 
@@ -51,8 +51,8 @@ typedef uint32_t pt_entry_t;
 
 #ifdef _KERNEL
 
-#if defined(_MODULAR) || defined(_STANDALONE)
-/* Assume all CPU architectures are valid for LKM's and standlone progs */
+#if defined(_MODULE) || defined(_STANDALONE)
+/* Assume all CPU architectures are valid for modules and standlone progs */
 #if !defined(__mips_n32) && !defined(__mips_n64)
 #define	MIPS1		1
 #endif
@@ -64,7 +64,7 @@ typedef uint32_t pt_entry_t;
 #endif
 #define	MIPS64		1
 #define	MIPS64R2	1
-#endif /* _MODULAR || _STANDALONE */
+#endif /* _MODULE || _STANDALONE */
 
 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 0
 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32, MIPS32R2, MIPS64, or MIPS64R2 must be specified

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Sun Jul 26 08:08:41 UTC 2020

Modified Files:
src/sys/arch/mips/include: asm.h bswap.h bus_dma_defs.h
bus_space_defs.h bus_space_funcs.h cache.h cache_ls2.h
cache_mipsNN.h cache_octeon.h cache_r4k.h cache_r5900.h cache_r5k.h
cachectl.h cdefs.h cpu.h cpu_counter.h cpuregs.h db_machdep.h
ecoff_machdep.h fenv.h float.h frame.h ieeefp.h int_const.h
int_fmtio.h int_limits.h int_mwgwtypes.h intr.h isa_machdep.h
kcore.h kdbparam.h limits.h locore.h math.h mcontext.h mips1_pte.h
mips3_pte.h mipsNN.h mips_opcode.h mips_param.h netbsd32_machdep.h
pci_machdep.h pmap.h proc.h profile.h pte.h ptrace.h r3900regs.h
reg.h regdef.h regnum.h reloc.h setjmp.h sljit_machdep.h sysarch.h
vmparam.h wchar_limits.h wired_map.h

Log Message:
#define
Nuke trailing whitespace.


To generate a diff of this commit:
cvs rdiff -u -r1.56 -r1.57 src/sys/arch/mips/include/asm.h
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/mips/include/bswap.h \
src/sys/arch/mips/include/bus_dma_defs.h \
src/sys/arch/mips/include/cache_octeon.h
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/mips/include/bus_space_defs.h \
src/sys/arch/mips/include/cache_ls2.h src/sys/arch/mips/include/kcore.h \
src/sys/arch/mips/include/wchar_limits.h \
src/sys/arch/mips/include/wired_map.h
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/mips/include/bus_space_funcs.h \
src/sys/arch/mips/include/sljit_machdep.h
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/mips/include/cache.h
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/mips/include/cache_mipsNN.h \
src/sys/arch/mips/include/cache_r5k.h \
src/sys/arch/mips/include/cpu_counter.h src/sys/arch/mips/include/fenv.h \
src/sys/arch/mips/include/int_const.h \
src/sys/arch/mips/include/netbsd32_machdep.h
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/mips/include/cache_r4k.h
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/mips/include/cache_r5900.h \
src/sys/arch/mips/include/frame.h src/sys/arch/mips/include/int_limits.h \
src/sys/arch/mips/include/reloc.h src/sys/arch/mips/include/setjmp.h
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/mips/include/cachectl.h \
src/sys/arch/mips/include/ieeefp.h src/sys/arch/mips/include/intr.h \
src/sys/arch/mips/include/sysarch.h
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/mips/include/cdefs.h
cvs rdiff -u -r1.128 -r1.129 src/sys/arch/mips/include/cpu.h
cvs rdiff -u -r1.104 -r1.105 src/sys/arch/mips/include/cpuregs.h
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/mips/include/db_machdep.h
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/mips/include/ecoff_machdep.h
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/mips/include/float.h \
src/sys/arch/mips/include/ptrace.h
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/mips/include/int_fmtio.h \
src/sys/arch/mips/include/int_mwgwtypes.h
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/mips/include/isa_machdep.h \
src/sys/arch/mips/include/kdbparam.h src/sys/arch/mips/include/mipsNN.h \
src/sys/arch/mips/include/pci_machdep.h
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/mips/include/limits.h
cvs rdiff -u -r1.109 -r1.110 src/sys/arch/mips/include/locore.h
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/mips/include/math.h \
src/sys/arch/mips/include/r3900regs.h
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/mips/include/mcontext.h
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/mips/include/mips1_pte.h
cvs rdiff -u -r1.29 -r1.30 src/sys/arch/mips/include/mips3_pte.h
cvs rdiff -u -r1.21 -r1.22 src/sys/arch/mips/include/mips_opcode.h \
src/sys/arch/mips/include/profile.h
cvs rdiff -u -r1.44 -r1.45 src/sys/arch/mips/include/mips_param.h
cvs rdiff -u -r1.71 -r1.72 src/sys/arch/mips/include/pmap.h
cvs rdiff -u -r1.28 -r1.29 src/sys/arch/mips/include/proc.h
cvs rdiff -u -r1.25 -r1.26 src/sys/arch/mips/include/pte.h
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/mips/include/reg.h
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/mips/include/regdef.h
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/mips/include/regnum.h
cvs rdiff -u -r1.62 -r1.63 src/sys/arch/mips/include/vmparam.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/asm.h
diff -u src/sys/arch/mips/include/asm.h:1.56 src/sys/arch/mips/include/asm.h:1.57
--- src/sys/arch/mips/include/asm.h:1.56	Fri Apr 17 14:19:43 2020
+++ src/sys/arch/mips/include/asm.h	Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: asm.h,v 1.56 2020/04/17 14:19:43 joerg Exp $	*/
+/*	$NetBSD: asm.h,v 1.57 2020/07/26 08:08:41 simonb Exp $	*/
 
 /*
  * Copyright (c) 1992, 1993
@@ -267,7 +267,7 @@ _C_LABEL(x):
 	.asciz str;			\
 	.align	3
 
-#define RCSID(x)	.pushsection ".ident","MS",@progbits,1;		\
+#define	RCSID(x)	.pushsection ".ident","MS",@progbits,1;		\
 			.asciz x;	\
 			.popsection
 
@@ -515,9 +515,9 @@ _C_LABEL(x):
 
 /* CPU dependent hook for cp0 load delays */
 #if defined(MIPS1) || 

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Sun Jul 26 07:52:08 UTC 2020

Modified Files:
src/sys/arch/mips/include: cpuregs.h

Log Message:
Add CP0 Config Registers 6 and 7.


To generate a diff of this commit:
cvs rdiff -u -r1.103 -r1.104 src/sys/arch/mips/include/cpuregs.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/cpuregs.h
diff -u src/sys/arch/mips/include/cpuregs.h:1.103 src/sys/arch/mips/include/cpuregs.h:1.104
--- src/sys/arch/mips/include/cpuregs.h:1.103	Sun Jul 26 07:46:21 2020
+++ src/sys/arch/mips/include/cpuregs.h	Sun Jul 26 07:52:07 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpuregs.h,v 1.103 2020/07/26 07:46:21 simonb Exp $	*/
+/*	$NetBSD: cpuregs.h,v 1.104 2020/07/26 07:52:07 simonb Exp $	*/
 
 /*
  * Copyright (c) 2009 Miodrag Vallat.
@@ -642,6 +642,8 @@
 #define MIPS_COP_0_CONFIG3	_(16), 3
 #define MIPS_COP_0_CONFIG4	_(16), 4
 #define MIPS_COP_0_CONFIG5	_(16), 5
+#define MIPS_COP_0_CONFIG6	_(16), 6
+#define MIPS_COP_0_CONFIG7	_(16), 7
 #define	MIPS_COP_0_OSSCRATCH	_(22)		/* RMI */
 #define	MIPS_COP_0_DIAG		_(22)		/* LOONGSON2 */
 #define	MIPS_COP_0_MCD		_(22)		/* CAVIUM */

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Sun Jul 26 07:13:51 UTC 2020

Modified Files:
src/sys/arch/mips/include: mips_param.h

Log Message:
Add a space in a comment.


To generate a diff of this commit:
cvs rdiff -u -r1.43 -r1.44 src/sys/arch/mips/include/mips_param.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/mips_param.h
diff -u src/sys/arch/mips/include/mips_param.h:1.43 src/sys/arch/mips/include/mips_param.h:1.44
--- src/sys/arch/mips/include/mips_param.h:1.43	Thu Jul 23 15:24:37 2020
+++ src/sys/arch/mips/include/mips_param.h	Sun Jul 26 07:13:51 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: mips_param.h,v 1.43 2020/07/23 15:24:37 skrll Exp $	*/
+/*	$NetBSD: mips_param.h,v 1.44 2020/07/26 07:13:51 simonb Exp $	*/
 
 /*-
  * Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -82,7 +82,7 @@
 
 /*
  * Most MIPS have a cache line size of 32 bytes, but Cavium chips
- * have a line size 128bytes and we need to cover the larger size.
+ * have a line size 128 bytes and we need to cover the larger size.
  */
 #define COHERENCY_UNIT	128
 #define CACHE_LINE_SIZE	128

CVS commit: src/sys/arch/mips/include

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Thu Jul 23 19:22:13 UTC 2020

Modified Files:
src/sys/arch/mips/include: locore.h

Log Message:
unifdef -U_LKM


To generate a diff of this commit:
cvs rdiff -u -r1.108 -r1.109 src/sys/arch/mips/include/locore.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/locore.h
diff -u src/sys/arch/mips/include/locore.h:1.108 src/sys/arch/mips/include/locore.h:1.109
--- src/sys/arch/mips/include/locore.h:1.108	Thu Jul 23 19:20:02 2020
+++ src/sys/arch/mips/include/locore.h	Thu Jul 23 19:22:13 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.108 2020/07/23 19:20:02 skrll Exp $ */
+/* $NetBSD: locore.h,v 1.109 2020/07/23 19:22:13 skrll Exp $ */
 
 /*
  * This file should not be included by MI code!!!
@@ -28,7 +28,7 @@
 #ifndef _MIPS_LOCORE_H
 #define _MIPS_LOCORE_H
 
-#if !defined(_LKM) && defined(_KERNEL_OPT)
+#if defined(_KERNEL_OPT)
 #include "opt_cputype.h"
 #endif
 
@@ -51,7 +51,7 @@ typedef uint32_t pt_entry_t;
 
 #ifdef _KERNEL
 
-#if defined(_MODULAR) || defined(_LKM) || defined(_STANDALONE)
+#if defined(_MODULAR) || defined(_STANDALONE)
 /* Assume all CPU architectures are valid for LKM's and standlone progs */
 #if !defined(__mips_n32) && !defined(__mips_n64)
 #define	MIPS1		1
@@ -64,7 +64,7 @@ typedef uint32_t pt_entry_t;
 #endif
 #define	MIPS64		1
 #define	MIPS64R2	1
-#endif /* _MODULAR || _LKM || _STANDALONE */
+#endif /* _MODULAR || _STANDALONE */
 
 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 0
 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32, MIPS32R2, MIPS64, or MIPS64R2 must be specified

CVS commit: src/sys/arch/mips/include

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Thu Jul 23 19:20:03 UTC 2020

Modified Files:
src/sys/arch/mips/include: locore.h

Log Message:
Trailing whitespace


To generate a diff of this commit:
cvs rdiff -u -r1.107 -r1.108 src/sys/arch/mips/include/locore.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/locore.h
diff -u src/sys/arch/mips/include/locore.h:1.107 src/sys/arch/mips/include/locore.h:1.108
--- src/sys/arch/mips/include/locore.h:1.107	Sun Jun 14 06:50:31 2020
+++ src/sys/arch/mips/include/locore.h	Thu Jul 23 19:20:02 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.107 2020/06/14 06:50:31 simonb Exp $ */
+/* $NetBSD: locore.h,v 1.108 2020/07/23 19:20:02 skrll Exp $ */
 
 /*
  * This file should not be included by MI code!!!
@@ -402,7 +402,7 @@ struct mips_jump_fixup_info {
 	uint32_t jfi_stub;
 	uint32_t jfi_real;
 };
- 
+
 void	fixup_splcalls(void);/* splstubs.c */
 bool	mips_fixup_exceptions(mips_fixup_callback_t, void *);
 bool	mips_fixup_zero_relative(int32_t, uint32_t [2], void *);

CVS commit: src/sys/arch/mips/include

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Thu Jul 23 15:24:37 UTC 2020

Modified Files:
src/sys/arch/mips/include: mips_param.h

Log Message:
Add a comment to CACHE_LINE_SIZE / COHERENCY_UNIT size defines


To generate a diff of this commit:
cvs rdiff -u -r1.42 -r1.43 src/sys/arch/mips/include/mips_param.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/mips_param.h
diff -u src/sys/arch/mips/include/mips_param.h:1.42 src/sys/arch/mips/include/mips_param.h:1.43
--- src/sys/arch/mips/include/mips_param.h:1.42	Thu Jul 23 12:15:59 2020
+++ src/sys/arch/mips/include/mips_param.h	Thu Jul 23 15:24:37 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: mips_param.h,v 1.42 2020/07/23 12:15:59 skrll Exp $	*/
+/*	$NetBSD: mips_param.h,v 1.43 2020/07/23 15:24:37 skrll Exp $	*/
 
 /*-
  * Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -80,6 +80,10 @@
 #define MSGBUFSIZE	NBPG		/* default message buffer size */
 #endif
 
+/*
+ * Most MIPS have a cache line size of 32 bytes, but Cavium chips
+ * have a line size 128bytes and we need to cover the larger size.
+ */
 #define COHERENCY_UNIT	128
 #define CACHE_LINE_SIZE	128
 

CVS commit: src/sys/arch/mips/include

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Thu Jul 23 12:15:59 UTC 2020

Modified Files:
src/sys/arch/mips/include: mips_param.h

Log Message:
On second thoughts this can't be conditional so define CACHE_LINE_SIZE /
COHERENCY_UNIT as 128 for all mips.


To generate a diff of this commit:
cvs rdiff -u -r1.41 -r1.42 src/sys/arch/mips/include/mips_param.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/mips_param.h
diff -u src/sys/arch/mips/include/mips_param.h:1.41 src/sys/arch/mips/include/mips_param.h:1.42
--- src/sys/arch/mips/include/mips_param.h:1.41	Thu Jul 23 12:13:25 2020
+++ src/sys/arch/mips/include/mips_param.h	Thu Jul 23 12:15:59 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: mips_param.h,v 1.41 2020/07/23 12:13:25 skrll Exp $	*/
+/*	$NetBSD: mips_param.h,v 1.42 2020/07/23 12:15:59 skrll Exp $	*/
 
 /*-
  * Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -80,13 +80,8 @@
 #define MSGBUFSIZE	NBPG		/* default message buffer size */
 #endif
 
-#ifdef MIPS64_OCTEON
 #define COHERENCY_UNIT	128
 #define CACHE_LINE_SIZE	128
-#endif
-#ifndef COHERENCY_UNIT
-#define COHERENCY_UNIT	32	/* MIPS cachelines are usually 32 bytes */
-#endif
 
 #ifdef ENABLE_MIPS_16KB_PAGE
 #define	PGSHIFT		14		/* LOG2(NBPG) */

CVS commit: src/sys/arch/mips/include

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Thu Jul 23 12:13:25 UTC 2020

Modified Files:
src/sys/arch/mips/include: mips_param.h

Log Message:
Define CACHE_LINE_SIZE / COHERENCY_UNIT as 128 for MIPS64_OCTEON


To generate a diff of this commit:
cvs rdiff -u -r1.40 -r1.41 src/sys/arch/mips/include/mips_param.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/mips_param.h
diff -u src/sys/arch/mips/include/mips_param.h:1.40 src/sys/arch/mips/include/mips_param.h:1.41
--- src/sys/arch/mips/include/mips_param.h:1.40	Wed Jun 19 09:55:27 2019
+++ src/sys/arch/mips/include/mips_param.h	Thu Jul 23 12:13:25 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: mips_param.h,v 1.40 2019/06/19 09:55:27 skrll Exp $	*/
+/*	$NetBSD: mips_param.h,v 1.41 2020/07/23 12:13:25 skrll Exp $	*/
 
 /*-
  * Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -80,6 +80,10 @@
 #define MSGBUFSIZE	NBPG		/* default message buffer size */
 #endif
 
+#ifdef MIPS64_OCTEON
+#define COHERENCY_UNIT	128
+#define CACHE_LINE_SIZE	128
+#endif
 #ifndef COHERENCY_UNIT
 #define COHERENCY_UNIT	32	/* MIPS cachelines are usually 32 bytes */
 #endif

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Mon Jul 20 03:17:44 UTC 2020

Modified Files:
src/sys/arch/mips/include: cpuregs.h

Log Message:
Expose the width of the MIPS_EBASE_CPUNUM bitfield for asm code.


To generate a diff of this commit:
cvs rdiff -u -r1.101 -r1.102 src/sys/arch/mips/include/cpuregs.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/cpuregs.h
diff -u src/sys/arch/mips/include/cpuregs.h:1.101 src/sys/arch/mips/include/cpuregs.h:1.102
--- src/sys/arch/mips/include/cpuregs.h:1.101	Mon Jul 20 01:10:38 2020
+++ src/sys/arch/mips/include/cpuregs.h	Mon Jul 20 03:17:44 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpuregs.h,v 1.101 2020/07/20 01:10:38 simonb Exp $	*/
+/*	$NetBSD: cpuregs.h,v 1.102 2020/07/20 03:17:44 simonb Exp $	*/
 
 /*
  * Copyright (c) 2009 Miodrag Vallat.
@@ -836,6 +836,7 @@
 #define	MIPS_EBASE_EXC_BASE_SHIFT	12
 #define	MIPS_EBASE_EXC_BASE		__BITS(29, MIPS_EBASE_EXC_BASE_SHIFT)
 #define	MIPS_EBASE_CPUNUM		__BITS(9, 0)
+#define	MIPS_EBASE_CPUNUM_WIDTH		10	/* used by asm code */
 
 /*
  * Hints for the prefetch instruction

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Mon Jul 20 01:10:38 UTC 2020

Modified Files:
src/sys/arch/mips/include: cpuregs.h

Log Message:
Add an extra bitfield in MIPS_COP_0_EBASE.


To generate a diff of this commit:
cvs rdiff -u -r1.100 -r1.101 src/sys/arch/mips/include/cpuregs.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/cpuregs.h
diff -u src/sys/arch/mips/include/cpuregs.h:1.100 src/sys/arch/mips/include/cpuregs.h:1.101
--- src/sys/arch/mips/include/cpuregs.h:1.100	Mon Jul 13 09:00:40 2020
+++ src/sys/arch/mips/include/cpuregs.h	Mon Jul 20 01:10:38 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpuregs.h,v 1.100 2020/07/13 09:00:40 simonb Exp $	*/
+/*	$NetBSD: cpuregs.h,v 1.101 2020/07/20 01:10:38 simonb Exp $	*/
 
 /*
  * Copyright (c) 2009 Miodrag Vallat.
@@ -833,6 +833,8 @@
 /*
  * Bits defined for EBASE (CP0 register 15, select 1).
  */
+#define	MIPS_EBASE_EXC_BASE_SHIFT	12
+#define	MIPS_EBASE_EXC_BASE		__BITS(29, MIPS_EBASE_EXC_BASE_SHIFT)
 #define	MIPS_EBASE_CPUNUM		__BITS(9, 0)
 
 /*

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Sun Jun 14 08:43:08 UTC 2020

Modified Files:
src/sys/arch/mips/include: cache_octeon.h

Log Message:
Define Octeon Cavium cache layouts for various cnMIPS cores.


To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/mips/include/cache_octeon.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/cache_octeon.h
diff -u src/sys/arch/mips/include/cache_octeon.h:1.3 src/sys/arch/mips/include/cache_octeon.h:1.4
--- src/sys/arch/mips/include/cache_octeon.h:1.3	Thu Apr 11 09:18:55 2019
+++ src/sys/arch/mips/include/cache_octeon.h	Sun Jun 14 08:43:07 2020
@@ -1,4 +1,7 @@
-/*	$NetBSD: cache_octeon.h,v 1.3 2019/04/11 09:18:55 simonb Exp $	*/
+/*	$NetBSD: cache_octeon.h,v 1.4 2020/06/14 08:43:07 simonb Exp $	*/
+
+#ifndef _MIPS_CACHE_OCTEON_H_
+#define _MIPS_CACHE_OCTEON_H_
 
 #define	CACHE_OCTEON_I			0
 #define	CACHE_OCTEON_D			1
@@ -8,6 +11,31 @@
 #define	CACHEOP_OCTEON_BITMAP_STORE		(3 << 2)	/* I */
 #define	CACHEOP_OCTEON_VIRTUAL_TAG_INV		(4 << 2)	/* D */
 
+#define	OCTEON_CACHELINE_SIZE			128
+
+/*
+ * Note that for the Dcache the 50XX manual says 1 set per way (Config1
+ * register - DS=0 ("... actual is 1"), p173) as does U-boot sources,
+ * however this only adds up to an 8kB Dcache.  The 50XX manual
+ * elsewhere references a 16kB Dcache as does the CN50XX product brief.
+ * The original NetBSD code, current OpenBSD and Linux code all use 2
+ * sets per way. lmbench's "cache" program also detects a 16kB Dcache.
+ * So we assume that all Octeon 1 and Octeon Plus cores have a 16kB
+ * Dcache.
+ */
+#define	OCTEON_I_DCACHE_WAYS			64
+#define	OCTEON_I_DCACHE_SETS			2
+
+#define	OCTEON_II_DCACHE_SETS			8
+#define	OCTEON_II_DCACHE_WAYS			32
+#define	OCTEON_II_ICACHE_SETS			8
+#define	OCTEON_II_ICACHE_WAYS			37
+
+#define	OCTEON_III_DCACHE_SETS			8
+#define	OCTEON_III_DCACHE_WAYS			32
+#define	OCTEON_III_ICACHE_SETS			16
+#define	OCTEON_III_ICACHE_WAYS			39
+
 #if !defined(_LOCORE)
 
 /*
@@ -54,3 +82,4 @@ void octeon_pdcache_inv_range_index(vadd
 void octeon_pdcache_wb_range(register_t va, vsize_t size);
 
 #endif /* !_LOCORE */
+#endif /* _MIPS_CACHE_OCTEON_H_ */

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Sat Jun 13 14:41:24 UTC 2020

Modified Files:
src/sys/arch/mips/include: mipsNN.h

Log Message:
Move MIPSNN_CFG3_ULRI so that it doesn't appear in some random position
among the other config3 register definitions.


To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/mips/include/mipsNN.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/mipsNN.h
diff -u src/sys/arch/mips/include/mipsNN.h:1.7 src/sys/arch/mips/include/mipsNN.h:1.8
--- src/sys/arch/mips/include/mipsNN.h:1.7	Sat Jun 13 14:39:07 2020
+++ src/sys/arch/mips/include/mipsNN.h	Sat Jun 13 14:41:24 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: mipsNN.h,v 1.7 2020/06/13 14:39:07 simonb Exp $	*/
+/*	$NetBSD: mipsNN.h,v 1.8 2020/06/13 14:41:24 simonb Exp $	*/
 
 /*
  * Copyright 2000, 2001
@@ -239,9 +239,6 @@
 /* "CMGCR" (R): Coherency Manager memory-mapped Global Configuration Register Space is implemented. */
 #define	MIPSNN_CFG3_CMGCR	0x2000
 
-/* "ULRI" (R): UserLocal register is implemented. */
-#define	MIPSNN_CFG3_ULRI	0x2000
-
 /* "IPLW" (R): Width of Status[IPL] and Cause[RIPL] fields. */
 #define	MIPSNN_CFG3_IPLW_MASK	0x0060
 #define	MIPSNN_CFG3_IPLW_SHIFT	21
@@ -271,6 +268,9 @@
 #define	MIPSNN_CFG3_ISA_MIPS64_OOR	2	/* both, MIPS64 out of reset */
 #define	MIPSNN_CFG3_ISA_microMIPS64_OOR	3	/* both, microMIPS64 OOR */
 
+/* "ULRI" (R): UserLocal register is implemented. */
+#define	MIPSNN_CFG3_ULRI	0x2000
+
 /* "DSP2P" (R): DSP v2 ASE extension present. */
 #define	MIPSNN_CFG3_DSP2P	0x0800
 

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Sat Jun 13 14:26:34 UTC 2020

Modified Files:
src/sys/arch/mips/include: locore.h

Log Message:
Note some hard-coded capabilties that can be probed.

XXX: Fix this and CPU table in mips/mips_machdep.c one day...


To generate a diff of this commit:
cvs rdiff -u -r1.105 -r1.106 src/sys/arch/mips/include/locore.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/locore.h
diff -u src/sys/arch/mips/include/locore.h:1.105 src/sys/arch/mips/include/locore.h:1.106
--- src/sys/arch/mips/include/locore.h:1.105	Sun May 24 07:15:24 2020
+++ src/sys/arch/mips/include/locore.h	Sat Jun 13 14:26:33 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.105 2020/05/24 07:15:24 simonb Exp $ */
+/* $NetBSD: locore.h,v 1.106 2020/06/13 14:26:33 simonb Exp $ */
 
 /*
  * This file should not be included by MI code!!!
@@ -857,17 +857,17 @@ struct pridtab {
 #define  MIPS_CP0FL_CACHE_ERR	__BIT(2)
 #define  MIPS_CP0FL_EIRR	__BIT(3)
 #define  MIPS_CP0FL_EIMR	__BIT(4)
-#define  MIPS_CP0FL_EBASE	__BIT(5)
-#define  MIPS_CP0FL_CONFIG	__BIT(6)
-#define  MIPS_CP0FL_CONFIG1	__BIT(7)
-#define  MIPS_CP0FL_CONFIG2	__BIT(8)
-#define  MIPS_CP0FL_CONFIG3	__BIT(9)
-#define  MIPS_CP0FL_CONFIG4	__BIT(10)
-#define  MIPS_CP0FL_CONFIG5	__BIT(11)
-#define  MIPS_CP0FL_CONFIG6	__BIT(12)
-#define  MIPS_CP0FL_CONFIG7	__BIT(13)
-#define  MIPS_CP0FL_USERLOCAL	__BIT(14)
-#define  MIPS_CP0FL_HWRENA	__BIT(15)
+#define  MIPS_CP0FL_EBASE	__BIT(5)  /* XXX probeable - shouldn't be hard coded */
+#define  MIPS_CP0FL_CONFIG	__BIT(6)  /* XXX defined - doesn't need to be hard coded */
+#define  MIPS_CP0FL_CONFIG1	__BIT(7)  /* XXX probeable - shouldn't be hard coded */
+#define  MIPS_CP0FL_CONFIG2	__BIT(8)  /* XXX probeable - shouldn't be hard coded */
+#define  MIPS_CP0FL_CONFIG3	__BIT(9)  /* XXX probeable - shouldn't be hard coded */
+#define  MIPS_CP0FL_CONFIG4	__BIT(10) /* XXX probeable - shouldn't be hard coded */
+#define  MIPS_CP0FL_CONFIG5	__BIT(11) /* XXX probeable - shouldn't be hard coded */
+#define  MIPS_CP0FL_CONFIG6	__BIT(12) /* XXX probeable - shouldn't be hard coded */
+#define  MIPS_CP0FL_CONFIG7	__BIT(13) /* XXX probeable - shouldn't be hard coded */
+#define  MIPS_CP0FL_USERLOCAL	__BIT(14) /* XXX probeable - shouldn't be hard coded */
+#define  MIPS_CP0FL_HWRENA	__BIT(15) /* XXX probeable - shouldn't be hard coded */
 
 /*
  * cpu_cidflags defines, by company

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Sat May 23 10:39:25 UTC 2020

Modified Files:
src/sys/arch/mips/include: cpuregs.h

Log Message:
Add CX73xx and CXF75xx Cavium Octeon PRIDs.


To generate a diff of this commit:
cvs rdiff -u -r1.97 -r1.98 src/sys/arch/mips/include/cpuregs.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/cpuregs.h
diff -u src/sys/arch/mips/include/cpuregs.h:1.97 src/sys/arch/mips/include/cpuregs.h:1.98
--- src/sys/arch/mips/include/cpuregs.h:1.97	Thu May  7 11:43:28 2020
+++ src/sys/arch/mips/include/cpuregs.h	Sat May 23 10:39:25 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpuregs.h,v 1.97 2020/05/07 11:43:28 simonb Exp $	*/
+/*	$NetBSD: cpuregs.h,v 1.98 2020/05/23 10:39:25 simonb Exp $	*/
 
 /*
  * Copyright (c) 2009 Miodrag Vallat.
@@ -1024,6 +1024,8 @@
 #define	MIPS_CNF71XX	0x94	/* Cavium Octeon CNF71XX	ISA 64  */
 #define	MIPS_CN78XX	0x95	/* Cavium Octeon CN78XX		ISA 64  */
 #define	MIPS_CN70XX	0x96	/* Cavium Octeon CN70XX		ISA 64  */
+#define	MIPS_CN73XX	0x97	/* Cavium Octeon CN73XX		ISA 64  */
+#define	MIPS_CNF75XX	0x98	/* Cavium Octeon CNF75XX	ISA 64  */
 
 /*
  * CPU processor revision IDs for company ID == 7 (Microsoft)

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Thu May  7 11:43:28 UTC 2020

Modified Files:
src/sys/arch/mips/include: cpuregs.h

Log Message:
Add PRID definition for newer SiByte SB1 cores (rev 0x11).
Add a constant for SiByte/BCRM cacheable coherent TLB cache attribute.


To generate a diff of this commit:
cvs rdiff -u -r1.96 -r1.97 src/sys/arch/mips/include/cpuregs.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/cpuregs.h
diff -u src/sys/arch/mips/include/cpuregs.h:1.96 src/sys/arch/mips/include/cpuregs.h:1.97
--- src/sys/arch/mips/include/cpuregs.h:1.96	Sun May  7 04:12:35 2017
+++ src/sys/arch/mips/include/cpuregs.h	Thu May  7 11:43:28 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpuregs.h,v 1.96 2017/05/07 04:12:35 skrll Exp $	*/
+/*	$NetBSD: cpuregs.h,v 1.97 2020/05/07 11:43:28 simonb Exp $	*/
 
 /*
  * Copyright (c) 2009 Miodrag Vallat.
@@ -148,6 +148,7 @@
 
 #define	CCA_UNCACHED		2
 #define	CCA_CACHEABLE		3	/* cacheable non-coherent */
+#define	CCA_SB_CACHEABLE_COHERENT 5	/* cacheable coherent (SiByte ext) */
 #define	CCA_ACCEL		7	/* non-cached, write combining */
 
 /* CPU dependent mtc0 hazard hook */
@@ -964,7 +965,8 @@
 /*
  * CPU processor revision IDs for company ID == 4 (SiByte)
  */
-#define	MIPS_SB1	0x01	/* SiByte SB1	 		ISA 64  */
+#define	MIPS_SB1	0x01	/* SiByte SB1			ISA 64  */
+#define	MIPS_SB1_11	0x11	/* SiByte SB1 (rev 0x11)	ISA 64  */
 
 /*
  * CPU processor revision IDs for company ID == 5 (SandCraft)

CVS commit: src/sys/arch/mips/include

[Christos Zoulas]

Module Name:src
Committed By:   christos
Date:   Sun May  5 18:13:16 UTC 2019

Modified Files:
src/sys/arch/mips/include: vmparam.h

Log Message:
PR/54133: Sevan Janiyan: Binaries fail to execute
Define M{IN,AX}_PAGE_SHIFT to cover all page possibilities


To generate a diff of this commit:
cvs rdiff -u -r1.61 -r1.62 src/sys/arch/mips/include/vmparam.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/vmparam.h
diff -u src/sys/arch/mips/include/vmparam.h:1.61 src/sys/arch/mips/include/vmparam.h:1.62
--- src/sys/arch/mips/include/vmparam.h:1.61	Thu May 31 18:26:36 2018
+++ src/sys/arch/mips/include/vmparam.h	Sun May  5 14:13:16 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: vmparam.h,v 1.61 2018/05/31 22:26:36 mrg Exp $	*/
+/*	$NetBSD: vmparam.h,v 1.62 2019/05/05 18:13:16 christos Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -50,10 +50,6 @@
 /*
  * Machine dependent VM constants for MIPS.
  */
-#if !defined(_RUMPKERNEL) && (defined(MODULAR) || defined(_MODULE))
-#define MAX_PAGE_SIZE	16384
-#define MIN_PAGE_SIZE	4096
-#endif
 
 /*
  * We normally use a 4K page but may use 16K on MIPS systems.
@@ -70,6 +66,12 @@
 #define	PAGE_SIZE	(1 << PAGE_SHIFT)
 #define	PAGE_MASK	(PAGE_SIZE - 1)
 
+#define MIN_PAGE_SHIFT	12
+#define	MAX_PAGE_SHIFT	14
+
+#define MAX_PAGE_SIZE	(1 << MAX_PAGE_SHIFT)
+#define MIN_PAGE_SIZE	(1 << MIN_PAGE_SHIFT)
+
 /*
  * USRSTACK is the top (end) of the user stack.
  *

CVS commit: src/sys/arch/mips/include

[Simon Burge]

Module Name:src
Committed By:   simonb
Date:   Thu Apr 11 09:18:55 UTC 2019

Modified Files:
src/sys/arch/mips/include: cache_octeon.h

Log Message:
Fix tyop.


To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/mips/include/cache_octeon.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/cache_octeon.h
diff -u src/sys/arch/mips/include/cache_octeon.h:1.2 src/sys/arch/mips/include/cache_octeon.h:1.3
--- src/sys/arch/mips/include/cache_octeon.h:1.2	Mon Jul 11 16:15:35 2016
+++ src/sys/arch/mips/include/cache_octeon.h	Thu Apr 11 09:18:55 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: cache_octeon.h,v 1.2 2016/07/11 16:15:35 matt Exp $	*/
+/*	$NetBSD: cache_octeon.h,v 1.3 2019/04/11 09:18:55 simonb Exp $	*/
 
 #define	CACHE_OCTEON_I			0
 #define	CACHE_OCTEON_D			1
@@ -13,7 +13,7 @@
 /*
  * cache_octeon_invalidate:
  *
- *	Invalidate all cahce blocks.
+ *	Invalidate all cache blocks.
  *	Argument "op" must be CACHE_OCTEON_I or CACHE_OCTEON_D.
  *	In Octeon specification, invalidate instruction works
  *	all cache blocks.

CVS commit: src/sys/arch/mips/include

[matthew green]

Module Name:src
Committed By:   mrg
Date:   Thu Feb  7 04:32:54 UTC 2019

Modified Files:
src/sys/arch/mips/include: bus_dma_defs.h

Log Message:
add missing BUS_DMA_PREFETCHABLE


To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/mips/include/bus_dma_defs.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/bus_dma_defs.h
diff -u src/sys/arch/mips/include/bus_dma_defs.h:1.3 src/sys/arch/mips/include/bus_dma_defs.h:1.4
--- src/sys/arch/mips/include/bus_dma_defs.h:1.3	Sat Jul 30 06:28:05 2016
+++ src/sys/arch/mips/include/bus_dma_defs.h	Thu Feb  7 04:32:54 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_dma_defs.h,v 1.3 2016/07/30 06:28:05 matt Exp $ */
+/* $NetBSD: bus_dma_defs.h,v 1.4 2019/02/07 04:32:54 mrg Exp $ */
 
 /*-
  * Copyright (c) 1997, 1998, 2000, 2001 The NetBSD Foundation, Inc.
@@ -82,6 +82,8 @@
 #define	BUS_DMA_READ		0x100	/* mapping is device -> memory only */
 #define	BUS_DMA_WRITE		0x200	/* mapping is memory -> device only */
 #define	BUS_DMA_NOCACHE		0x400	/* hint: map non-cached memory */
+#define	BUS_DMA_PREFETCHABLE	0x800	/* hint: map non-cached but allow 
+	 * things like write combining */
 
 /*
  * Private flags stored in the DMA map.

CVS commit: src/sys/arch/mips/include

[matthew green]

Module Name:src
Committed By:   mrg
Date:   Tue Sep  4 00:01:41 UTC 2018

Modified Files:
src/sys/arch/mips/include: asm.h

Log Message:
mark STATIC_NESTED_NOPROFILE() functions as functions.


To generate a diff of this commit:
cvs rdiff -u -r1.54 -r1.55 src/sys/arch/mips/include/asm.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/asm.h
diff -u src/sys/arch/mips/include/asm.h:1.54 src/sys/arch/mips/include/asm.h:1.55
--- src/sys/arch/mips/include/asm.h:1.54	Sat Feb 25 21:16:50 2017
+++ src/sys/arch/mips/include/asm.h	Tue Sep  4 00:01:41 2018
@@ -1,4 +1,4 @@
-/*	$NetBSD: asm.h,v 1.54 2017/02/25 21:16:50 joerg Exp $	*/
+/*	$NetBSD: asm.h,v 1.55 2018/09/04 00:01:41 mrg Exp $	*/
 
 /*
  * Copyright (c) 1992, 1993
@@ -169,8 +169,9 @@ _C_LABEL(x):
  *	No profilable local nested routine.
  */
 #define	STATIC_NESTED_NOPROFILE(x, fsize, retpc)	\
-	.ent	_C_LABEL(x);			\
-_C_LABEL(x): ;	\
+	.ent	_C_LABEL(x);\
+	.type	_C_LABEL(x), @function;			\
+_C_LABEL(x): ;		\
 	.frame	sp, fsize, retpc
 
 /*

CVS commit: src/sys/arch/mips/include

[Maya Rashish]

Module Name:src
Committed By:   maya
Date:   Wed Mar  7 23:08:29 UTC 2018

Modified Files:
src/sys/arch/mips/include: cpu.h

Log Message:
Adjust ci on the second iteration.

Now a MULTIPROCESSOR+LOCKDEBUG ERLITE reaches userland again


To generate a diff of this commit:
cvs rdiff -u -r1.123 -r1.124 src/sys/arch/mips/include/cpu.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/cpu.h
diff -u src/sys/arch/mips/include/cpu.h:1.123 src/sys/arch/mips/include/cpu.h:1.124
--- src/sys/arch/mips/include/cpu.h:1.123	Mon Jan 22 23:20:26 2018
+++ src/sys/arch/mips/include/cpu.h	Wed Mar  7 23:08:29 2018
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpu.h,v 1.123 2018/01/22 23:20:26 maya Exp $	*/
+/*	$NetBSD: cpu.h,v 1.124 2018/03/07 23:08:29 maya Exp $	*/
 
 /*-
  * Copyright (c) 1992, 1993
@@ -160,9 +160,11 @@ struct cpu_info {
 #ifdef MULTIPROCESSOR
 #define	CPU_INFO_ITERATOR		int
 #define	CPU_INFO_FOREACH(cii, ci)	\
-cii = 0, ci = (ncpu ? cpu_infos[0] : _info_store); \
-cii < (ncpu ? ncpu : 1); \
-++cii
+cii = 0, ci = _info_store; \
+ci != NULL; \
+cii++, \
+ncpu ? (ci = cpu_infos[cii]) \
+ : (ci = NULL)
 #else
 #define	CPU_INFO_ITERATOR		int __unused
 #define	CPU_INFO_FOREACH(cii, ci)	\

CVS commit: src/sys/arch/mips/include

[Maya Rashish]

Module Name:src
Committed By:   maya
Date:   Mon Jan 22 23:20:26 UTC 2018

Modified Files:
src/sys/arch/mips/include: cpu.h

Log Message:
Don't attempt to dereference cpu_infos if ncpus == 0.
Instead use the already initialized cpu_info_store.

(Also, now we assume all ncpus have cpu_infos initialized. seems to work.)

fixes PR port-mips/52940: ERLITE multiprocessor hangs early


To generate a diff of this commit:
cvs rdiff -u -r1.122 -r1.123 src/sys/arch/mips/include/cpu.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/cpu.h
diff -u src/sys/arch/mips/include/cpu.h:1.122 src/sys/arch/mips/include/cpu.h:1.123
--- src/sys/arch/mips/include/cpu.h:1.122	Sat Dec 16 00:37:52 2017
+++ src/sys/arch/mips/include/cpu.h	Mon Jan 22 23:20:26 2018
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpu.h,v 1.122 2017/12/16 00:37:52 mrg Exp $	*/
+/*	$NetBSD: cpu.h,v 1.123 2018/01/22 23:20:26 maya Exp $	*/
 
 /*-
  * Copyright (c) 1992, 1993
@@ -160,7 +160,9 @@ struct cpu_info {
 #ifdef MULTIPROCESSOR
 #define	CPU_INFO_ITERATOR		int
 #define	CPU_INFO_FOREACH(cii, ci)	\
-cii = 0, ci = cpu_infos[0]; cii < (ncpu ? ncpu : 1) && (ci = cpu_infos[cii]) != NULL; cii++
+cii = 0, ci = (ncpu ? cpu_infos[0] : _info_store); \
+cii < (ncpu ? ncpu : 1); \
+++cii
 #else
 #define	CPU_INFO_ITERATOR		int __unused
 #define	CPU_INFO_FOREACH(cii, ci)	\

CVS commit: src/sys/arch/mips/include

[Christos Zoulas]

Module Name:src
Committed By:   christos
Date:   Sat Dec  9 03:22:33 UTC 2017

Modified Files:
src/sys/arch/mips/include: reg.h types.h

Log Message:
provide 32 and 64 bit register struct definitions.


To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/mips/include/reg.h
cvs rdiff -u -r1.66 -r1.67 src/sys/arch/mips/include/types.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/reg.h
diff -u src/sys/arch/mips/include/reg.h:1.16 src/sys/arch/mips/include/reg.h:1.17
--- src/sys/arch/mips/include/reg.h:1.16	Sun Jan 24 11:13:19 2016
+++ src/sys/arch/mips/include/reg.h	Fri Dec  8 22:22:33 2017
@@ -1,4 +1,4 @@
-/*	$NetBSD: reg.h,v 1.16 2016/01/24 16:13:19 christos Exp $	*/
+/*	$NetBSD: reg.h,v 1.17 2017/12/09 03:22:33 christos Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -46,14 +46,38 @@ struct reg {
 	__register_t	r_regs[38];
 };
 
+struct reg32 {
+	__register32_t	r_regs[38];
+};
+
+struct reg64 {
+	__register64_t	r_regs[38];
+};
+
 struct fpreg {
 	__fpregister_t	r_regs[33];
 };
 
+struct fpreg32 {
+	__fpregister32_t	r_regs[33];
+};
+
+struct fpreg64 {
+	__fpregister64_t	r_regs[33];
+};
+
 struct dspreg {
 	__register_t	r_regs[8];
 };
 
+struct dspreg32 {
+	__register32_t	r_regs[8];
+};
+
+struct dspreg64 {
+	__register64_t	r_regs[8];
+};
+
 #if defined(__mips_n32) || defined(__mips_n64)
 struct fpreg_oabi {
 	int32_t		r_regs[33];

Index: src/sys/arch/mips/include/types.h
diff -u src/sys/arch/mips/include/types.h:1.66 src/sys/arch/mips/include/types.h:1.67
--- src/sys/arch/mips/include/types.h:1.66	Fri Jan 27 12:22:16 2017
+++ src/sys/arch/mips/include/types.h	Fri Dec  8 22:22:33 2017
@@ -1,4 +1,4 @@
-/*	$NetBSD: types.h,v 1.66 2017/01/27 17:22:16 christos Exp $	*/
+/*	$NetBSD: types.h,v 1.67 2017/12/09 03:22:33 christos Exp $	*/
 
 /*-
  * Copyright (c) 1992, 1993
@@ -41,16 +41,21 @@
 #include 
 #include 
 
-typedef	unsigned int	__cpu_simple_lock_nv_t;
+typedef __int32_t		__register32_t;
+typedef __int64_t		__register64_t;
+typedef __uint32_t		__fpregister32_t;
+typedef __uint64_t		__fpregister64_t;
+
+typedef	unsigned int		__cpu_simple_lock_nv_t;
 #if defined(__mips_o32)
-typedef __int32_t	__register_t;
+typedef __register32_t		__register_t;
 #else
-typedef __int64_t	__register_t;
+typedef __register64_t		__register_t;
 #endif
 #if defined(__mips_o64) || defined(__mips_o32)
-typedef	__uint32_t	__fpregister_t;
+typedef	__fpregister32_t	__fpregister_t;
 #else
-typedef	__uint64_t	__fpregister_t;
+typedef	__fpregister64_t	__fpregister_t;
 #endif
 
 /*

CVS commit: src/sys/arch/mips/include

[Christos Zoulas]

Module Name:src
Committed By:   christos
Date:   Mon Nov  6 19:17:43 UTC 2017

Modified Files:
src/sys/arch/mips/include: elf_machdep.h

Log Message:
Handle 64 bit kernels.


To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/mips/include/elf_machdep.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/elf_machdep.h
diff -u src/sys/arch/mips/include/elf_machdep.h:1.19 src/sys/arch/mips/include/elf_machdep.h:1.20
--- src/sys/arch/mips/include/elf_machdep.h:1.19	Sun Nov  5 22:47:47 2017
+++ src/sys/arch/mips/include/elf_machdep.h	Mon Nov  6 14:17:43 2017
@@ -1,4 +1,4 @@
-/*	$NetBSD: elf_machdep.h,v 1.19 2017/11/06 03:47:47 christos Exp $	*/
+/*	$NetBSD: elf_machdep.h,v 1.20 2017/11/06 19:17:43 christos Exp $	*/
 
 /*-
  * Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -28,10 +28,11 @@
 #ifndef _MIPS_ELF_MACHDEP_H_
 #define	_MIPS_ELF_MACHDEP_H_
 
-#define	KERN_ELFSIZE		32
 #ifdef _LP64
+#define	KERN_ELFSIZE		64
 #define	ARCH_ELFSIZE		64	/* MD native binary size */
 #else
+#define	KERN_ELFSIZE		32
 #define	ARCH_ELFSIZE		32	/* MD native binary size */
 #endif
 

CVS commit: src/sys/arch/mips/include

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Thu Sep  7 06:36:24 UTC 2017

Modified Files:
src/sys/arch/mips/include: vmparam.h

Log Message:
Don't define UVM_KM_VMFREELIST on mips as it excludes some memory
ranges unnecessarily.

PR/52501 - erlite quickly fails to allocate memory and processes wedge


To generate a diff of this commit:
cvs rdiff -u -r1.59 -r1.60 src/sys/arch/mips/include/vmparam.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/vmparam.h
diff -u src/sys/arch/mips/include/vmparam.h:1.59 src/sys/arch/mips/include/vmparam.h:1.60
--- src/sys/arch/mips/include/vmparam.h:1.59	Sat Jun 24 13:43:36 2017
+++ src/sys/arch/mips/include/vmparam.h	Thu Sep  7 06:36:24 2017
@@ -1,4 +1,4 @@
-/*	$NetBSD: vmparam.h,v 1.59 2017/06/24 13:43:36 joerg Exp $	*/
+/*	$NetBSD: vmparam.h,v 1.60 2017/09/07 06:36:24 skrll Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -208,8 +208,6 @@
 #endif
 
 #ifdef _KERNEL
-#define	UVM_KM_VMFREELIST	mips_poolpage_vmfreelist
-extern int mips_poolpage_vmfreelist;
 #ifdef ENABLE_MIPS_16KB_PAGE
 extern vaddr_t mips_vm_maxuser_address;
 #endif

CVS commit: src/sys/arch/mips/include

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Sat Jun 24 07:00:37 UTC 2017

Modified Files:
src/sys/arch/mips/include: pte.h

Log Message:
Provide pte_set


To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/mips/include/pte.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/pte.h
diff -u src/sys/arch/mips/include/pte.h:1.24 src/sys/arch/mips/include/pte.h:1.25
--- src/sys/arch/mips/include/pte.h:1.24	Sun Sep  4 07:27:49 2016
+++ src/sys/arch/mips/include/pte.h	Sat Jun 24 07:00:37 2017
@@ -1,4 +1,4 @@
-/*	$NetBSD: pte.h,v 1.24 2016/09/04 07:27:49 skrll Exp $	*/
+/*	$NetBSD: pte.h,v 1.25 2017/06/24 07:00:37 skrll Exp $	*/
 
 /*-
  * Copyright (c) 1997 The NetBSD Foundation, Inc.
@@ -361,6 +361,12 @@ pte_cached_change(pt_entry_t pte, bool c
 	return pte;
 }
 
+static inline void
+pte_set(pt_entry_t *ptep, pt_entry_t pte)
+{
+	*ptep = pte;
+}
+
 #ifdef __PMAP_PRIVATE
 struct vm_page_md;
 

CVS commit: src/sys/arch/mips/include

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Sun May  7 04:12:35 UTC 2017

Modified Files:
src/sys/arch/mips/include: cpuregs.h

Log Message:
Trailing whitespace


To generate a diff of this commit:
cvs rdiff -u -r1.95 -r1.96 src/sys/arch/mips/include/cpuregs.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/cpuregs.h
diff -u src/sys/arch/mips/include/cpuregs.h:1.95 src/sys/arch/mips/include/cpuregs.h:1.96
--- src/sys/arch/mips/include/cpuregs.h:1.95	Mon Jul 11 16:15:35 2016
+++ src/sys/arch/mips/include/cpuregs.h	Sun May  7 04:12:35 2017
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpuregs.h,v 1.95 2016/07/11 16:15:35 matt Exp $	*/
+/*	$NetBSD: cpuregs.h,v 1.96 2017/05/07 04:12:35 skrll Exp $	*/
 
 /*
  * Copyright (c) 2009 Miodrag Vallat.
@@ -125,7 +125,7 @@
 
 /* Map virtual address to index in mips3 r4k virtually-indexed cache */
 #define	MIPS3_VA_TO_CINDEX(x) \
-		(((intptr_t)(x) & 0xff) | MIPS_KSEG0_START) 
+		(((intptr_t)(x) & 0xff) | MIPS_KSEG0_START)
 
 #ifndef _LOCORE
 #define	MIPS_XSEG_MASK		(0x3fffLL)
@@ -826,7 +826,7 @@
 /*
  * Prefetched data is expected to be read (not modified)
  */
-#define	PREF_LOAD		0	
+#define	PREF_LOAD		0
 #define	PREF_LOAD_STREAMED	4	/* but not reused extensively; it */
 	/* "streams" through cache.  */
 #define	PREF_LOAD_RETAINED	6	/* and reused extensively; it should */
@@ -835,7 +835,7 @@
 /*
  * Prefetched data is expected to be stored or modified
  */
-#define	PREF_STORE		1	
+#define	PREF_STORE		1
 #define	PREF_STORE_STREAMED	5	/* but not reused extensively; it */
 	/* "streams" through cache.  */
 #define	PREF_STORE_RETAINED	7	/* and reused extensively; it should */
@@ -845,14 +845,14 @@
  * data is no longer expected to be used.  For a WB cache, schedule a
  * writeback of any dirty data and afterwards free the cache lines.
  */
-#define	PREF_WB_INV		25	
+#define	PREF_WB_INV		25
 #define	PREF_NUDGE		PREF_WB_INV
 
 /*
  * Prepare for writing an entire cache line without the overhead
  * involved in filling the line from memory.
  */
-#define	PREF_PREPAREFORSTORE	30	
+#define	PREF_PREPAREFORSTORE	30
 
 /*
  * CPU processor revision IDs for company ID == 0 (non mips32/64 chips)

CVS commit: src/sys/arch/mips/include

[Chuck Silvers]

Module Name:src
Committed By:   chs
Date:   Mon Feb 27 06:57:16 UTC 2017

Modified Files:
src/sys/arch/mips/include: fenv.h

Log Message:
fix fesetround() to set the FPSR to the desired value rather than
a pointer to a local variable.  wrap the asm in inline functions so that
the compiler can do type checking for us.


To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/mips/include/fenv.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/fenv.h
diff -u src/sys/arch/mips/include/fenv.h:1.2 src/sys/arch/mips/include/fenv.h:1.3
--- src/sys/arch/mips/include/fenv.h:1.2	Fri Jan 13 19:10:14 2017
+++ src/sys/arch/mips/include/fenv.h	Mon Feb 27 06:57:16 2017
@@ -1,4 +1,4 @@
-/*	$NetBSD: fenv.h,v 1.2 2017/01/13 19:10:14 christos Exp $	*/
+/*	$NetBSD: fenv.h,v 1.3 2017/02/27 06:57:16 chs Exp $	*/
 
 /*-
  * Copyright (c) 2004-2005 David Schultz 
@@ -67,9 +67,21 @@ extern const fenv_t	__fe_dfl_env;
 #define	_ENABLE_MASK	(FE_ALL_EXCEPT << _ENABLE_SHIFT)
 #define _ENABLE_SHIFT5
 
+static inline fpu_control_t
+__rfs(void)
+{
+	fpu_control_t __fpsr;
+
+	__asm __volatile("cfc1 %0,$31" : "=r" (__fpsr));
+	return __fpsr;
+}
 
-#define	__rfs(__fpsr)	__asm __volatile("cfc1 %0,$31" : "=r" ((*__fpsr)))
-#define	__wfs(__fpsr)	__asm __volatile("ctc1 %0,$31" : : "r" (__fpsr))
+static inline void
+__wfs(fpu_control_t __fpsr)
+{
+
+	__asm __volatile("ctc1 %0,$31" : : "r" (__fpsr));
+}
 
 __fenv_static inline int
 feclearexcept(int __excepts)
@@ -77,7 +89,7 @@ feclearexcept(int __excepts)
 	fexcept_t __fpsr;
 
 	__excepts &= FE_ALL_EXCEPT;
-	__rfs(&__fpsr);
+	__fpsr = __rfs();
 	__fpsr &= ~(__excepts | (__excepts << _ENABLE_SHIFT));
 	__wfs(__fpsr);
 	return 0;
@@ -88,7 +100,7 @@ fegetexceptflag(fexcept_t *__flagp, int 
 {
 	fexcept_t __fpsr;
 
-	__rfs(&__fpsr);
+	__fpsr = __rfs();
 	*__flagp = __fpsr & __excepts;
 	return (0);
 }
@@ -98,7 +110,7 @@ fesetexceptflag(const fexcept_t *__flagp
 {
 	fexcept_t __fpsr;
 
-	__rfs(&__fpsr);
+	__fpsr = __rfs();
 	__fpsr &= ~__excepts;
 	__fpsr |= *__flagp & __excepts;
 	__wfs(__fpsr);
@@ -119,7 +131,7 @@ fetestexcept(int __excepts)
 {
 	fexcept_t __fpsr;
 
-	__rfs(&__fpsr);
+	__fpsr = __rfs();
 	return (__fpsr & __excepts);
 }
 
@@ -128,7 +140,7 @@ fegetround(void)
 {
 	fexcept_t __fpsr;
 
-	__rfs(&__fpsr);
+	__fpsr = __rfs();
 	return __fpsr & _ROUND_MASK;
 }
 
@@ -139,10 +151,10 @@ fesetround(int __round)
 
 	if (__round & ~_ROUND_MASK)
 		return 1;
-	__rfs(&__fpsr);
+	__fpsr = __rfs();
 	__fpsr &= ~_ROUND_MASK;
 	__fpsr |= __round;
-	__wfs(&__fpsr);
+	__wfs(__fpsr);
 
 	return 0;
 }
@@ -151,7 +163,7 @@ __fenv_static inline int
 fegetenv(fenv_t *__envp)
 {
 
-	__rfs(__envp);
+	*__envp = __rfs();
 	return (0);
 }
 
@@ -160,7 +172,7 @@ feholdexcept(fenv_t *__envp)
 {
 	fenv_t __env;
 
-	__rfs(&__env);
+	__env = __rfs();
 	*__envp = __env;
 	__env &= ~(FE_ALL_EXCEPT | _ENABLE_MASK);
 	__wfs(__env);
@@ -180,7 +192,7 @@ feupdateenv(const fenv_t *__envp)
 {
 	fexcept_t __fpsr;
 
-	__rfs(&__fpsr);
+	__fpsr = __rfs();
 	__wfs(*__envp);
 	feraiseexcept(__fpsr & FE_ALL_EXCEPT);
 	return (0);
@@ -195,7 +207,7 @@ feenableexcept(int __excepts)
 {
 	fenv_t __old_fpsr, __new_fpsr;
 
-	__rfs(&__new_fpsr);
+	__new_fpsr = __rfs();
 	__old_fpsr = (__new_fpsr & _ENABLE_MASK) >> _ENABLE_SHIFT;
 	__excepts &= FE_ALL_EXCEPT;
 	__new_fpsr |= __excepts << _ENABLE_SHIFT;
@@ -208,7 +220,7 @@ fedisableexcept(int __excepts)
 {
 	fenv_t __old_fpsr, __new_fpsr;
 
-	__rfs(&__new_fpsr);
+	__new_fpsr = __rfs();
 	__old_fpsr = (__new_fpsr & _ENABLE_MASK) >> _ENABLE_SHIFT;
 	__excepts &= FE_ALL_EXCEPT;
 	__new_fpsr &= ~(__excepts << _ENABLE_SHIFT);
@@ -221,7 +233,7 @@ fegetexcept(void)
 {
 	fenv_t __fpsr;
 
-	__rfs(&__fpsr);
+	__fpsr = __rfs();
 	return ((__fpsr & _ENABLE_MASK) >> _ENABLE_SHIFT);
 }
 

CVS commit: src/sys/arch/mips/include

[Chuck Silvers]

Module Name:src
Committed By:   chs
Date:   Mon Feb 27 06:56:03 UTC 2017

Modified Files:
src/sys/arch/mips/include: ieeefp.h

Log Message:
the FP_* rounding constants need to be different from the new FE_* constants
to preserve the ABI, so shift them as needed when using them.


To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/mips/include/ieeefp.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/ieeefp.h
diff -u src/sys/arch/mips/include/ieeefp.h:1.8 src/sys/arch/mips/include/ieeefp.h:1.9
--- src/sys/arch/mips/include/ieeefp.h:1.8	Fri Dec 25 06:01:38 2015
+++ src/sys/arch/mips/include/ieeefp.h	Mon Feb 27 06:56:03 2017
@@ -1,4 +1,4 @@
-/*	$NetBSD: ieeefp.h,v 1.8 2015/12/25 06:01:38 christos Exp $	*/
+/*	$NetBSD: ieeefp.h,v 1.9 2017/02/27 06:56:03 chs Exp $	*/
 
 /*
  * Written by J.T. Conklin, Apr 11, 1995
@@ -17,11 +17,15 @@
 #if !defined(_ISOC99_SOURCE)
 
 typedef unsigned int fp_except;
-#define FP_X_IMP	FE_INEXACT	/* imprecise (loss of precision) */
-#define FP_X_UFL	FE_UNDERFLOW	/* underflow exception */
-#define FP_X_OFL	FE_OVERFLOW	/* overflow exception */
-#define FP_X_DZ		FE_DIVBYZERO	/* divide-by-zero exception */
-#define FP_X_INV	FE_INVALID	/* invalid operation exception */
+
+/* adjust for FP_* and FE_* value differences */ 
+#define	__FPE(x) ((x) >> 2)
+
+#define FP_X_IMP	__FPE(FE_INEXACT)	/* imprecise (loss of precision) */
+#define FP_X_UFL	__FPE(FE_UNDERFLOW)	/* underflow exception */
+#define FP_X_OFL	__FPE(FE_OVERFLOW)	/* overflow exception */
+#define FP_X_DZ		__FPE(FE_DIVBYZERO)	/* divide-by-zero exception */
+#define FP_X_INV	__FPE(FE_INVALID)	/* invalid operation exception */
 
 typedef enum {
 FP_RN=FE_TONEAREST,		/* round to nearest representable number */

CVS commit: src/sys/arch/mips/include

[Christos Zoulas]

Module Name:src
Committed By:   christos
Date:   Thu Feb 23 18:56:12 UTC 2017

Modified Files:
src/sys/arch/mips/include: ecoff_machdep.h

Log Message:
provide ecoff 32 defines.


To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/mips/include/ecoff_machdep.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/ecoff_machdep.h
diff -u src/sys/arch/mips/include/ecoff_machdep.h:1.22 src/sys/arch/mips/include/ecoff_machdep.h:1.23
--- src/sys/arch/mips/include/ecoff_machdep.h:1.22	Mon Jul 11 12:15:35 2016
+++ src/sys/arch/mips/include/ecoff_machdep.h	Thu Feb 23 13:56:12 2017
@@ -1,4 +1,4 @@
-/*	$NetBSD: ecoff_machdep.h,v 1.22 2016/07/11 16:15:35 matt Exp $	*/
+/*	$NetBSD: ecoff_machdep.h,v 1.23 2017/02/23 18:56:12 christos Exp $	*/
 
 /*
  * Copyright (c) 1997 Jonathan Stone
@@ -37,6 +37,12 @@
 #define ECOFF_LDPGSZ 4096
 
 #define ECOFF_PAD
+#define ECOFF32_PAD
+
+#define ECOFF32_MACHDEP \
+ecoff32_ulong gprmask; \
+ecoff32_ulong cprmask[4]; \
+ecoff32_ulong gp_value
 
 #define ECOFF_MACHDEP \
 u_long gprmask; \
@@ -67,6 +73,7 @@
 
 
 #define ECOFF_SEGMENT_ALIGNMENT(ep) ((ep)->a.vstamp < 23 ? 8 : 16)
+#define ECOFF32_SEGMENT_ALIGNMENT(ep) ((ep)->a.vstamp < 23 ? 8 : 16)
 
 #ifdef _KERNEL
 struct proc;
@@ -75,6 +82,34 @@ void	cpu_exec_ecoff_setregs(struct lwp *
 #endif	/* _KERNEL */
 
 
+struct ecoff32_symhdr {
+	int16_t		magic;
+	int16_t		vstamp;
+	int32_t		ilineMax;
+	int32_t		cbLine;
+	int32_t		cbLineOffset;
+	int32_t		idnMax;
+	int32_t		cbDnOffset;
+	int32_t		ipdMax;
+	int32_t		cbPdOffset;
+	int32_t		isymMax;
+	int32_t		cbSymOffset;
+	int32_t		ioptMax;
+	int32_t		cbOptOffset;
+	int32_t		iauxMax;
+	int32_t		cbAuxOffset;
+	int32_t		issMax;
+	int32_t		cbSsOffset;
+	int32_t		issExtMax;
+	int32_t		cbSsExtOffset;
+	int32_t		ifdMax;
+	int32_t		cbFdOffset;
+	int32_t		crfd;
+	int32_t		cbRfdOffset;
+	int32_t		iextMax;
+	int32_t		cbExtOffset;
+};
+
 /*
  * ECOFF symbol definitions for 32-bit mips.
  * XXX 64-bit (mips3?) may be different.
@@ -121,3 +156,14 @@ struct ecoff_extsym {
 	unsigned	:1;
 	unsigned	es_symauxindex:20;
 };
+
+struct ecoff32_extsym {
+	uint16_t	es_flags;
+	uint16_t	es_ifd;
+	int32_t		es_strindex;
+	int32_t		es_value;
+	unsigned	es_type:6;
+	unsigned	es_class:5;
+	unsigned	:1;
+	unsigned	es_symauxindex:20;
+};

CVS commit: src/sys/arch/mips/include

[Christos Zoulas]

Module Name:src
Committed By:   christos
Date:   Fri Jan 27 17:22:16 UTC 2017

Modified Files:
src/sys/arch/mips/include: types.h

Log Message:
remove __HAVE_COMPAT_NETBSD32


To generate a diff of this commit:
cvs rdiff -u -r1.65 -r1.66 src/sys/arch/mips/include/types.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/types.h
diff -u src/sys/arch/mips/include/types.h:1.65 src/sys/arch/mips/include/types.h:1.66
--- src/sys/arch/mips/include/types.h:1.65	Thu Jan 26 10:55:10 2017
+++ src/sys/arch/mips/include/types.h	Fri Jan 27 12:22:16 2017
@@ -1,4 +1,4 @@
-/*	$NetBSD: types.h,v 1.65 2017/01/26 15:55:10 christos Exp $	*/
+/*	$NetBSD: types.h,v 1.66 2017/01/27 17:22:16 christos Exp $	*/
 
 /*-
  * Copyright (c) 1992, 1993
@@ -168,6 +168,5 @@ typedef __uint32_t tlb_asid_t;
 #define	__HAVE_MM_MD_DIRECT_MAPPED_PHYS
 #define	__HAVE_MM_MD_KERNACC
 #define	__HAVE_MM_MD_CACHE_ALIASING
-#define	__HAVE_COMPAT_NETBSD32
 
 #endif	/* _MIPS_TYPES_H_ */

CVS commit: src/sys/arch/mips/include

[Christos Zoulas]

Module Name:src
Committed By:   christos
Date:   Fri Jan 13 19:10:14 UTC 2017

Modified Files:
src/sys/arch/mips/include: fenv.h

Log Message:
making this use mips assembly is a good start!


To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/mips/include/fenv.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/fenv.h
diff -u src/sys/arch/mips/include/fenv.h:1.1 src/sys/arch/mips/include/fenv.h:1.2
--- src/sys/arch/mips/include/fenv.h:1.1	Mon Dec 21 12:02:33 2015
+++ src/sys/arch/mips/include/fenv.h	Fri Jan 13 14:10:14 2017
@@ -1,4 +1,4 @@
-/*	$NetBSD: fenv.h,v 1.1 2015/12/21 17:02:33 christos Exp $	*/
+/*	$NetBSD: fenv.h,v 1.2 2017/01/13 19:10:14 christos Exp $	*/
 
 /*-
  * Copyright (c) 2004-2005 David Schultz 
@@ -37,15 +37,16 @@
 #define	__fenv_static	static
 #endif
 
-typedef	uint32_t	fenv_t;
-typedef	uint32_t	fexcept_t;
+typedef	uint32_t 	fpu_control_t __attribute__((__mode__(__SI__)));
+typedef	fpu_control_t	fenv_t;
+typedef	fpu_control_t	fexcept_t;
 
 /* Exception flags */
-#define	FE_INVALID	0x0001
-#define	FE_DIVBYZERO	0x0002
-#define	FE_OVERFLOW	0x0004
+#define	FE_INEXACT	0x0004
 #define	FE_UNDERFLOW	0x0008
-#define	FE_INEXACT	0x0010
+#define	FE_OVERFLOW	0x0010
+#define	FE_DIVBYZERO	0x0020
+#define	FE_INVALID	0x0040
 #define	FE_ALL_EXCEPT	(FE_DIVBYZERO | FE_INEXACT | \
 			 FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW)
 
@@ -63,26 +64,23 @@ extern const fenv_t	__fe_dfl_env;
 #define	FE_DFL_ENV	(&__fe_dfl_env)
 
 /* We need to be able to map status flag positions to mask flag positions */
-#define _FPUSW_SHIFT	16
-#define	_ENABLE_MASK	(FE_ALL_EXCEPT << _FPUSW_SHIFT)
+#define	_ENABLE_MASK	(FE_ALL_EXCEPT << _ENABLE_SHIFT)
+#define _ENABLE_SHIFT5
 
-#ifdef	ARM_HARD_FLOAT
-#define	__rfs(__fpsr)	__asm __volatile("rfs %0" : "=r" (*(__fpsr)))
-#define	__wfs(__fpsr)	__asm __volatile("wfs %0" : : "r" (__fpsr))
-#else
-#define __rfs(__fpsr)
-#define __wfs(__fpsr)
-#endif
+
+#define	__rfs(__fpsr)	__asm __volatile("cfc1 %0,$31" : "=r" ((*__fpsr)))
+#define	__wfs(__fpsr)	__asm __volatile("ctc1 %0,$31" : : "r" (__fpsr))
 
 __fenv_static inline int
 feclearexcept(int __excepts)
 {
 	fexcept_t __fpsr;
 
+	__excepts &= FE_ALL_EXCEPT;
 	__rfs(&__fpsr);
-	__fpsr &= ~__excepts;
+	__fpsr &= ~(__excepts | (__excepts << _ENABLE_SHIFT));
 	__wfs(__fpsr);
-	return (0);
+	return 0;
 }
 
 __fenv_static inline int
@@ -128,20 +126,25 @@ fetestexcept(int __excepts)
 __fenv_static inline int
 fegetround(void)
 {
+	fexcept_t __fpsr;
 
-	/*
-	 * Apparently, the rounding mode is specified as part of the
-	 * instruction format on ARM, so the dynamic rounding mode is
-	 * indeterminate.  Some FPUs may differ.
-	 */
-	return (-1);
+	__rfs(&__fpsr);
+	return __fpsr & _ROUND_MASK;
 }
 
 __fenv_static inline int
 fesetround(int __round)
 {
+	fexcept_t __fpsr;
+
+	if (__round & ~_ROUND_MASK)
+		return 1;
+	__rfs(&__fpsr);
+	__fpsr &= ~_ROUND_MASK;
+	__fpsr |= __round;
+	__wfs(&__fpsr);
 
-	return (-1);
+	return 0;
 }
 
 __fenv_static inline int
@@ -188,25 +191,29 @@ feupdateenv(const fenv_t *__envp)
 /* We currently provide no external definitions of the functions below. */
 
 static inline int
-feenableexcept(int __mask)
+feenableexcept(int __excepts)
 {
 	fenv_t __old_fpsr, __new_fpsr;
 
-	__rfs(&__old_fpsr);
-	__new_fpsr = __old_fpsr | (__mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT;
+	__rfs(&__new_fpsr);
+	__old_fpsr = (__new_fpsr & _ENABLE_MASK) >> _ENABLE_SHIFT;
+	__excepts &= FE_ALL_EXCEPT;
+	__new_fpsr |= __excepts << _ENABLE_SHIFT;
 	__wfs(__new_fpsr);
-	return ((__old_fpsr >> _FPUSW_SHIFT) & FE_ALL_EXCEPT);
+	return __old_fpsr;
 }
 
 static inline int
-fedisableexcept(int __mask)
+fedisableexcept(int __excepts)
 {
 	fenv_t __old_fpsr, __new_fpsr;
 
-	__rfs(&__old_fpsr);
-	__new_fpsr = __old_fpsr & ~((__mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT);
+	__rfs(&__new_fpsr);
+	__old_fpsr = (__new_fpsr & _ENABLE_MASK) >> _ENABLE_SHIFT;
+	__excepts &= FE_ALL_EXCEPT;
+	__new_fpsr &= ~(__excepts << _ENABLE_SHIFT);
 	__wfs(__new_fpsr);
-	return ((__old_fpsr >> _FPUSW_SHIFT) & FE_ALL_EXCEPT);
+	return __old_fpsr;
 }
 
 static inline int
@@ -215,7 +222,7 @@ fegetexcept(void)
 	fenv_t __fpsr;
 
 	__rfs(&__fpsr);
-	return ((__fpsr & _ENABLE_MASK) >> _FPUSW_SHIFT);
+	return ((__fpsr & _ENABLE_MASK) >> _ENABLE_SHIFT);
 }
 
 #endif /* _NETBSD_SOURCE || _GNU_SOURCE */

CVS commit: src/sys/arch/mips/include

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Tue Nov 22 11:01:51 UTC 2016

Modified Files:
src/sys/arch/mips/include: vmparam.h

Log Message:
1TB is enough UVA for anyone... plus not all cpus can support more.


To generate a diff of this commit:
cvs rdiff -u -r1.56 -r1.57 src/sys/arch/mips/include/vmparam.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/vmparam.h
diff -u src/sys/arch/mips/include/vmparam.h:1.56 src/sys/arch/mips/include/vmparam.h:1.57
--- src/sys/arch/mips/include/vmparam.h:1.56	Fri Nov  4 08:24:36 2016
+++ src/sys/arch/mips/include/vmparam.h	Tue Nov 22 11:01:50 2016
@@ -1,4 +1,4 @@
-/*	$NetBSD: vmparam.h,v 1.56 2016/11/04 08:24:36 skrll Exp $	*/
+/*	$NetBSD: vmparam.h,v 1.57 2016/11/22 11:01:50 skrll Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -158,7 +158,7 @@
  */
 #define VM_MIN_ADDRESS		((vaddr_t)0x)
 #ifdef _LP64
-#define MIPS_VM_MAXUSER_ADDRESS	((vaddr_t) 1L << (4*PGSHIFT-8))
+#define MIPS_VM_MAXUSER_ADDRESS	((vaddr_t) 1L << 40)
 #ifdef ENABLE_MIPS_16KB_PAGE
 #define VM_MAXUSER_ADDRESS	mips_vm_maxuser_address
 #else

CVS commit: src/sys/arch/mips/include

[Maya Rashish]

Module Name:src
Committed By:   maya
Date:   Fri Nov 11 16:41:32 UTC 2016

Modified Files:
src/sys/arch/mips/include: asm.h

Log Message:
switch mfc0_hazard to be superscalar nop, some mips3 are superscalar
and need this to do the right thing


To generate a diff of this commit:
cvs rdiff -u -r1.52 -r1.53 src/sys/arch/mips/include/asm.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/asm.h
diff -u src/sys/arch/mips/include/asm.h:1.52 src/sys/arch/mips/include/asm.h:1.53
--- src/sys/arch/mips/include/asm.h:1.52	Wed Nov  9 11:50:09 2016
+++ src/sys/arch/mips/include/asm.h	Fri Nov 11 16:41:32 2016
@@ -1,4 +1,4 @@
-/*	$NetBSD: asm.h,v 1.52 2016/11/09 11:50:09 maya Exp $	*/
+/*	$NetBSD: asm.h,v 1.53 2016/11/11 16:41:32 maya Exp $	*/
 
 /*
  * Copyright (c) 1992, 1993
@@ -512,7 +512,7 @@ _C_LABEL(x):
 
 /* CPU dependent hook for cp0 load delays */
 #if defined(MIPS1) || defined(MIPS2) || defined(MIPS3)
-#define MFC0_HAZARD	nop
+#define MFC0_HAZARD	sll $0,$0,1	/* super scalar nop */
 #else
 #define MFC0_HAZARD	/* nothing */
 #endif

CVS commit: src/sys/arch/mips/include

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Fri Nov  4 08:24:36 UTC 2016

Modified Files:
src/sys/arch/mips/include: vmparam.h

Log Message:
Cmoment formatting.  No functional change.


To generate a diff of this commit:
cvs rdiff -u -r1.55 -r1.56 src/sys/arch/mips/include/vmparam.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/vmparam.h
diff -u src/sys/arch/mips/include/vmparam.h:1.55 src/sys/arch/mips/include/vmparam.h:1.56
--- src/sys/arch/mips/include/vmparam.h:1.55	Mon Jul 11 16:15:35 2016
+++ src/sys/arch/mips/include/vmparam.h	Fri Nov  4 08:24:36 2016
@@ -1,4 +1,4 @@
-/*	$NetBSD: vmparam.h,v 1.55 2016/07/11 16:15:35 matt Exp $	*/
+/*	$NetBSD: vmparam.h,v 1.56 2016/11/04 08:24:36 skrll Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -164,8 +164,7 @@
 #else
 #define VM_MAXUSER_ADDRESS	MIPS_VM_MAXUSER_ADDRESS
 #endif
-			/* 0x0100 */
-#define VM_MAX_ADDRESS		VM_MAXUSER_ADDRESS
+#define VM_MAX_ADDRESS		VM_MAXUSER_ADDRESS	/* 0x0100 */
 #define VM_MIN_KERNEL_ADDRESS	((vaddr_t) 3L << 62)	/* 0xC000 */
 #define VM_MAX_KERNEL_ADDRESS	((vaddr_t) -1L << 31)	/* 0x8000 */
 #else
@@ -178,7 +177,7 @@
 #define VM_MAX_KERNEL_ADDRESS	((vaddr_t)-0x4000)	/* 0xC000 */
 #endif
 #endif
-#define VM_MAXUSER32_ADDRESS	((vaddr_t)(1UL << 31))/* 0x8000 */
+#define VM_MAXUSER32_ADDRESS	((vaddr_t)(1UL << 31))	/* 0x8000 */
 
 /*
  * The address to which unspecified mapping requests default

CVS commit: src/sys/arch/mips/include

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Thu Oct 13 18:52:30 UTC 2016

Modified Files:
src/sys/arch/mips/include: locore.h

Log Message:
sprinkle #ifndef __ASSEMBLER__ to make this file usable from .S - mostly for
macros like MIPS3_PLUS


To generate a diff of this commit:
cvs rdiff -u -r1.100 -r1.101 src/sys/arch/mips/include/locore.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/locore.h
diff -u src/sys/arch/mips/include/locore.h:1.100 src/sys/arch/mips/include/locore.h:1.101
--- src/sys/arch/mips/include/locore.h:1.100	Mon Jul 11 16:15:35 2016
+++ src/sys/arch/mips/include/locore.h	Thu Oct 13 18:52:30 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.100 2016/07/11 16:15:35 matt Exp $ */
+/* $NetBSD: locore.h,v 1.101 2016/10/13 18:52:30 macallan Exp $ */
 
 /*
  * This file should not be included by MI code!!!
@@ -32,6 +32,8 @@
 #include "opt_cputype.h"
 #endif
 
+#ifndef __ASSEMBLER__
+
 #include 
 
 #include 
@@ -45,6 +47,7 @@ typedef uint32_t pt_entry_t;
 #endif
 
 #include 
+#endif /* !__ASSEMBLER__ */
 
 #ifdef _KERNEL
 
@@ -90,6 +93,9 @@ typedef uint32_t pt_entry_t;
 #error MIPS1 does not support non-4KB page sizes.
 #endif
 
+/* XXX some .S files look for MIPS3_PLUS */
+#ifndef __ASSEMBLER__
+
 /* XXX simonb
  * Should the following be in a cpu_info type structure?
  * And how many of these are per-cpu vs. per-system?  (Ie,
@@ -122,6 +128,8 @@ struct mips_options {
 #endif
 };
 
+#endif /* !__ASSEMBLER__ */
+
 /*
  * Macros to find the CPU architecture we're on at run-time,
  * or if possible, at compile-time.
@@ -309,6 +317,8 @@ struct mips_options {
 
 #endif /* run-time test */
 
+#ifndef __ASSEMBLER__
+
 struct tlbmask;
 struct trapframe;
 
@@ -966,7 +976,7 @@ struct pridtab {
 # define MIPS_CIDFL_RMI_L2SZ(cidfl)	\
 		((256*1024) << (((cidfl) & MIPS_CIDFL_RMI_L2SZ_MASK)	\
 			>> MIPS_CIDFL_RMI_L2SZ_SHIFT))
-
+#endif /* !__ASSEMBLER__ */
 #endif	/* _KERNEL */
 
 #endif	/* _MIPS_LOCORE_H */

CVS commit: src/sys/arch/mips/include

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Sun Sep  4 07:27:49 UTC 2016

Modified Files:
src/sys/arch/mips/include: pte.h

Log Message:
Fix pte_cached_p for MIPS_HAS_R4K_MMU


To generate a diff of this commit:
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/mips/include/pte.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/pte.h
diff -u src/sys/arch/mips/include/pte.h:1.23 src/sys/arch/mips/include/pte.h:1.24
--- src/sys/arch/mips/include/pte.h:1.23	Mon Jul 11 16:15:35 2016
+++ src/sys/arch/mips/include/pte.h	Sun Sep  4 07:27:49 2016
@@ -1,4 +1,4 @@
-/*	$NetBSD: pte.h,v 1.23 2016/07/11 16:15:35 matt Exp $	*/
+/*	$NetBSD: pte.h,v 1.24 2016/09/04 07:27:49 skrll Exp $	*/
 
 /*-
  * Copyright (c) 1997 The NetBSD Foundation, Inc.
@@ -315,7 +315,7 @@ static inline bool
 pte_cached_p(pt_entry_t pte)
 {
 	if (MIPS_HAS_R4K_MMU) {
-		return MIPS3_PG_TO_CCA(pte) == mips_options.mips3_pg_cached;
+		return MIPS3_PG_TO_CCA(pte) == MIPS3_PG_TO_CCA(mips_options.mips3_pg_cached);
 	} else {
 		return (pte & MIPS1_PG_N) == 0;
 	}

CVS commit: src/sys/arch/mips/include

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Thu Aug 18 22:23:20 UTC 2016

Modified Files:
src/sys/arch/mips/include: cache.h

Log Message:
Need to compile in cache alias support when MIPS3 or MIPS4


To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/mips/include/cache.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/cache.h
diff -u src/sys/arch/mips/include/cache.h:1.13 src/sys/arch/mips/include/cache.h:1.14
--- src/sys/arch/mips/include/cache.h:1.13	Mon Jul 11 16:15:35 2016
+++ src/sys/arch/mips/include/cache.h	Thu Aug 18 22:23:20 2016
@@ -1,4 +1,4 @@
-/*	$NetBSD: cache.h,v 1.13 2016/07/11 16:15:35 matt Exp $	*/
+/*	$NetBSD: cache.h,v 1.14 2016/08/18 22:23:20 skrll Exp $	*/
 
 /*
  * Copyright 2001 Wasabi Systems, Inc.
@@ -225,7 +225,9 @@ struct mips_cache_info {
 	bool mci_icache_virtual_alias;
 };
 
-#if (MIPS1 + MIPS64_RMIXL + MIPS64R2_RMIXL + MIPS64_OCTEON) > 0 \
+
+#if (MIPS1 + MIPS64_RMIXL + MIPS64R2_RMIXL + MIPS64_OCTEON) > 0 && \
+(MIPS3 + MIPS4) == 0 \
  && !defined(MODULE)
 #define	MIPS_CACHE_ALIAS_MASK		0
 #define	MIPS_CACHE_VIRTUAL_ALIAS	false
@@ -233,7 +235,9 @@ struct mips_cache_info {
 #define	MIPS_CACHE_ALIAS_MASK		mips_cache_info.mci_cache_alias_mask
 #define	MIPS_CACHE_VIRTUAL_ALIAS	mips_cache_info.mci_cache_virtual_alias
 #endif
-#if (MIPS1 + MIPS64_RMIXL + MIPS64_OCTEON) > 0 && !defined(_MODULE)
+#if (MIPS1 + MIPS64_RMIXL + MIPS64_OCTEON) > 0 && \
+(MIPS3 + MIPS4) == 0 \
+&& !defined(_MODULE)
 #define	MIPS_ICACHE_ALIAS_MASK		0
 #define	MIPS_ICACHE_VIRTUAL_ALIAS	false
 #else

CVS commit: src/sys/arch/mips/include

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Sat Aug 13 07:52:52 UTC 2016

Modified Files:
src/sys/arch/mips/include: asm.h

Log Message:
Trailing whitespace


To generate a diff of this commit:
cvs rdiff -u -r1.49 -r1.50 src/sys/arch/mips/include/asm.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/asm.h
diff -u src/sys/arch/mips/include/asm.h:1.49 src/sys/arch/mips/include/asm.h:1.50
--- src/sys/arch/mips/include/asm.h:1.49	Mon Jul 11 16:15:35 2016
+++ src/sys/arch/mips/include/asm.h	Sat Aug 13 07:52:52 2016
@@ -1,4 +1,4 @@
-/*	$NetBSD: asm.h,v 1.49 2016/07/11 16:15:35 matt Exp $	*/
+/*	$NetBSD: asm.h,v 1.50 2016/08/13 07:52:52 skrll Exp $	*/
 
 /*
  * Copyright (c) 1992, 1993
@@ -76,7 +76,7 @@
 	lw	t9,4(sp);	\
 	addiu	sp,sp,8;	\
 	addiu	t9,t9,40;	\
-	.set	pop;	
+	.set	pop;
 
 #ifdef GPROF
 #define	MCOUNT _KERN_MCOUNT

CVS commit: src/sys/arch/mips/include

[Matt Thomas]

Module Name:src
Committed By:   matt
Date:   Sat Jul 30 06:27:45 UTC 2016

Modified Files:
src/sys/arch/mips/include: psl.h

Log Message:
KX needs to set on !O32 kernels


To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/mips/include/psl.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/psl.h
diff -u src/sys/arch/mips/include/psl.h:1.18 src/sys/arch/mips/include/psl.h:1.19
--- src/sys/arch/mips/include/psl.h:1.18	Mon Dec 14 00:46:05 2009
+++ src/sys/arch/mips/include/psl.h	Sat Jul 30 06:27:45 2016
@@ -1,4 +1,4 @@
-/*	$NetBSD: psl.h,v 1.18 2009/12/14 00:46:05 matt Exp $	*/
+/*	$NetBSD: psl.h,v 1.19 2016/07/30 06:27:45 matt Exp $	*/
 
 /*
  * Copyright (c) 1992, 1993
@@ -48,11 +48,7 @@
 #define	MIPS3_PSL_LOWIPL	(MIPS3_INT_MASK | MIPS_SR_INT_IE)
 
 #if !defined(__mips_o32)
-# ifdef _LP64
-#  define MIPS3_PSL_XFLAGS	(MIPS3_SR_XX | MIPS_SR_KX)
-# else
-#  define MIPS3_PSL_XFLAGS	(MIPS3_SR_XX)
-# endif
+# define MIPS3_PSL_XFLAGS	(MIPS3_SR_XX | MIPS_SR_KX)
 #else
 # define MIPS3_PSL_XFLAGS	(0)
 #endif

CVS commit: src/sys/arch/mips/include

[Matt Thomas]

Module Name:src
Committed By:   matt
Date:   Sat Jul 30 06:28:05 UTC 2016

Modified Files:
src/sys/arch/mips/include: bus_dma_defs.h

Log Message:
Use register_t for _ds_vaddr


To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/mips/include/bus_dma_defs.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/bus_dma_defs.h
diff -u src/sys/arch/mips/include/bus_dma_defs.h:1.2 src/sys/arch/mips/include/bus_dma_defs.h:1.3
--- src/sys/arch/mips/include/bus_dma_defs.h:1.2	Thu Jun 11 08:22:09 2015
+++ src/sys/arch/mips/include/bus_dma_defs.h	Sat Jul 30 06:28:05 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_dma_defs.h,v 1.2 2015/06/11 08:22:09 matt Exp $ */
+/* $NetBSD: bus_dma_defs.h,v 1.3 2016/07/30 06:28:05 matt Exp $ */
 
 /*-
  * Copyright (c) 1997, 1998, 2000, 2001 The NetBSD Foundation, Inc.
@@ -112,7 +112,7 @@ typedef struct mips_bus_dmamap	*bus_dmam
 struct mips_bus_dma_segment {
 	bus_addr_t	ds_addr;	/* DMA address */
 	bus_size_t	ds_len;		/* length of transfer */
-	bus_addr_t	_ds_vaddr;	/* virtual address, 0 if invalid */
+	register_t	_ds_vaddr;	/* virtual address, 0 if invalid */
 };
 typedef struct mips_bus_dma_segment	bus_dma_segment_t;
 

CVS commit: src/sys/arch/mips/include

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Sat Jul 16 01:59:05 UTC 2016

Modified Files:
src/sys/arch/mips/include: cpu.h

Log Message:
move sysctl-related #defines out of #ifdef _KERNEL so userland can see them
now pixman builds again on loongson


To generate a diff of this commit:
cvs rdiff -u -r1.119 -r1.120 src/sys/arch/mips/include/cpu.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/cpu.h
diff -u src/sys/arch/mips/include/cpu.h:1.119 src/sys/arch/mips/include/cpu.h:1.120
--- src/sys/arch/mips/include/cpu.h:1.119	Mon Jul 11 19:05:57 2016
+++ src/sys/arch/mips/include/cpu.h	Sat Jul 16 01:59:05 2016
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpu.h,v 1.119 2016/07/11 19:05:57 skrll Exp $	*/
+/*	$NetBSD: cpu.h,v 1.120 2016/07/16 01:59:05 macallan Exp $	*/
 
 /*-
  * Copyright (c) 1992, 1993
@@ -164,23 +164,6 @@ struct cpu_info {
 ci = _info_store; ci != NULL; ci = NULL
 #endif
 
-/*
- * CTL_MACHDEP definitions.
- */
-#define CPU_CONSDEV		1	/* dev_t: console terminal device */
-#define CPU_BOOTED_KERNEL	2	/* string: booted kernel name */
-#define CPU_ROOT_DEVICE		3	/* string: root device name */
-#define CPU_LLSC		4	/* OS/CPU supports LL/SC instruction */
-#define CPU_LMMI		5	/* Loongson multimedia instructions */
-
-/*
- * Platform can override, but note this breaks userland compatibility
- * with other mips platforms.
- */
-#ifndef CPU_MAXID
-#define CPU_MAXID		5	/* number of valid machdep ids */
-#endif
-
 /* Note: must be kept in sync with -ffixed-?? Makefile.mips. */
 //	MIPS_CURLWP moved to 
 #define MIPS_CURLWP_QUOTED	"$24"
@@ -290,4 +273,22 @@ void	cpu_vmspace_exec(struct lwp *, vadd
 #endif
 
 #endif /* _KERNEL */
+
+/*
+ * CTL_MACHDEP definitions.
+ */
+#define CPU_CONSDEV		1	/* dev_t: console terminal device */
+#define CPU_BOOTED_KERNEL	2	/* string: booted kernel name */
+#define CPU_ROOT_DEVICE		3	/* string: root device name */
+#define CPU_LLSC		4	/* OS/CPU supports LL/SC instruction */
+#define CPU_LMMI		5	/* Loongson multimedia instructions */
+
+/*
+ * Platform can override, but note this breaks userland compatibility
+ * with other mips platforms.
+ */
+#ifndef CPU_MAXID
+#define CPU_MAXID		5	/* number of valid machdep ids */
+#endif
+
 #endif /* _CPU_H_ */

CVS commit: src/sys/arch/mips/include

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Tue Jul 12 15:56:23 UTC 2016

Modified Files:
src/sys/arch/mips/include: cache_r4k.h

Log Message:
Appease gcc and asm


To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/mips/include/cache_r4k.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/cache_r4k.h
diff -u src/sys/arch/mips/include/cache_r4k.h:1.15 src/sys/arch/mips/include/cache_r4k.h:1.16
--- src/sys/arch/mips/include/cache_r4k.h:1.15	Tue Jul 12 14:24:13 2016
+++ src/sys/arch/mips/include/cache_r4k.h	Tue Jul 12 15:56:23 2016
@@ -1,4 +1,4 @@
-/*	$NetBSD: cache_r4k.h,v 1.15 2016/07/12 14:24:13 skrll Exp $	*/
+/*	$NetBSD: cache_r4k.h,v 1.16 2016/07/12 15:56:23 skrll Exp $	*/
 
 /*
  * Copyright 2001 Wasabi Systems, Inc.
@@ -63,18 +63,16 @@
  *
  *	Perform the specified cache operation on a single line.
  */
-static inline void
-cache_op_r4k_line(register_t va, u_int op)
-{
-	__CTASSERT(__builtin_constant_p(op));
-	__asm volatile(
-		".set push"		"\n\t"
-		".set noreorder"	"\n\t"
-		"cache %[op], 0(%[va])"	"\n\t"
-		".set pop"
-	:
-	: [op] "n" (op), [va] "r" (va)
-	: "memory");
+#define cache_op_r4k_line(va, op)\
+{\
+	__asm volatile(		\
+		".set push"		"\n\t"			\
+		".set noreorder"	"\n\t"			\
+		"cache %0, 0(%[va])"	"\n\t"			\
+		".set pop"	\
+	:			\
+	: "i" (op), [va] "r" (va)\
+	: "memory");	\
 }
 
 /*
@@ -122,50 +120,47 @@ cache_r4k_op_8lines_NN(size_t n, registe
  *
  *	Perform the specified cache operation on 32 n-byte cache lines.
  */
-static inline void
-cache_r4k_op_32lines_NN(size_t n, register_t va, u_int op)
-{
-	__CTASSERT(__builtin_constant_p(n));
-	__CTASSERT(__builtin_constant_p(op));
-	__asm volatile(
-		".set push"			"\n\t"
-		".set noreorder"		"\n\t"
-		"cache %[op], (0*%[n])(%[va])"	"\n\t"
-		"cache %[op], (1*%[n])(%[va])"	"\n\t"
-		"cache %[op], (2*%[n])(%[va])"	"\n\t"
-		"cache %[op], (3*%[n])(%[va])"	"\n\t"
-		"cache %[op], (4*%[n])(%[va])"	"\n\t"
-		"cache %[op], (5*%[n])(%[va])"	"\n\t"
-		"cache %[op], (6*%[n])(%[va])"	"\n\t"
-		"cache %[op], (7*%[n])(%[va])"	"\n\t"
-		"cache %[op], (8*%[n])(%[va])"	"\n\t"
-		"cache %[op], (9*%[n])(%[va])"	"\n\t"
-		"cache %[op], (10*%[n])(%[va])"	"\n\t"
-		"cache %[op], (11*%[n])(%[va])"	"\n\t"
-		"cache %[op], (12*%[n])(%[va])"	"\n\t"
-		"cache %[op], (13*%[n])(%[va])"	"\n\t"
-		"cache %[op], (14*%[n])(%[va])"	"\n\t"
-		"cache %[op], (15*%[n])(%[va])"	"\n\t"
-		"cache %[op], (16*%[n])(%[va])"	"\n\t"
-		"cache %[op], (17*%[n])(%[va])"	"\n\t"
-		"cache %[op], (18*%[n])(%[va])"	"\n\t"
-		"cache %[op], (19*%[n])(%[va])"	"\n\t"
-		"cache %[op], (20*%[n])(%[va])"	"\n\t"
-		"cache %[op], (21*%[n])(%[va])"	"\n\t"
-		"cache %[op], (22*%[n])(%[va])"	"\n\t"
-		"cache %[op], (23*%[n])(%[va])"	"\n\t"
-		"cache %[op], (24*%[n])(%[va])"	"\n\t"
-		"cache %[op], (25*%[n])(%[va])"	"\n\t"
-		"cache %[op], (26*%[n])(%[va])"	"\n\t"
-		"cache %[op], (27*%[n])(%[va])"	"\n\t"
-		"cache %[op], (28*%[n])(%[va])"	"\n\t"
-		"cache %[op], (29*%[n])(%[va])"	"\n\t"
-		"cache %[op], (30*%[n])(%[va])"	"\n\t"
-		"cache %[op], (31*%[n])(%[va])"	"\n\t"
-		".set pop"
-	:
-	:	[n] "n" ((uint8_t)n), [va] "r" (va), [op] "i" ((uint8_t)op)
-	:	"memory");
+#define cache_r4k_op_32lines_NN(n, va, op)\
+{	\
+	__asm volatile(			\
+		".set push"			"\n\t"			\
+		".set noreorder"		"\n\t"			\
+		"cache %2, (0*%0)(%[va])"	"\n\t"			\
+		"cache %2, (1*%0)(%[va])"	"\n\t"			\
+		"cache %2, (2*%0)(%[va])"	"\n\t"			\
+		"cache %2, (3*%0)(%[va])"	"\n\t"			\
+		"cache %2, (4*%0)(%[va])"	"\n\t"			\
+		"cache %2, (5*%0)(%[va])"	"\n\t"			\
+		"cache %2, (6*%0)(%[va])"	"\n\t"			\
+		"cache %2, (7*%0)(%[va])"	"\n\t"			\
+		"cache %2, (8*%0)(%[va])"	"\n\t"			\
+		"cache %2, (9*%0)(%[va])"	"\n\t"			\
+		"cache %2, (10*%0)(%[va])"	"\n\t"			\
+		"cache %2, (11*%0)(%[va])"	"\n\t"			\
+		"cache %2, (12*%0)(%[va])"	"\n\t"			\
+		"cache %2, (13*%0)(%[va])"	"\n\t"			\
+		"cache %2, (14*%0)(%[va])"	"\n\t"			\
+		"cache %2, (15*%0)(%[va])"	"\n\t"			\
+		"cache %2, (16*%0)(%[va])"	"\n\t"			\
+		"cache %2, (17*%0)(%[va])"	"\n\t"			\
+		"cache %2, (18*%0)(%[va])"	"\n\t"			\
+		"cache %2, (19*%0)(%[va])"	"\n\t"			\
+		"cache %2, (20*%0)(%[va])"	"\n\t"			\
+		"cache %2, (21*%0)(%[va])"	"\n\t"			\
+		"cache %2, (22*%0)(%[va])"	"\n\t"			\
+		"cache %2, (23*%0)(%[va])"	"\n\t"			\
+		"cache %2, (24*%0)(%[va])"	"\n\t"			\
+		"cache %2, (25*%0)(%[va])"	"\n\t"			\
+		"cache %2, (26*%0)(%[va])"	"\n\t"			\
+		"cache %2, (27*%0)(%[va])"	"\n\t"			\
+		"cache %2, (28*%0)(%[va])"	"\n\t"			\
+		"cache %2, (29*%0)(%[va])"	"\n\t"			\
+		"cache %2, (30*%0)(%[va])"	"\n\t"			\
+		"cache %2, (31*%0)(%[va])"	"\n\t"			\
+		".set pop"		\
+	:\
+	:	"i" (n), [va] "r" (va), "i" (op)			\
+	:	"memory");		\
 }
 
 /*
@@ -174,13 +169,13 @@ cache_r4k_op_32lines_NN(size_t n, regist
  *	

CVS commit: src/sys/arch/mips/include

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Tue Jul 12 14:24:14 UTC 2016

Modified Files:
src/sys/arch/mips/include: cache_r4k.h

Log Message:
Fix RCSId


To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/mips/include/cache_r4k.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/cache_r4k.h
diff -u src/sys/arch/mips/include/cache_r4k.h:1.14 src/sys/arch/mips/include/cache_r4k.h:1.15
--- src/sys/arch/mips/include/cache_r4k.h:1.14	Mon Jul 11 23:06:54 2016
+++ src/sys/arch/mips/include/cache_r4k.h	Tue Jul 12 14:24:13 2016
@@ -1,4 +1,4 @@
-/*	cache_r4k.h,v 1.11.96.3 2012/01/19 08:28:48 matt Exp	*/
+/*	$NetBSD: cache_r4k.h,v 1.15 2016/07/12 14:24:13 skrll Exp $	*/
 
 /*
  * Copyright 2001 Wasabi Systems, Inc.

CVS commit: src/sys/arch/mips/include

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Mon Jul 11 19:06:33 UTC 2016

Modified Files:
src/sys/arch/mips/include: cache_r4k.h

Log Message:
Trailing whitespace


To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/mips/include/cache_r4k.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/cache_r4k.h
diff -u src/sys/arch/mips/include/cache_r4k.h:1.12 src/sys/arch/mips/include/cache_r4k.h:1.13
--- src/sys/arch/mips/include/cache_r4k.h:1.12	Mon Jul 11 16:15:35 2016
+++ src/sys/arch/mips/include/cache_r4k.h	Mon Jul 11 19:06:33 2016
@@ -389,5 +389,5 @@ void	cache_r4k_sdcache_index_wb_inv_128(
 void	cache_r4k_sdcache_hit_inv_128(register_t, vsize_t);
 void	cache_r4k_sdcache_hit_wb_inv_128(register_t, vsize_t);
 void	cache_r4k_sdcache_hit_wb_128(register_t, vsize_t);
-
+ 
 #endif /* !_LOCORE */

CVS commit: src/sys/arch/mips/include

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Mon Jul 11 19:05:57 UTC 2016

Modified Files:
src/sys/arch/mips/include: cpu.h

Log Message:
Remove commented #include


To generate a diff of this commit:
cvs rdiff -u -r1.118 -r1.119 src/sys/arch/mips/include/cpu.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/cpu.h
diff -u src/sys/arch/mips/include/cpu.h:1.118 src/sys/arch/mips/include/cpu.h:1.119
--- src/sys/arch/mips/include/cpu.h:1.118	Mon Jul 11 16:15:35 2016
+++ src/sys/arch/mips/include/cpu.h	Mon Jul 11 19:05:57 2016
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpu.h,v 1.118 2016/07/11 16:15:35 matt Exp $	*/
+/*	$NetBSD: cpu.h,v 1.119 2016/07/11 19:05:57 skrll Exp $	*/
 
 /*-
  * Copyright (c) 1992, 1993
@@ -37,8 +37,6 @@
 #ifndef _CPU_H_
 #define _CPU_H_
 
-//#include 
-
 /*
  * Exported definitions unique to NetBSD/mips cpu support.
  */

CVS commit: src/sys/arch/mips/include

[Martin Husemann]

Module Name:src
Committed By:   martin
Date:   Thu Jun  9 05:43:51 UTC 2016

Modified Files:
src/sys/arch/mips/include: Makefile.inc

Log Message:
Sync register number for curlwp with the kernel


To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/mips/include/Makefile.inc

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/Makefile.inc
diff -u src/sys/arch/mips/include/Makefile.inc:1.9 src/sys/arch/mips/include/Makefile.inc:1.10
--- src/sys/arch/mips/include/Makefile.inc:1.9	Fri Jan 21 15:59:07 2011
+++ src/sys/arch/mips/include/Makefile.inc	Thu Jun  9 05:43:51 2016
@@ -1,6 +1,6 @@
-# $NetBSD: Makefile.inc,v 1.9 2011/01/21 15:59:07 joerg Exp $
+# $NetBSD: Makefile.inc,v 1.10 2016/06/09 05:43:51 martin Exp $
 
-CFLAGS+=	-G 0 -ffixed-23
+CFLAGS+=	-G 0 -ffixed-24
 
 # this should really be !(RUMPKERNEL && target=PIC)
 .if !defined(RUMPKERNEL)

CVS commit: src/sys/arch/mips/include

[Christos Zoulas]

Module Name:src
Committed By:   christos
Date:   Sun Jan 24 16:08:05 UTC 2016

Modified Files:
src/sys/arch/mips/include: types.h

Log Message:
expose label_t for _KMEMUSER


To generate a diff of this commit:
cvs rdiff -u -r1.62 -r1.63 src/sys/arch/mips/include/types.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/types.h
diff -u src/sys/arch/mips/include/types.h:1.62 src/sys/arch/mips/include/types.h:1.63
--- src/sys/arch/mips/include/types.h:1.62	Sun Jan 24 11:00:45 2016
+++ src/sys/arch/mips/include/types.h	Sun Jan 24 11:08:05 2016
@@ -1,4 +1,4 @@
-/*	$NetBSD: types.h,v 1.62 2016/01/24 16:00:45 christos Exp $	*/
+/*	$NetBSD: types.h,v 1.63 2016/01/24 16:08:05 christos Exp $	*/
 
 /*-
  * Copyright (c) 1992, 1993
@@ -109,9 +109,7 @@ typedef __uint64_t	uregister32_t;
 #define	PRIxREGISTER	PRIx64
 #define	PRIxUREGISTER	PRIx64
 #endif /* __mips_o32 */
-#endif /* _KERNEL || _KMEMUSER*/
 
-#if defined(_KERNEL)
 typedef struct label_t {
 	register_t val[14];
 } label_t;

CVS commit: src/sys/arch/mips/include

[Christos Zoulas]

Module Name:src
Committed By:   christos
Date:   Sun Jan 24 16:00:29 UTC 2016

Modified Files:
src/sys/arch/mips/include: signal.h

Log Message:
use namespace protected types.


To generate a diff of this commit:
cvs rdiff -u -r1.29 -r1.30 src/sys/arch/mips/include/signal.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/signal.h
diff -u src/sys/arch/mips/include/signal.h:1.29 src/sys/arch/mips/include/signal.h:1.30
--- src/sys/arch/mips/include/signal.h:1.29	Sun Dec 13 19:46:05 2009
+++ src/sys/arch/mips/include/signal.h	Sun Jan 24 11:00:29 2016
@@ -1,4 +1,4 @@
-/*	$NetBSD: signal.h,v 1.29 2009/12/14 00:46:05 matt Exp $	*/
+/*	$NetBSD: signal.h,v 1.30 2016/01/24 16:00:29 christos Exp $	*/
 
 /*
  * Copyright (c) 1992, 1993
@@ -106,7 +106,7 @@ struct sigcontext { \
 _SIGCONTEXT_DEFINE(sigcontext, int, int);
 #endif
 #ifdef _LIBC
-_SIGCONTEXT_DEFINE(sigcontext, register_t, fpregister_t);
+_SIGCONTEXT_DEFINE(sigcontext, __register_t, __fpregister_t);
 #endif
 
 #endif /* _LIBC || _KERNEL */

CVS commit: src/sys/arch/mips/include

[Christos Zoulas]

Module Name:src
Committed By:   christos
Date:   Sun Jan 24 16:13:19 UTC 2016

Modified Files:
src/sys/arch/mips/include: reg.h

Log Message:
use namespace protected types.


To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/mips/include/reg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/reg.h
diff -u src/sys/arch/mips/include/reg.h:1.15 src/sys/arch/mips/include/reg.h:1.16
--- src/sys/arch/mips/include/reg.h:1.15	Tue Aug 16 02:58:15 2011
+++ src/sys/arch/mips/include/reg.h	Sun Jan 24 11:13:19 2016
@@ -1,4 +1,4 @@
-/*	$NetBSD: reg.h,v 1.15 2011/08/16 06:58:15 matt Exp $	*/
+/*	$NetBSD: reg.h,v 1.16 2016/01/24 16:13:19 christos Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -43,15 +43,15 @@
 
 
 struct reg {
-	mips_reg_t	r_regs[38];
+	__register_t	r_regs[38];
 };
 
 struct fpreg {
-	mips_fpreg_t	r_regs[33];
+	__fpregister_t	r_regs[33];
 };
 
 struct dspreg {
-	mips_reg_t	r_regs[8];
+	__register_t	r_regs[8];
 };
 
 #if defined(__mips_n32) || defined(__mips_n64)

CVS commit: src/sys/arch/mips/include

[Christos Zoulas]

Module Name:src
Committed By:   christos
Date:   Fri Dec 25 06:01:38 UTC 2015

Modified Files:
src/sys/arch/mips/include: ieeefp.h

Log Message:
remove dup fenv


To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/mips/include/ieeefp.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/ieeefp.h
diff -u src/sys/arch/mips/include/ieeefp.h:1.7 src/sys/arch/mips/include/ieeefp.h:1.8
--- src/sys/arch/mips/include/ieeefp.h:1.7	Mon Mar 19 18:24:07 2012
+++ src/sys/arch/mips/include/ieeefp.h	Fri Dec 25 01:01:38 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: ieeefp.h,v 1.7 2012/03/19 22:24:07 matt Exp $	*/
+/*	$NetBSD: ieeefp.h,v 1.8 2015/12/25 06:01:38 christos Exp $	*/
 
 /*
  * Written by J.T. Conklin, Apr 11, 1995
@@ -12,21 +12,7 @@
 
 #if defined(_NETBSD_SOURCE) || defined(_ISOC99_SOURCE)
 
-typedef unsigned int fenv_t;
-typedef unsigned int fexcept_t;
-
-#define	FE_INEXACT	0x01	/* imprecise (loss of precision) */
-#define	FE_UNDERFLOW	0x02	/* underflow exception */
-#define	FE_OVERFLOW	0x04	/* overflow exception */
-#define	FE_DIVBYZERO	0x08	/* divide-by-zero exception */
-#define	FE_INVALID	0x10	/* invalid operation exception */
-
-#define	FE_ALL_EXCEPT	0x1f
-
-#define	FE_TONEAREST	0	/* round to nearest representable number */
-#define	FE_TOWARDZERO	1	/* round to zero (truncate) */
-#define	FE_UPWARD	2	/* round toward positive infinity */
-#define	FE_DOWNWARD	3	/* round toward negative infinity */
+#include 
 
 #if !defined(_ISOC99_SOURCE)
 

CVS commit: src/sys/arch/mips/include

[Matt Thomas]

Module Name:src
Committed By:   matt
Date:   Tue Jun 30 03:41:04 UTC 2015

Modified Files:
src/sys/arch/mips/include: vmparam.h

Log Message:
We support multiple page sizes so let modules know it.


To generate a diff of this commit:
cvs rdiff -u -r1.52 -r1.53 src/sys/arch/mips/include/vmparam.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/vmparam.h
diff -u src/sys/arch/mips/include/vmparam.h:1.52 src/sys/arch/mips/include/vmparam.h:1.53
--- src/sys/arch/mips/include/vmparam.h:1.52	Sat Jan 25 15:16:50 2014
+++ src/sys/arch/mips/include/vmparam.h	Tue Jun 30 03:41:04 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: vmparam.h,v 1.52 2014/01/25 15:16:50 christos Exp $	*/
+/*	$NetBSD: vmparam.h,v 1.53 2015/06/30 03:41:04 matt Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -49,6 +49,8 @@
 /*
  * Machine dependent VM constants for MIPS.
  */
+#define MAX_PAGE_SIZE	16384
+#define MIN_PAGE_SIZE	4096
 
 /*
  * We normally use a 4K page but may use 16K on MIPS systems.

CVS commit: src/sys/arch/mips/include

[Matt Thomas]

Module Name:src
Committed By:   matt
Date:   Tue Jun 30 04:20:19 UTC 2015

Modified Files:
src/sys/arch/mips/include: proc.h vmparam.h

Log Message:
Make vmparam.h change work with RUMP


To generate a diff of this commit:
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/mips/include/proc.h
cvs rdiff -u -r1.53 -r1.54 src/sys/arch/mips/include/vmparam.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/proc.h
diff -u src/sys/arch/mips/include/proc.h:1.27 src/sys/arch/mips/include/proc.h:1.28
--- src/sys/arch/mips/include/proc.h:1.27	Sun Feb 20 07:45:47 2011
+++ src/sys/arch/mips/include/proc.h	Tue Jun 30 04:20:19 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: proc.h,v 1.27 2011/02/20 07:45:47 matt Exp $	*/
+/*	$NetBSD: proc.h,v 1.28 2015/06/30 04:20:19 matt Exp $	*/
 
 /*
  * Copyright (c) 1992, 1993
@@ -52,11 +52,7 @@ struct mdlwp {
 	vaddr_t	md_ss_addr;		/* single step address for ptrace */
 	int	md_ss_instr;		/* single step instruction for ptrace */
 	volatile int md_astpending;	/* AST pending on return to userland */
-#if USPACE  PAGE_SIZE
-	int	md_upte[USPACE/4096];	/* ptes for mapping u page */
-#else
-	int	md_dpte[USPACE/4096];	/* dummy ptes to keep the same */
-#endif
+	int	md_upte[2];		/* ptes for mapping u page */
 };
 
 struct mdproc {

Index: src/sys/arch/mips/include/vmparam.h
diff -u src/sys/arch/mips/include/vmparam.h:1.53 src/sys/arch/mips/include/vmparam.h:1.54
--- src/sys/arch/mips/include/vmparam.h:1.53	Tue Jun 30 03:41:04 2015
+++ src/sys/arch/mips/include/vmparam.h	Tue Jun 30 04:20:19 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: vmparam.h,v 1.53 2015/06/30 03:41:04 matt Exp $	*/
+/*	$NetBSD: vmparam.h,v 1.54 2015/06/30 04:20:19 matt Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -42,15 +42,18 @@
 #define	_MIPS_VMPARAM_H_
 
 #ifdef _KERNEL_OPT
-#include opt_multiprocessor.h
 #include opt_cputype.h
+#include opt_multiprocessor.h
+#include opt_modular.h
 #endif
 
 /*
  * Machine dependent VM constants for MIPS.
  */
+#if !defined(_RUMPKERNEL)  (defined(MODULAR) || defined(_MODULE))
 #define MAX_PAGE_SIZE	16384
 #define MIN_PAGE_SIZE	4096
+#endif
 
 /*
  * We normally use a 4K page but may use 16K on MIPS systems.

CVS commit: src/sys/arch/mips/include

[Matt Thomas]

Module Name:src
Committed By:   matt
Date:   Sat Jun 27 21:44:06 UTC 2015

Modified Files:
src/sys/arch/mips/include: pte.h

Log Message:
Remove unused struct pt_entry_t union.


To generate a diff of this commit:
cvs rdiff -u -r1.21 -r1.22 src/sys/arch/mips/include/pte.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/pte.h
diff -u src/sys/arch/mips/include/pte.h:1.21 src/sys/arch/mips/include/pte.h:1.22
--- src/sys/arch/mips/include/pte.h:1.21	Thu Jun 11 08:22:09 2015
+++ src/sys/arch/mips/include/pte.h	Sat Jun 27 21:44:06 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: pte.h,v 1.21 2015/06/11 08:22:09 matt Exp $	*/
+/*	$NetBSD: pte.h,v 1.22 2015/06/27 21:44:06 matt Exp $	*/
 
 /*-
  * Copyright (c) 1997 The NetBSD Foundation, Inc.
@@ -56,8 +56,10 @@
 
 typedef union pt_entry {
 	uint32_t	 pt_entry;	/* for copying, etc. */
+#if 0
 	struct mips1_pte pt_mips1_pte;	/* for getting to bits by name */
 	struct mips3_pte pt_mips3_pte;
+#endif
 } pt_entry_t;
 
 /*

CVS commit: src/sys/arch/mips/include

[Matt Thomas]

Module Name:src
Committed By:   matt
Date:   Fri Jun 26 22:56:36 UTC 2015

Modified Files:
src/sys/arch/mips/include: mips1_pte.h

Log Message:
ifdef out bitfield struct for pte (not used).


To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/mips/include/mips1_pte.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/mips1_pte.h
diff -u src/sys/arch/mips/include/mips1_pte.h:1.19 src/sys/arch/mips/include/mips1_pte.h:1.20
--- src/sys/arch/mips/include/mips1_pte.h:1.19	Sun Feb 20 07:45:47 2011
+++ src/sys/arch/mips/include/mips1_pte.h	Fri Jun 26 22:56:36 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: mips1_pte.h,v 1.19 2011/02/20 07:45:47 matt Exp $	*/
+/*	$NetBSD: mips1_pte.h,v 1.20 2015/06/26 22:56:36 matt Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -45,6 +45,7 @@
  */
 
 #ifndef _LOCORE
+#if 0
 struct mips1_pte {
 #if BYTE_ORDER == BIG_ENDIAN
 unsigned int	pg_pfnum:20,		/* HW: core page frame number or 0 */
@@ -69,6 +70,7 @@ unsigned int	pg_prot:2,		/* SW: access c
 		pg_pfnum:20;		/* HW: core page frame number or 0 */
 #endif
 };
+#endif
 #endif /* _LOCORE */
 
 #define	MIPS1_PG_PROT	0x0003

CVS commit: src/sys/arch/mips/include

[Matt Thomas]

Module Name:src
Committed By:   matt
Date:   Sat Jun 27 03:30:01 UTC 2015

Modified Files:
src/sys/arch/mips/include: mips_opcode.h

Log Message:
More instructions


To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/mips/include/mips_opcode.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/mips_opcode.h
diff -u src/sys/arch/mips/include/mips_opcode.h:1.20 src/sys/arch/mips/include/mips_opcode.h:1.21
--- src/sys/arch/mips/include/mips_opcode.h:1.20	Thu Jun  4 02:26:49 2015
+++ src/sys/arch/mips/include/mips_opcode.h	Sat Jun 27 03:30:01 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: mips_opcode.h,v 1.20 2015/06/04 02:26:49 matt Exp $	*/
+/*	$NetBSD: mips_opcode.h,v 1.21 2015/06/27 03:30:01 matt Exp $	*/
 
 /*-
  * Copyright (c) 1992, 1993
@@ -150,6 +150,8 @@ typedef union {
 #define OP_LDR		033		/* MIPS-II, for r4000 port */
 
 #define OP_SPECIAL2	034		/* QED opcodes */
+#define OP_JALX		035
+#define OP_MDMX		036
 #define OP_SPECIAL3	037
 
 #define OP_LB		040
@@ -309,14 +311,30 @@ typedef union {
 #define OP_DINSU	006		/* MIPS32/64 r2 */
 #define OP_DINS		007		/* MIPS32/64 r2 */
 #define	OP_LX		012		/* DSP */
+#define OP_LWLE		031		/* EVA */
+#define OP_LWRE		032		/* EVA */
+#define OP_CACHEE	033		/* EVA */
+#define OP_SBE		034		/* EVA */
+#define OP_SHE		035		/* EVA */
+#define OP_SCE		035		/* EVA */
+#define OP_SWE		035		/* EVA */
 #define OP_BSHFL	040		/* MIPS32/64 r2 */
+#define OP_SWLE		041		/* EVA */
+#define OP_SWRE		042		/* EVA */
+#define OP_PREFE	043		/* EVA */
 #define OP_DBSHFL	044		/* MIPS32/64 r2 */
+#define OP_LBUE		050		/* EVA */
+#define OP_LHUE		051		/* EVA */
+#define OP_LBE		054		/* EVA */
+#define OP_LHE		055		/* EVA */
+#define OP_LLE		056		/* EVA */
+#define OP_LWE		057		/* EVA */
 #define OP_RDHWR	073		/* MIPS32/64 r2 */
 
-#define OP_BSHFL_SBH	2		/* swap bytes within halfwords */
-#define OP_BSHFL_SHD	4		/* swap halfworks within double */
-#define OP_BSHFL_SEB	16		/* sign extend byte */
-#define OP_BSHFL_SEH	24		/* sign extend halfword */
+#define OP_BSHFL_SBH	002		/* swap bytes within halfwords */
+#define OP_BSHFL_SHD	005		/* swap halfworks within double */
+#define OP_BSHFL_SEB	020		/* sign extend byte */
+#define OP_BSHFL_SEH	030		/* sign extend halfword */
 
 #define	OP_LX_LWX	0		/* lwx */
 #define	OP_LX_LHX	4		/* lhx */

CVS commit: src/sys/arch/mips/include

[Matt Thomas]

Module Name:src
Committed By:   matt
Date:   Fri Jun 12 16:28:39 UTC 2015

Modified Files:
src/sys/arch/mips/include: kcore.h

Log Message:
Add back sysmapsize


To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/mips/include/kcore.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/include/kcore.h
diff -u src/sys/arch/mips/include/kcore.h:1.2 src/sys/arch/mips/include/kcore.h:1.3
--- src/sys/arch/mips/include/kcore.h:1.2	Thu Jun 11 15:36:26 2015
+++ src/sys/arch/mips/include/kcore.h	Fri Jun 12 16:28:39 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: kcore.h,v 1.2 2015/06/11 15:36:26 matt Exp $	*/
+/*	$NetBSD: kcore.h,v 1.3 2015/06/12 16:28:39 matt Exp $	*/
 
 /*
  * Copyright (c) 1996 Carnegie-Mellon University.
@@ -37,6 +37,7 @@
 
 typedef struct cpu_kcore_hdr {
 	uint64_t	sysmappa;		/* PA of Sysmap */
+	uint32_t	sysmapsize;		/* size of Sysmap */
 	uint32_t	archlevel;		/* MIPS architecture level */
 	uint32_t	pg_shift;		/* PTE page frame num shift */
 	uint32_t	pg_frame;		/* PTE page frame num mask */