subject:"CVS commit\: src\/usr.sbin\/cpuctl\/arch"

CVS commit: src/usr.sbin/cpuctl/arch

2021-07-12 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Mon Jul 12 12:56:52 UTC 2021

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
 Add 0x96(Elkhart Lake) and 0x9c(Jasper Lake).
Not listed in SDM but listed in those spec update documents.


To generate a diff of this commit:
cvs rdiff -u -r1.116 -r1.117 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.116 src/usr.sbin/cpuctl/arch/i386.c:1.117
--- src/usr.sbin/cpuctl/arch/i386.c:1.116	Sat Jul 10 17:18:05 2021
+++ src/usr.sbin/cpuctl/arch/i386.c	Mon Jul 12 12:56:52 2021
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.116 2021/07/10 17:18:05 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.117 2021/07/12 12:56:52 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.116 2021/07/10 17:18:05 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.117 2021/07/12 12:56:52 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -354,6 +354,8 @@ const struct cpu_cpuid_nameclass i386_cp
 [0x8c] = "11th gen Core (Tiger Lake)",
 [0x8d] = "11th gen Core (Tiger Lake)",
 [0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)",
+[0x96] = "Atom x6000E (Elkhart Lake)",
+[0x9c] = "Pentium Silver N6xxx, Celeron N45xx, Celeron N51xx (Jasper Lake)",
 [0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)",
 [0xa5] = "10th gen Core (Comet Lake)",
 [0xa6] = "10th gen Core (Comet Lake)",

CVS commit: src/usr.sbin/cpuctl/arch

2021-07-10 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Sat Jul 10 17:18:05 UTC 2021

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
0x6a and 0x6c are 3rd gen Xeon Scalable (Ice Lake).


To generate a diff of this commit:
cvs rdiff -u -r1.115 -r1.116 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.115 src/usr.sbin/cpuctl/arch/i386.c:1.116
--- src/usr.sbin/cpuctl/arch/i386.c:1.115	Tue Nov 24 00:48:39 2020
+++ src/usr.sbin/cpuctl/arch/i386.c	Sat Jul 10 17:18:05 2021
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.115 2020/11/24 00:48:39 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.116 2021/07/10 17:18:05 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.115 2020/11/24 00:48:39 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.116 2021/07/10 17:18:05 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -344,8 +344,8 @@ const struct cpu_cpuid_nameclass i386_cp
 [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
 [0x5f] = "Atom (Goldmont, Denverton)",
 [0x66] = "8th gen Core i3 (Cannon Lake)",
-[0x6a] = "Future Xeon (Ice Lake)",
-[0x6c] = "Future Xeon (Ice Lake)",
+[0x6a] = "3rd gen Xeon Scalable (Ice Lake)",
+[0x6c] = "3rd gen Xeon Scalable (Ice Lake)",
 [0x7a] = "Atom (Goldmont Plus)",
 [0x7d] = "10th gen Core (Ice Lake)",
 [0x7e] = "10th gen Core (Ice Lake)",

CVS commit: src/usr.sbin/cpuctl/arch

2021-05-17 Thread Taylor R Campbell

Module Name:src
Committed By:   riastradh
Date:   Mon May 17 18:43:18 UTC 2021

Modified Files:
src/usr.sbin/cpuctl/arch: aarch64.c

Log Message:
Teach cpuctl(8) about some additional aarch64 feature bits.

(Descriptions for CSV3 and CSV2 are not very good, but the blurbs in
the arm arm are an entire paragraph long each.  Please fix if you have
a conciser summary!)


To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/usr.sbin/cpuctl/arch/aarch64.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/aarch64.c
diff -u src/usr.sbin/cpuctl/arch/aarch64.c:1.14 src/usr.sbin/cpuctl/arch/aarch64.c:1.15
--- src/usr.sbin/cpuctl/arch/aarch64.c:1.14	Sat Jan 16 15:34:37 2021
+++ src/usr.sbin/cpuctl/arch/aarch64.c	Mon May 17 18:43:18 2021
@@ -1,4 +1,4 @@
-/*	$NetBSD: aarch64.c,v 1.14 2021/01/16 15:34:37 jmcneill Exp $	*/
+/*	$NetBSD: aarch64.c,v 1.15 2021/05/17 18:43:18 riastradh Exp $	*/
 
 /*
  * Copyright (c) 2018 Ryo Shimizu 
@@ -29,7 +29,7 @@
 #include 
 
 #ifndef lint
-__RCSID("$NetBSD: aarch64.c,v 1.14 2021/01/16 15:34:37 jmcneill Exp $");
+__RCSID("$NetBSD: aarch64.c,v 1.15 2021/05/17 18:43:18 riastradh Exp $");
 #endif /* no lint */
 
 #include 
@@ -169,6 +169,66 @@ struct fieldinfo id_aa64pfr0_fieldinfo[]
 			[3] = "GIC CPU interface sysregs v4.1 supported"
 		}
 	},
+	{
+		.bitpos = 28, .bitwidth = 4, .name = "RAS",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "Reliability/Availability/Serviceability not supported",
+			[1] = "Reliability/Availability/Serviceability supported",
+			[2] = "Reliability/Availability/Serviceability ARMv8.4 supported",
+		},
+	},
+	{
+		.bitpos = 32, .bitwidth = 4, .name = "SVE",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "Scalable Vector Extensions not implemented",
+			[1] = "Scalable Vector Extensions implemented",
+		},
+	},
+	{
+		.bitpos = 36, .bitwidth = 4, .name = "SEL2",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "Secure EL2 not implemented",
+			[1] = "Secure EL2 implemented",
+		},
+	},
+	{
+		.bitpos = 40, .bitwidth = 4, .name = "MPAM",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "Memory Partitioning and Monitoring not implemented",
+			[1] = "Memory Partitioning and Monitoring implemented",
+		},
+	},
+	{
+		.bitpos = 44, .bitwidth = 4, .name = "AMU",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "Activity Monitors Extension not implemented",
+			[1] = "Activity Monitors Extension v1 ARMv8.4",
+			[2] = "Activity Monitors Extension v1 ARMv8.6",
+		},
+	},
+	{
+		.bitpos = 48, .bitwidth = 4, .name = "DIT",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "No Data-Independent Timing guarantees",
+			[1] = "Data-Independent Timing guaranteed by PSTATE.DIT",
+		},
+	},
+	{
+		.bitpos = 56, .bitwidth = 4, .name = "CSV2",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "Branch prediction might be Spectred",
+			[1] = "Branch prediction maybe not Spectred",
+			[2] = "Branch prediction probably not Spectred",
+		},
+	},
+	{
+		.bitpos = 60, .bitwidth = 4, .name = "CSV3",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "Faults might be Spectred",
+			[1] = "Faults maybe not Spectred",
+			[2] = "Faults probably not Spectred",
+		},
+	},
 	{ .bitwidth = 0 }	/* end of table */
 };

CVS commit: src/usr.sbin/cpuctl/arch

2021-01-16 Thread Jared D. McNeill

Module Name:src
Committed By:   jmcneill
Date:   Sat Jan 16 15:35:28 UTC 2021

Modified Files:
src/usr.sbin/cpuctl/arch: arm.c

Log Message:
trailing whitespace


To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/usr.sbin/cpuctl/arch/arm.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/arm.c
diff -u src/usr.sbin/cpuctl/arch/arm.c:1.3 src/usr.sbin/cpuctl/arch/arm.c:1.4
--- src/usr.sbin/cpuctl/arch/arm.c:1.3	Sun Feb  3 10:48:47 2019
+++ src/usr.sbin/cpuctl/arch/arm.c	Sat Jan 16 15:35:28 2021
@@ -1,4 +1,4 @@
-/*	$NetBSD: arm.c,v 1.3 2019/02/03 10:48:47 mrg Exp $	*/
+/*	$NetBSD: arm.c,v 1.4 2021/01/16 15:35:28 jmcneill Exp $	*/
 
 /*-
  * Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
 #include 
 
 #ifndef lint
-__RCSID("$NetBSD: arm.c,v 1.3 2019/02/03 10:48:47 mrg Exp $");
+__RCSID("$NetBSD: arm.c,v 1.4 2021/01/16 15:35:28 jmcneill Exp $");
 #endif /* not lint */
 
 #include 
@@ -81,32 +81,32 @@ static const char * const id_mmfr_fieldn
 		"FCSE-Support",
 		"Innermost-Shareability"
 	}, {
-		"L1-Harvard-Cache-VA", 
-		"L1-Unified-Cache-VA", 
-		"L1-Harvard-Cache-Set/Way", 
-		"L1-Unified-Cache-Set/Way", 
-		"L1-Harvard-Cache", 
-		"L1-Unified-Cache", 
-		"L1-Cache-Test-and-Clean", 
-		"Branch-Predictor", 
+		"L1-Harvard-Cache-VA",
+		"L1-Unified-Cache-VA",
+		"L1-Harvard-Cache-Set/Way",
+		"L1-Unified-Cache-Set/Way",
+		"L1-Harvard-Cache",
+		"L1-Unified-Cache",
+		"L1-Cache-Test-and-Clean",
+		"Branch-Predictor",
 	}, {
-		"L1-Harvard-Foreground-Fetch", 
-		"L1-Unified-Background-Fetch", 
-		"L1-Harvard-Range", 
+		"L1-Harvard-Foreground-Fetch",
+		"L1-Unified-Background-Fetch",
+		"L1-Harvard-Range",
 		"Harvard-TLB",
-		"Unified-TLB", 
-		"Mem-Barrier", 
-		"WFI-Stall", 
-		"HW-Access", 
+		"Unified-TLB",
+		"Mem-Barrier",
+		"WFI-Stall",
+		"HW-Access",
 	}, {
-		"Cache-Maintenance-MVA", 
-		"Cache-Maintenance-Set/Way", 
-		"BP-Maintenance", 
+		"Cache-Maintenance-MVA",
+		"Cache-Maintenance-Set/Way",
+		"BP-Maintenance",
 		"Maintenance-Broadcast",
 		NULL,
-		"Coherent-Tablewalk", 
-		"Cached-Memory-Size", 
-		"Supersection-Support", 
+		"Coherent-Tablewalk",
+		"Cached-Memory-Size",
+		"Supersection-Support",
 	},
 };
 
@@ -194,7 +194,7 @@ print_features(const char *cpuname, cons
 "=%u", isar & 0x0f);
 			}
 			size_t tmplen = snprintf(tmpbuf, sizeof(tmpbuf),
-			 "%s%s%s", sep, name, value);   
+			 "%s%s%s", sep, name, value);
 			if (len + tmplen > 78) {
 printf("%s\n", buf);
 len = snprintf(buf, sizeof(buf),

CVS commit: src/usr.sbin/cpuctl/arch

2021-01-16 Thread Jared D. McNeill

Module Name:src
Committed By:   jmcneill
Date:   Sat Jan 16 15:34:37 UTC 2021

Modified Files:
src/usr.sbin/cpuctl/arch: aarch64.c

Log Message:
ID_AA64PFR0_EL1.GIC=0 means that the CPU interface system registers are
not implemented. This does not necessarily mean that there is no GIC in the
system, as GICv2 uses MMIO instead of system registers for the CPU
interface.

While here, add description for GIC=3, which means that the v4.1 system
register interface is supported.


To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/usr.sbin/cpuctl/arch/aarch64.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/aarch64.c
diff -u src/usr.sbin/cpuctl/arch/aarch64.c:1.13 src/usr.sbin/cpuctl/arch/aarch64.c:1.14
--- src/usr.sbin/cpuctl/arch/aarch64.c:1.13	Mon Jan  4 05:35:14 2021
+++ src/usr.sbin/cpuctl/arch/aarch64.c	Sat Jan 16 15:34:37 2021
@@ -1,4 +1,4 @@
-/*	$NetBSD: aarch64.c,v 1.13 2021/01/04 05:35:14 ryo Exp $	*/
+/*	$NetBSD: aarch64.c,v 1.14 2021/01/16 15:34:37 jmcneill Exp $	*/
 
 /*
  * Copyright (c) 2018 Ryo Shimizu 
@@ -29,7 +29,7 @@
 #include 
 
 #ifndef lint
-__RCSID("$NetBSD: aarch64.c,v 1.13 2021/01/04 05:35:14 ryo Exp $");
+__RCSID("$NetBSD: aarch64.c,v 1.14 2021/01/16 15:34:37 jmcneill Exp $");
 #endif /* no lint */
 
 #include 
@@ -164,8 +164,9 @@ struct fieldinfo id_aa64pfr0_fieldinfo[]
 	{
 		.bitpos = 24, .bitwidth = 4, .name = "GIC",
 		.info = (const char *[16]) { /* 16=4bit */
-			[0] = "No GIC",
-			[1] = "GICv3"
+			[0] = "GIC CPU interface sysregs not implemented",
+			[1] = "GIC CPU interface sysregs v3.0/4.0 supported",
+			[3] = "GIC CPU interface sysregs v4.1 supported"
 		}
 	},
 	{ .bitwidth = 0 }	/* end of table */

CVS commit: src/usr.sbin/cpuctl/arch

2021-01-03 Thread Ryo Shimizu

Module Name:src
Committed By:   ryo
Date:   Mon Jan  4 05:35:15 UTC 2021

Modified Files:
src/usr.sbin/cpuctl/arch: aarch64.c

Log Message:
sync cpuids[] of sys/arch/aarch64/aarch64/cpu.c r1.43


To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/usr.sbin/cpuctl/arch/aarch64.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/aarch64.c
diff -u src/usr.sbin/cpuctl/arch/aarch64.c:1.12 src/usr.sbin/cpuctl/arch/aarch64.c:1.13
--- src/usr.sbin/cpuctl/arch/aarch64.c:1.12	Sat Oct 10 08:27:41 2020
+++ src/usr.sbin/cpuctl/arch/aarch64.c	Mon Jan  4 05:35:14 2021
@@ -1,4 +1,4 @@
-/*	$NetBSD: aarch64.c,v 1.12 2020/10/10 08:27:41 jmcneill Exp $	*/
+/*	$NetBSD: aarch64.c,v 1.13 2021/01/04 05:35:14 ryo Exp $	*/
 
 /*
  * Copyright (c) 2018 Ryo Shimizu 
@@ -29,7 +29,7 @@
 #include 
 
 #ifndef lint
-__RCSID("$NetBSD: aarch64.c,v 1.12 2020/10/10 08:27:41 jmcneill Exp $");
+__RCSID("$NetBSD: aarch64.c,v 1.13 2021/01/04 05:35:14 ryo Exp $");
 #endif /* no lint */
 
 #include 
@@ -72,17 +72,25 @@ struct fieldinfo {
 
 #define CPU_PARTMASK	(CPU_ID_IMPLEMENTOR_MASK | CPU_ID_PARTNO_MASK)
 const struct cpuidtab cpuids[] = {
-	{ CPU_ID_CORTEXA53R0 & CPU_PARTMASK, "Cortex-A53", "Cortex", "V8-A" },
-	{ CPU_ID_CORTEXA57R0 & CPU_PARTMASK, "Cortex-A57", "Cortex", "V8-A" },
-	{ CPU_ID_CORTEXA72R0 & CPU_PARTMASK, "Cortex-A72", "Cortex", "V8-A" },
-	{ CPU_ID_CORTEXA73R0 & CPU_PARTMASK, "Cortex-A73", "Cortex", "V8-A" },
-	{ CPU_ID_CORTEXA55R1 & CPU_PARTMASK, "Cortex-A55", "Cortex", "V8.2-A" },
-	{ CPU_ID_CORTEXA75R2 & CPU_PARTMASK, "Cortex-A75", "Cortex", "V8.2-A" },
-	{ CPU_ID_CORTEXA76R3 & CPU_PARTMASK, "Cortex-A76", "Cortex", "V8.2-A" },
-	{ CPU_ID_THUNDERXRX, "Cavium ThunderX", "Cavium", "V8-A" },
-	{ CPU_ID_THUNDERX81XXRX, "Cavium ThunderX CN81XX", "Cavium", "V8-A" },
-	{ CPU_ID_THUNDERX83XXRX, "Cavium ThunderX CN83XX", "Cavium", "V8-A" },
-	{ CPU_ID_THUNDERX2RX, "Cavium ThunderX2", "Cavium", "V8.1-A" },
+	{ CPU_ID_CORTEXA35R0 & CPU_PARTMASK, "Cortex-A35", "Arm", "v8-A" },
+	{ CPU_ID_CORTEXA53R0 & CPU_PARTMASK, "Cortex-A53", "Arm", "v8-A" },
+	{ CPU_ID_CORTEXA57R0 & CPU_PARTMASK, "Cortex-A57", "Arm", "v8-A" },
+	{ CPU_ID_CORTEXA55R1 & CPU_PARTMASK, "Cortex-A55", "Arm", "v8.2-A+" },
+	{ CPU_ID_CORTEXA65R0 & CPU_PARTMASK, "Cortex-A65", "Arm", "v8.2-A+" },
+	{ CPU_ID_CORTEXA72R0 & CPU_PARTMASK, "Cortex-A72", "Arm", "v8-A" },
+	{ CPU_ID_CORTEXA73R0 & CPU_PARTMASK, "Cortex-A73", "Arm", "v8-A" },
+	{ CPU_ID_CORTEXA75R2 & CPU_PARTMASK, "Cortex-A75", "Arm", "v8.2-A+" },
+	{ CPU_ID_CORTEXA76R3 & CPU_PARTMASK, "Cortex-A76", "Arm", "v8.2-A+" },
+	{ CPU_ID_CORTEXA76AER1 & CPU_PARTMASK, "Cortex-A76AE", "Arm", "v8.2-A+" },
+	{ CPU_ID_CORTEXA77R0 & CPU_PARTMASK, "Cortex-A77", "Arm", "v8.2-A+" },
+	{ CPU_ID_NVIDIADENVER2 & CPU_PARTMASK, "Denver2", "NVIDIA", "v8-A" },
+	{ CPU_ID_EMAG8180 & CPU_PARTMASK, "eMAG", "Ampere", "v8-A" },
+	{ CPU_ID_NEOVERSEE1R1 & CPU_PARTMASK, "Neoverse E1", "Arm", "v8.2-A+" },
+	{ CPU_ID_NEOVERSEN1R3 & CPU_PARTMASK, "Neoverse N1", "Arm", "v8.2-A+" },
+	{ CPU_ID_THUNDERXRX, "ThunderX", "Cavium", "v8-A" },
+	{ CPU_ID_THUNDERX81XXRX, "ThunderX CN81XX", "Cavium", "v8-A" },
+	{ CPU_ID_THUNDERX83XXRX, "ThunderX CN83XX", "Cavium", "v8-A" },
+	{ CPU_ID_THUNDERX2RX, "ThunderX2", "Marvell", "v8.1-A" },
 };
 
 const struct impltab implids[] = {

CVS commit: src/usr.sbin/cpuctl/arch

2020-11-23 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Tue Nov 24 00:48:39 UTC 2020

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
- Print CPUID 0x808 %ebx on Intel, too. Intel now supports WBNOINVD.
- Print CPUID leaf 7 subleaf 1.


To generate a diff of this commit:
cvs rdiff -u -r1.114 -r1.115 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.114 src/usr.sbin/cpuctl/arch/i386.c:1.115
--- src/usr.sbin/cpuctl/arch/i386.c:1.114	Sat Sep  5 07:45:44 2020
+++ src/usr.sbin/cpuctl/arch/i386.c	Tue Nov 24 00:48:39 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.114 2020/09/05 07:45:44 maxv Exp $	*/
+/*	$NetBSD: i386.c,v 1.115 2020/11/24 00:48:39 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.114 2020/09/05 07:45:44 maxv Exp $");
+__RCSID("$NetBSD: i386.c,v 1.115 2020/11/24 00:48:39 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -351,6 +351,8 @@ const struct cpu_cpuid_nameclass i386_cp
 [0x7e] = "10th gen Core (Ice Lake)",
 [0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)",
 [0x86] = "Atom (Tremont)",
+[0x8c] = "11th gen Core (Tiger Lake)",
+[0x8d] = "11th gen Core (Tiger Lake)",
 [0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)",
 [0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)",
 [0xa5] = "10th gen Core (Comet Lake)",
@@ -2250,19 +2252,25 @@ identifycpu(int fd, const char *cpuname)
 		x86_cpuid(7, descs);
 		aprint_verbose("%s: SEF highest subleaf %08x\n",
 		cpuname, descs[0]);
+		if (descs[0] >= 1) {
+			x86_cpuid2(7, 1, descs);
+			print_bits(cpuname, "SEF-subleaf1-eax",
+			CPUID_SEF1_FLAGS_A, descs[0]);
+		}
 	}
 
-	if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD))
+	if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) {
 		if (ci->ci_max_ext_cpuid >= 0x8007)
 			powernow_probe(ci);
 
-	if (cpu_vendor == CPUVENDOR_AMD) {
 		if (ci->ci_max_ext_cpuid >= 0x8008) {
 			x86_cpuid(0x8008, descs);
 			print_bits(cpuname, "AMD Extended features",
 			CPUID_CAPEX_FLAGS, descs[1]);
 		}
+	}
 
+	if (cpu_vendor == CPUVENDOR_AMD) {
 		if ((ci->ci_max_ext_cpuid >= 0x800a)
 		&& (ci->ci_feat_val[3] & CPUID_SVM) != 0) {
 			x86_cpuid(0x800a, descs);

CVS commit: src/usr.sbin/cpuctl/arch

2020-10-10 Thread Jared D. McNeill

Module Name:src
Committed By:   jmcneill
Date:   Sat Oct 10 08:27:41 UTC 2020

Modified Files:
src/usr.sbin/cpuctl/arch: aarch64.c

Log Message:
Report half-precision FP and SIMD support


To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/usr.sbin/cpuctl/arch/aarch64.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/aarch64.c
diff -u src/usr.sbin/cpuctl/arch/aarch64.c:1.11 src/usr.sbin/cpuctl/arch/aarch64.c:1.12
--- src/usr.sbin/cpuctl/arch/aarch64.c:1.11	Sun Jul  5 19:40:27 2020
+++ src/usr.sbin/cpuctl/arch/aarch64.c	Sat Oct 10 08:27:41 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: aarch64.c,v 1.11 2020/07/05 19:40:27 riastradh Exp $	*/
+/*	$NetBSD: aarch64.c,v 1.12 2020/10/10 08:27:41 jmcneill Exp $	*/
 
 /*
  * Copyright (c) 2018 Ryo Shimizu 
@@ -29,7 +29,7 @@
 #include 
 
 #ifndef lint
-__RCSID("$NetBSD: aarch64.c,v 1.11 2020/07/05 19:40:27 riastradh Exp $");
+__RCSID("$NetBSD: aarch64.c,v 1.12 2020/10/10 08:27:41 jmcneill Exp $");
 #endif /* no lint */
 
 #include 
@@ -141,6 +141,7 @@ struct fieldinfo id_aa64pfr0_fieldinfo[]
 		.bitpos = 16, .bitwidth = 4, .name = "FP",
 		.info = (const char *[16]) { /* 16=4bit */
 			[0] = "Floating Point",
+			[1] = "Floating Point including half-precision support",
 			[15] = "No Floating Point"
 		}
 	},
@@ -148,6 +149,7 @@ struct fieldinfo id_aa64pfr0_fieldinfo[]
 		.bitpos = 20, .bitwidth = 4, .name = "AdvSIMD",
 		.info = (const char *[16]) { /* 16=4bit */
 			[0] = "Advanced SIMD",
+			[1] = "Advanced SIMD including half-precision support",
 			[15] = "No Advanced SIMD"
 		}
 	},

CVS commit: src/usr.sbin/cpuctl/arch

2020-07-05 Thread Taylor R Campbell

Module Name:src
Committed By:   riastradh
Date:   Sun Jul  5 19:40:27 UTC 2020

Modified Files:
src/usr.sbin/cpuctl/arch: aarch64.c

Log Message:
(cpuctl/aarch64) Add some more aa64isar0_eli1 flags.


To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/usr.sbin/cpuctl/arch/aarch64.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/aarch64.c
diff -u src/usr.sbin/cpuctl/arch/aarch64.c:1.10 src/usr.sbin/cpuctl/arch/aarch64.c:1.11
--- src/usr.sbin/cpuctl/arch/aarch64.c:1.10	Wed Jul  1 08:03:10 2020
+++ src/usr.sbin/cpuctl/arch/aarch64.c	Sun Jul  5 19:40:27 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: aarch64.c,v 1.10 2020/07/01 08:03:10 ryo Exp $	*/
+/*	$NetBSD: aarch64.c,v 1.11 2020/07/05 19:40:27 riastradh Exp $	*/
 
 /*
  * Copyright (c) 2018 Ryo Shimizu 
@@ -29,7 +29,7 @@
 #include 
 
 #ifndef lint
-__RCSID("$NetBSD: aarch64.c,v 1.10 2020/07/01 08:03:10 ryo Exp $");
+__RCSID("$NetBSD: aarch64.c,v 1.11 2020/07/05 19:40:27 riastradh Exp $");
 #endif /* no lint */
 
 #include 
@@ -229,6 +229,75 @@ struct fieldinfo id_aa64isar0_fieldinfo[
 		}
 	},
 	{
+		.bitpos = 20, .bitwidth = 4, .name = "Atomic",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "No Atomic",
+			[1] = "LDADD/LDCLR/LDEOR/LDSET/LDSMAX/LDSMIN"
+			"/LDUMAX/LDUMIN/CAS/CASP/SWP",
+		}
+	},
+	{
+		.bitpos = 28, .bitwidth = 4, .name = "RDM",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "No RDMA",
+			[1] = "SQRDMLAH/SQRDMLSH",
+		}
+	},
+	{
+		.bitpos = 32, .bitwidth = 4, .name = "SHA3",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "No SHA3",
+			[1] = "EOR3/RAX1/XAR/BCAX",
+		}
+	},
+	{
+		.bitpos = 36, .bitwidth = 4, .name = "SM3",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "No SM3",
+			[1] = "SM3SS1/SM3TT1A/SM3TT1B/SM3TT2A/SM3TT2B"
+			"/SM3PARTW1/SM3PARTW2",
+		}
+	},
+	{
+		.bitpos = 40, .bitwidth = 4, .name = "SM4",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "No SM4",
+			[1] = "SM4E/SM4EKEY",
+		}
+	},
+	{
+		.bitpos = 44, .bitwidth = 4, .name = "DP",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "No Dot Product",
+			[1] = "UDOT/SDOT",
+		}
+	},
+	{
+		.bitpos = 48, .bitwidth = 4, .name = "FHM",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "No FHM",
+			[1] = "FMLAL/FMLSL",
+		}
+	},
+	{
+		.bitpos = 52, .bitwidth = 4, .name = "TS",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "No TS",
+			[1] = "CFINV/RMIF/SETF16/SETF8",
+			[2] = "CFINV/RMIF/SETF16/SETF8/AXFLAG/XAFLAG",
+		}
+	},
+	{
+		.bitpos = 56, .bitwidth = 4, .name = "TLBI",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "No outer shareable and TLB range maintenance"
+			" instructions",
+			[1] = "Outer shareable TLB maintenance instructions",
+			[2] = "Outer shareable and TLB range maintenance"
+			" instructions",
+		}
+	},
+	{
 		.bitpos = 60, .bitwidth = 4, .name = "RNDR",
 		.info = (const char *[16]) { /* 16=4bit */
 			[0] = "No RNDR/RNDRRS",

CVS commit: src/usr.sbin/cpuctl/arch

2020-07-01 Thread Ryo Shimizu

Module Name:src
Committed By:   ryo
Date:   Wed Jul  1 08:03:10 UTC 2020

Modified Files:
src/usr.sbin/cpuctl/arch: aarch64.c

Log Message:
show clidr_el1 and ctr_el0.


To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/usr.sbin/cpuctl/arch/aarch64.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/aarch64.c
diff -u src/usr.sbin/cpuctl/arch/aarch64.c:1.9 src/usr.sbin/cpuctl/arch/aarch64.c:1.10
--- src/usr.sbin/cpuctl/arch/aarch64.c:1.9	Sun May 10 21:42:05 2020
+++ src/usr.sbin/cpuctl/arch/aarch64.c	Wed Jul  1 08:03:10 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: aarch64.c,v 1.9 2020/05/10 21:42:05 riastradh Exp $	*/
+/*	$NetBSD: aarch64.c,v 1.10 2020/07/01 08:03:10 ryo Exp $	*/
 
 /*
  * Copyright (c) 2018 Ryo Shimizu 
@@ -29,7 +29,7 @@
 #include 
 
 #ifndef lint
-__RCSID("$NetBSD: aarch64.c,v 1.9 2020/05/10 21:42:05 riastradh Exp $");
+__RCSID("$NetBSD: aarch64.c,v 1.10 2020/07/01 08:03:10 ryo Exp $");
 #endif /* no lint */
 
 #include 
@@ -60,8 +60,11 @@ struct impltab {
 };
 
 struct fieldinfo {
-	int bitpos;
-	int bitwidth;
+	unsigned int flags;
+#define FIELDINFO_FLAGS_DEC	0x0001
+#define FIELDINFO_FLAGS_4LOG2	0x0002
+	unsigned char bitpos;
+	unsigned char bitwidth;
 	const char *name;
 	const char * const *info;
 };
@@ -549,13 +552,108 @@ struct fieldinfo mvfr2_fieldinfo[] = {
 	{ .bitwidth = 0 }	/* end of table */
 };
 
+/* CLIDR_EL1 - Cache Level ID Register */
+const char * const clidr_cachetype[8] = { /* 8=3bit */
+	[0] = "None",
+	[1] = "Instruction cache",
+	[2] = "Data cache",
+	[3] = "Instruction and Data cache",
+	[4] = "Unified cache"
+};
+
+struct fieldinfo clidr_fieldinfo[] = {
+	{
+		.bitpos = 0, .bitwidth = 3, .name = "L1",
+		.info = clidr_cachetype
+	},
+	{
+		.bitpos = 3, .bitwidth = 3, .name = "L2",
+		.info = clidr_cachetype
+	},
+	{
+		.bitpos = 6, .bitwidth = 3, .name = "L3",
+		.info = clidr_cachetype
+	},
+	{
+		.bitpos = 9, .bitwidth = 3, .name = "L4",
+		.info = clidr_cachetype
+	},
+	{
+		.bitpos = 12, .bitwidth = 3, .name = "L5",
+		.info = clidr_cachetype
+	},
+	{
+		.bitpos = 15, .bitwidth = 3, .name = "L6",
+		.info = clidr_cachetype
+	},
+	{
+		.bitpos = 18, .bitwidth = 3, .name = "L7",
+		.info = clidr_cachetype
+	},
+	{
+		.bitpos = 21, .bitwidth = 3, .name = "LoUU",
+		.flags = FIELDINFO_FLAGS_DEC
+	},
+	{
+		.bitpos = 24, .bitwidth = 3, .name = "LoC",
+		.flags = FIELDINFO_FLAGS_DEC
+	},
+	{
+		.bitpos = 27, .bitwidth = 3, .name = "LoUIS",
+		.flags = FIELDINFO_FLAGS_DEC
+	},
+	{
+		.bitpos = 30, .bitwidth = 3, .name = "ICB",
+		.flags = FIELDINFO_FLAGS_DEC
+	},
+	{ .bitwidth = 0 }	/* end of table */
+};
+
+struct fieldinfo ctr_fieldinfo[] = {
+	{
+		.bitpos = 0, .bitwidth = 4, .name = "IminLine",
+		.flags = FIELDINFO_FLAGS_DEC | FIELDINFO_FLAGS_4LOG2
+	},
+	{
+		.bitpos = 16, .bitwidth = 4, .name = "DminLine",
+		.flags = FIELDINFO_FLAGS_DEC | FIELDINFO_FLAGS_4LOG2
+	},
+	{
+		.bitpos = 14, .bitwidth = 2, .name = "L1 Icache policy",
+		.info = (const char *[4]) { /* 4=2bit */
+			[0] = "VMID aware PIPT (VPIPT)",
+			[1] = "ASID-tagged VIVT (AIVIVT)",
+			[2] = "VIPT",
+			[3] = "PIPT"
+		},
+	},
+	{
+		.bitpos = 20, .bitwidth = 4, .name = "ERG",
+		.flags = FIELDINFO_FLAGS_DEC | FIELDINFO_FLAGS_4LOG2
+	},
+	{
+		.bitpos = 24, .bitwidth = 4, .name = "CWG",
+		.flags = FIELDINFO_FLAGS_DEC | FIELDINFO_FLAGS_4LOG2
+	},
+	{
+		.bitpos = 28, .bitwidth = 1, .name = "DIC",
+		.flags = FIELDINFO_FLAGS_DEC
+	},
+	{
+		.bitpos = 29, .bitwidth = 1, .name = "IDC",
+		.flags = FIELDINFO_FLAGS_DEC
+	},
+	{ .bitwidth = 0 }	/* end of table */
+};
+
+
 static void
 print_fieldinfo(const char *cpuname, const char *setname,
 struct fieldinfo *fieldinfo, uint64_t data)
 {
 	uint64_t v;
 	const char *info;
-	int i;
+	int i, flags;
 
 #define WIDTHMASK(w)	(0xULL >> (64 - (w)))
 
@@ -563,13 +661,24 @@ print_fieldinfo(const char *cpuname, con
 		v = (data >> fieldinfo[i].bitpos) &
 		WIDTHMASK(fieldinfo[i].bitwidth);
 
-		info = fieldinfo[i].info[v];
-		if (info == NULL)
-			printf("%s: %s: %s: 0x%"PRIx64"\n",
-			cpuname, setname, fieldinfo[i].name, v);
-		else
-			printf("%s: %s: %s: %s\n",
-			cpuname, setname, fieldinfo[i].name, info);
+		flags = fieldinfo[i].flags;
+		info = NULL;
+		if (fieldinfo[i].info != NULL)
+			info = fieldinfo[i].info[v];
+
+		printf("%s: %s: %s: ",
+		cpuname, setname, fieldinfo[i].name);
+
+		if (info == NULL) {
+			if (flags & FIELDINFO_FLAGS_4LOG2)
+v = 4 * (1 << v);
+			if (flags & FIELDINFO_FLAGS_DEC)
+printf("%"PRIu64"\n", v);
+			else
+printf("0x%"PRIx64"\n", v);
+		} else {
+			printf("%s\n", info);
+		}
 	}
 }
 
@@ -671,6 +780,7 @@ identifycpu(int fd, const char *cpuname)
 
 	snprintf(path, sizeof path, "machdep.%s.cpu_id", cpuname);
 	len = sizeof(sysctlbuf);
+	memset(sysctlbuf, 0, len);
 	if (sysctlbyname(path, id, , 0, 0) == -1)
 		err(1, "couldn't get %s", path);

CVS commit: src/usr.sbin/cpuctl/arch

2020-06-01 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Mon Jun  1 08:33:40 UTC 2020

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
 Add 0xa5 and 0xa6 for Comet Lake.


To generate a diff of this commit:
cvs rdiff -u -r1.112 -r1.113 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.112 src/usr.sbin/cpuctl/arch/i386.c:1.113
--- src/usr.sbin/cpuctl/arch/i386.c:1.112	Tue Apr 21 02:56:37 2020
+++ src/usr.sbin/cpuctl/arch/i386.c	Mon Jun  1 08:33:40 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.112 2020/04/21 02:56:37 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.113 2020/06/01 08:33:40 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.112 2020/04/21 02:56:37 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.113 2020/06/01 08:33:40 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -353,6 +353,8 @@ const struct cpu_cpuid_nameclass i386_cp
 [0x86] = "Atom (Tremont)",
 [0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)",
 [0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)",
+[0xa5] = "10th gen Core (Comet Lake)",
+[0xa6] = "10th gen Core (Comet Lake)",
 			},
 			"Pentium Pro, II or III",	/* Default */
 			NULL,

CVS commit: src/usr.sbin/cpuctl/arch

2020-05-10 Thread Taylor R Campbell

Module Name:src
Committed By:   riastradh
Date:   Sun May 10 21:42:06 UTC 2020

Modified Files:
src/usr.sbin/cpuctl/arch: aarch64.c

Log Message:
Teach cpuctl(8) about ARMv8.5-RNG RNDR/RNDRRS support.


To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/usr.sbin/cpuctl/arch/aarch64.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/aarch64.c
diff -u src/usr.sbin/cpuctl/arch/aarch64.c:1.8 src/usr.sbin/cpuctl/arch/aarch64.c:1.9
--- src/usr.sbin/cpuctl/arch/aarch64.c:1.8	Tue Jan 28 17:36:42 2020
+++ src/usr.sbin/cpuctl/arch/aarch64.c	Sun May 10 21:42:05 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: aarch64.c,v 1.8 2020/01/28 17:36:42 maxv Exp $	*/
+/*	$NetBSD: aarch64.c,v 1.9 2020/05/10 21:42:05 riastradh Exp $	*/
 
 /*
  * Copyright (c) 2018 Ryo Shimizu 
@@ -29,7 +29,7 @@
 #include 
 
 #ifndef lint
-__RCSID("$NetBSD: aarch64.c,v 1.8 2020/01/28 17:36:42 maxv Exp $");
+__RCSID("$NetBSD: aarch64.c,v 1.9 2020/05/10 21:42:05 riastradh Exp $");
 #endif /* no lint */
 
 #include 
@@ -225,6 +225,13 @@ struct fieldinfo id_aa64isar0_fieldinfo[
 			"/CRC32CB/CRC32CH/CRC32CW/CRC32CX"
 		}
 	},
+	{
+		.bitpos = 60, .bitwidth = 4, .name = "RNDR",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "No RNDR/RNDRRS",
+			[1] = "RNDR/RNDRRS",
+		},
+	},
 	{ .bitwidth = 0 }	/* end of table */
 };

CVS commit: src/usr.sbin/cpuctl/arch

2020-04-15 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Thu Apr 16 01:52:34 UTC 2020

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
No functional change:
 - Rename ci_cpuid_level to ci_max_cpuid and ci_cpuid_extlevel to
   ci_max_ext_cpuid to match x86/include/cpu.h though cpuctl/arch/i386.c added
   them first.
 - Sort some entries.
 - Add comment.


To generate a diff of this commit:
cvs rdiff -u -r1.110 -r1.111 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.110 src/usr.sbin/cpuctl/arch/i386.c:1.111
--- src/usr.sbin/cpuctl/arch/i386.c:1.110	Mon Apr  6 09:48:44 2020
+++ src/usr.sbin/cpuctl/arch/i386.c	Thu Apr 16 01:52:34 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.110 2020/04/06 09:48:44 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.111 2020/04/16 01:52:34 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.110 2020/04/06 09:48:44 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.111 2020/04/16 01:52:34 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -93,9 +93,10 @@ __RCSID("$NetBSD: i386.c,v 1.110 2020/04
 struct cpu_info {
 	const char	*ci_dev;
 	int32_t		ci_cpu_type;	 /* for cpu's without cpuid */
-	int32_t		ci_cpuid_level;	 /* highest cpuid supported */
-	uint32_t	ci_cpuid_extlevel; /* highest cpuid extended func lv */
 	uint32_t	ci_signature;	 /* X86 cpuid type */
+	uint32_t	ci_vendor[4];	 /* vendor string */
+	int32_t		ci_max_cpuid;	 /* highest cpuid supported */
+	uint32_t	ci_max_ext_cpuid; /* highest cpuid extended func lv */
 	uint32_t	ci_family;	 /* from ci_signature */
 	uint32_t	ci_model;	 /* from ci_signature */
 	uint32_t	ci_feat_val[10]; /* X86 CPUID feature bits
@@ -112,13 +113,12 @@ struct cpu_info {
 	  */
 	uint32_t	ci_cpu_class;	 /* CPU class */
 	uint32_t	ci_brand_id;	 /* Intel brand id */
-	uint32_t	ci_vendor[4];	 /* vendor string */
 	uint32_t	ci_cpu_serial[3]; /* PIII serial number */
 	uint64_t	ci_tsc_freq;	 /* cpu cycles/second */
 	uint8_t		ci_packageid;
 	uint8_t		ci_coreid;
 	uint8_t		ci_smtid;
-	uint32_t	ci_initapicid;
+	uint32_t	ci_initapicid;	/* our initial APIC ID */
 
 	uint32_t	ci_cur_xsave;
 	uint32_t	ci_max_xsave;
@@ -1065,7 +1065,7 @@ intel_cpu_cacheinfo(struct cpu_info *ci)
 	if (ci->ci_cpu_type >= 0)
 		return;
 
-	if (ci->ci_cpuid_level < 2)
+	if (ci->ci_max_cpuid < 2)
 		return;
 
 	/*
@@ -1103,13 +1103,13 @@ intel_cpu_cacheinfo(struct cpu_info *ci)
 		x86_cpuid(2, descs);
 	}
 
-	if (ci->ci_cpuid_level < 4)
+	if (ci->ci_max_cpuid < 4)
 		return;
 
 	/* Parse the cache info from `cpuid leaf 4', if we have it. */
 	cpu_dcp_cacheinfo(ci, 4);
 
-	if (ci->ci_cpuid_level < 0x18)
+	if (ci->ci_max_cpuid < 0x18)
 		return;
 	/* Parse the TLB info from `cpuid leaf 18H', if we have it. */
 	x86_cpuid(0x18, descs);
@@ -1583,7 +1583,7 @@ cpu_probe_base_features(struct cpu_info 
 	ci->ci_cpu_type = x86_identify();
 	if (ci->ci_cpu_type >= 0) {
 		/* Old pre-cpuid instruction cpu */
-		ci->ci_cpuid_level = -1;
+		ci->ci_max_cpuid = -1;
 		return;
 	}
 
@@ -1598,7 +1598,7 @@ cpu_probe_base_features(struct cpu_info 
 	 * - Save vendor string.
 	 */
 	x86_cpuid(0, descs);
-	ci->ci_cpuid_level = descs[0];
+	ci->ci_max_cpuid = descs[0];
 	/* Save vendor string */
 	ci->ci_vendor[0] = descs[1];
 	ci->ci_vendor[2] = descs[2];
@@ -1611,17 +1611,17 @@ cpu_probe_base_features(struct cpu_info 
 	 */
 	x86_cpuid(0x8000, descs);
 	if (descs[0] >= 0x8000)
-		ci->ci_cpuid_extlevel = descs[0];
+		ci->ci_max_ext_cpuid = descs[0];
 	else {
 		/* Set lower value than 0x8000 */
-		ci->ci_cpuid_extlevel = 0;
+		ci->ci_max_ext_cpuid = 0;
 	}
 
 	/*
 	 * Fn8000_000[2-4]:
 	 * - Save brand string.
 	 */
-	if (ci->ci_cpuid_extlevel >= 0x8004) {
+	if (ci->ci_max_ext_cpuid >= 0x8004) {
 		x86_cpuid(0x8002, brand);
 		x86_cpuid(0x8003, brand + 4);
 		x86_cpuid(0x8004, brand + 8);
@@ -1631,7 +1631,7 @@ cpu_probe_base_features(struct cpu_info 
 		memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i);
 	}
 
-	if (ci->ci_cpuid_level < 1)
+	if (ci->ci_max_cpuid < 1)
 		return;
 
 	/*
@@ -1656,7 +1656,7 @@ cpu_probe_base_features(struct cpu_info 
 	ci->ci_feat_val[1] = descs[2];
 	ci->ci_feat_val[0] = descs[3];
 
-	if (ci->ci_cpuid_level < 3)
+	if (ci->ci_max_cpuid < 3)
 		return;
 
 	/*
@@ -1670,7 +1670,7 @@ cpu_probe_base_features(struct cpu_info 
 		ci->ci_cpu_serial[1] = descs[3];
 	}
 
-	if (ci->ci_cpuid_level < 0x7)
+	if (ci->ci_max_cpuid < 0x7)
 		return;
 
 	x86_cpuid(7, descs);
@@ -1678,7 +1678,7 @@ cpu_probe_base_features(struct cpu_info 
 	ci->ci_feat_val[6] = descs[2];
 	ci->ci_feat_val[7] = descs[3];
 
-	if (ci->ci_cpuid_level < 0xd)
+	if (ci->ci_max_cpuid < 0xd)
 		return;
 
 	/* Get support XCR0 bits */
@@

CVS commit: src/usr.sbin/cpuctl/arch

2020-04-06 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Mon Apr  6 09:48:44 UTC 2020

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
 Print CPUID 0x8007 %edx on both Intel and AMD.


To generate a diff of this commit:
cvs rdiff -u -r1.109 -r1.110 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.109 src/usr.sbin/cpuctl/arch/i386.c:1.110
--- src/usr.sbin/cpuctl/arch/i386.c:1.109	Mon Apr  6 09:46:21 2020
+++ src/usr.sbin/cpuctl/arch/i386.c	Mon Apr  6 09:48:44 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.109 2020/04/06 09:46:21 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.110 2020/04/06 09:48:44 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.109 2020/04/06 09:46:21 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.110 2020/04/06 09:48:44 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -2286,10 +2286,11 @@ identifycpu(int fd, const char *cpuname)
 		cpuname, descs[0]);
 	}
 
-	if (cpu_vendor == CPUVENDOR_AMD) {
+	if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD))
 		if (ci->ci_cpuid_extlevel >= 0x8007)
 			powernow_probe(ci);
 
+	if (cpu_vendor == CPUVENDOR_AMD) {
 		if (ci->ci_cpuid_extlevel >= 0x8008) {
 			x86_cpuid(0x8008, descs);
 			print_bits(cpuname, "AMD Extended features",
@@ -2566,8 +2567,7 @@ powernow_probe(struct cpu_info *ci)
 	x86_cpuid(0x8007, regs);
 
 	snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]);
-	aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n",
-	buf);
+	aprint_normal_dev(ci->ci_dev, "Power Management features: %s\n", buf);
 }
 
 bool

CVS commit: src/usr.sbin/cpuctl/arch

2020-04-06 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Mon Apr  6 09:46:21 UTC 2020

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
 Remove ci_max_ext_cpuid because it's the same as ci_cpuid_extlevel.


To generate a diff of this commit:
cvs rdiff -u -r1.108 -r1.109 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.108 src/usr.sbin/cpuctl/arch/i386.c:1.109
--- src/usr.sbin/cpuctl/arch/i386.c:1.108	Sun Nov 17 15:32:00 2019
+++ src/usr.sbin/cpuctl/arch/i386.c	Mon Apr  6 09:46:21 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.108 2019/11/17 15:32:00 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.109 2020/04/06 09:46:21 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.108 2019/11/17 15:32:00 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.109 2020/04/06 09:46:21 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -119,7 +119,6 @@ struct cpu_info {
 	uint8_t		ci_coreid;
 	uint8_t		ci_smtid;
 	uint32_t	ci_initapicid;
-	uint32_t	ci_max_ext_cpuid;
 
 	uint32_t	ci_cur_xsave;
 	uint32_t	ci_max_xsave;
@@ -1944,7 +1943,7 @@ identifycpu_cpuids_amd(struct cpu_info *
 		x86_cpuid(1, descs);
 		lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES);
 
-		if (cpu_family >= 0x10 && ci->ci_max_ext_cpuid >= 0x808) {
+		if (cpu_family >= 0x10 && ci->ci_cpuid_extlevel >= 0x808) {
 			x86_cpuid(0x808, descs);
 			core_max = (descs[2] & 0xff) + 1;
 			n = (descs[2] >> 12) & 0x0f;
@@ -2288,21 +2287,16 @@ identifycpu(int fd, const char *cpuname)
 	}
 
 	if (cpu_vendor == CPUVENDOR_AMD) {
-		x86_cpuid(0x8000, descs);
-		if (descs[0] >= 0x8000)
-			ci->ci_max_ext_cpuid = descs[0];
-		else
-			ci->ci_max_ext_cpuid = 0;
-		if (ci->ci_max_ext_cpuid >= 0x8007)
+		if (ci->ci_cpuid_extlevel >= 0x8007)
 			powernow_probe(ci);
 
-		if (ci->ci_max_ext_cpuid >= 0x8008) {
+		if (ci->ci_cpuid_extlevel >= 0x8008) {
 			x86_cpuid(0x8008, descs);
 			print_bits(cpuname, "AMD Extended features",
 			CPUID_CAPEX_FLAGS, descs[1]);
 		}
 
-		if ((ci->ci_max_ext_cpuid >= 0x800a)
+		if ((ci->ci_cpuid_extlevel >= 0x800a)
 		&& (ci->ci_feat_val[3] & CPUID_SVM) != 0) {
 			x86_cpuid(0x800a, descs);
 			aprint_verbose("%s: SVM Rev. %d\n", cpuname,
@@ -2312,7 +2306,7 @@ identifycpu(int fd, const char *cpuname)
 			print_bits(cpuname, "SVM features",
 			CPUID_AMD_SVM_FLAGS, descs[3]);
 		}
-		if (ci->ci_max_ext_cpuid >= 0x801f) {
+		if (ci->ci_cpuid_extlevel >= 0x801f) {
 			x86_cpuid(0x801f, descs);
 			print_bits(cpuname, "Encrypted Memory features",
 			CPUID_AMD_ENCMEM_FLAGS, descs[0]);

CVS commit: src/usr.sbin/cpuctl/arch

2020-01-28 Thread Maxime Villard

Module Name:src
Committed By:   maxv
Date:   Tue Jan 28 17:36:42 UTC 2020

Modified Files:
src/usr.sbin/cpuctl/arch: aarch64.c

Log Message:
More identification.


To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/usr.sbin/cpuctl/arch/aarch64.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/aarch64.c
diff -u src/usr.sbin/cpuctl/arch/aarch64.c:1.7 src/usr.sbin/cpuctl/arch/aarch64.c:1.8
--- src/usr.sbin/cpuctl/arch/aarch64.c:1.7	Thu May  9 07:38:44 2019
+++ src/usr.sbin/cpuctl/arch/aarch64.c	Tue Jan 28 17:36:42 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: aarch64.c,v 1.7 2019/05/09 07:38:44 mrg Exp $	*/
+/*	$NetBSD: aarch64.c,v 1.8 2020/01/28 17:36:42 maxv Exp $	*/
 
 /*
  * Copyright (c) 2018 Ryo Shimizu 
@@ -29,7 +29,7 @@
 #include 
 
 #ifndef lint
-__RCSID("$NetBSD: aarch64.c,v 1.7 2019/05/09 07:38:44 mrg Exp $");
+__RCSID("$NetBSD: aarch64.c,v 1.8 2020/01/28 17:36:42 maxv Exp $");
 #endif /* no lint */
 
 #include 
@@ -158,6 +158,41 @@ struct fieldinfo id_aa64pfr0_fieldinfo[]
 	{ .bitwidth = 0 }	/* end of table */
 };
 
+/* ID_AA64PFR1_EL1 - AArch64 Processor Feature Register 1 */
+struct fieldinfo id_aa64pfr1_fieldinfo[] = {
+	{
+		.bitpos = 0, .bitwidth = 4, .name = "BT",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "Branch Target Identification not implemented",
+			[1] = "Branch Target Identification implemented",
+		}
+	},
+	{
+		.bitpos = 4, .bitwidth = 4, .name = "SSBS",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "Speculative Store Bypassing control not implemented",
+			[1] = "Speculative Store Bypassing control implemented",
+			[2] = "Speculative Store Bypassing control implemented, plus MSR/MRS"
+		}
+	},
+	{
+		.bitpos = 8, .bitwidth = 4, .name = "MTE",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "Tagged Memory Extension not implemented",
+			[1] = "Tagged Memory Extension implemented, EL0 only",
+			[2] = "Tagged Memory Extension implemented"
+		}
+	},
+	{
+		.bitpos = 12, .bitwidth = 4, .name = "RAS_frac",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "Regular RAS",
+			[1] = "RAS plus registers",
+		}
+	},
+	{ .bitwidth = 0 }	/* end of table */
+};
+
 /* ID_AA64ISAR0_EL1 - AArch64 Instruction Set Attribute Register 0 */
 struct fieldinfo id_aa64isar0_fieldinfo[] = {
 	{
@@ -258,6 +293,70 @@ struct fieldinfo id_aa64mmfr0_fieldinfo[
 	{ .bitwidth = 0 }	/* end of table */
 };
 
+/* ID_AA64MMFR1_EL1 - AArch64 Memory Model Feature Register 1 */
+struct fieldinfo id_aa64mmfr1_fieldinfo[] = {
+	{
+		.bitpos = 0, .bitwidth = 4, .name = "HAFDBS",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "Access and Dirty flags not supported",
+			[1] = "Access flag supported",
+			[2] = "Access and Dirty flags supported",
+		}
+	},
+	{
+		.bitpos = 4, .bitwidth = 4, .name = "VMIDBits",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "8bits",
+			[2] = "16bits"
+		}
+	},
+	{
+		.bitpos = 8, .bitwidth = 4, .name = "VH",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "Virtualization Host Extensions not supported",
+			[1] = "Virtualization Host Extensions supported",
+		}
+	},
+	{
+		.bitpos = 12, .bitwidth = 4, .name = "HPDS",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "Disabling of hierarchical controls not supported",
+			[1] = "Disabling of hierarchical controls supported",
+			[2] = "Disabling of hierarchical controls supported, plus PTD"
+		}
+	},
+	{
+		.bitpos = 16, .bitwidth = 4, .name = "LO",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "LORegions not supported",
+			[1] = "LORegions supported"
+		}
+	},
+	{
+		.bitpos = 20, .bitwidth = 4, .name = "PAN",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "PAN not supported",
+			[1] = "PAN supported",
+			[2] = "PAN supported, and instructions supported"
+		}
+	},
+	{
+		.bitpos = 24, .bitwidth = 4, .name = "SpecSEI",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "SError interrupt not supported",
+			[1] = "SError interrupt supported"
+		}
+	},
+	{
+		.bitpos = 28, .bitwidth = 4, .name = "XNX",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "Distinction between EL0 and EL1 XN control at stage 2 not supported",
+			[1] = "Distinction between EL0 and EL1 XN control at stage 2 supported"
+		}
+	},
+	{ .bitwidth = 0 }	/* end of table */
+};
+
 /* ID_AA64DFR0_EL1 - AArch64 Debug Feature Register 0 */
 struct fieldinfo id_aa64dfr0_fieldinfo[] = {
 	{
@@ -610,8 +709,12 @@ identifycpu(int fd, const char *cpuname)
 	id_aa64isar0_fieldinfo, id->ac_aa64isar0);
 	print_fieldinfo(cpuname, "memory model 0",
 	id_aa64mmfr0_fieldinfo, id->ac_aa64mmfr0);
+	print_fieldinfo(cpuname, "memory model 1",
+	id_aa64mmfr1_fieldinfo, id->ac_aa64mmfr1);
 	print_fieldinfo(cpuname, "processor feature 0",
 	id_aa64pfr0_fieldinfo, id->ac_aa64pfr0);
+	print_fieldinfo(cpuname, "processor feature 1",
+

CVS commit: src/usr.sbin/cpuctl/arch

2019-05-10 Thread Michael van Elst

Module Name:src
Committed By:   mlelstv
Date:   Fri May 10 16:42:57 UTC 2019

Modified Files:
src/usr.sbin/cpuctl/arch: cpuctl_i386.h i386-asm.S i386.c x86_64-asm.S

Log Message:
Get CPU topology data for AMD processors.


To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/usr.sbin/cpuctl/arch/cpuctl_i386.h
cvs rdiff -u -r1.4 -r1.5 src/usr.sbin/cpuctl/arch/i386-asm.S
cvs rdiff -u -r1.95 -r1.96 src/usr.sbin/cpuctl/arch/i386.c
cvs rdiff -u -r1.5 -r1.6 src/usr.sbin/cpuctl/arch/x86_64-asm.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/cpuctl_i386.h
diff -u src/usr.sbin/cpuctl/arch/cpuctl_i386.h:1.2 src/usr.sbin/cpuctl/arch/cpuctl_i386.h:1.3
--- src/usr.sbin/cpuctl/arch/cpuctl_i386.h:1.2	Mon Jan  7 23:20:42 2013
+++ src/usr.sbin/cpuctl/arch/cpuctl_i386.h	Fri May 10 16:42:57 2019
@@ -1,4 +1,4 @@
-/*  $NetBSD: cpuctl_i386.h,v 1.2 2013/01/07 23:20:42 dsl Exp $  */
+/*  $NetBSD: cpuctl_i386.h,v 1.3 2019/05/10 16:42:57 mlelstv Exp $  */
 
 /* Interfaces to code in i386-asm.S */
 
@@ -7,3 +7,4 @@
 void x86_cpuid2(uint32_t, uint32_t, uint32_t *);
 uint32_t x86_identify(void);
 uint32_t x86_xgetbv(void);
+uint64_t rdmsr(u_int);

Index: src/usr.sbin/cpuctl/arch/i386-asm.S
diff -u src/usr.sbin/cpuctl/arch/i386-asm.S:1.4 src/usr.sbin/cpuctl/arch/i386-asm.S:1.5
--- src/usr.sbin/cpuctl/arch/i386-asm.S:1.4	Sun Mar  1 18:02:42 2015
+++ src/usr.sbin/cpuctl/arch/i386-asm.S	Fri May 10 16:42:57 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386-asm.S,v 1.4 2015/03/01 18:02:42 tnn Exp $	*/
+/*	$NetBSD: i386-asm.S,v 1.5 2019/05/10 16:42:57 mlelstv Exp $	*/
 
 /*-
  * Copyright (c) 1998, 2000, 2004, 2006, 2007 The NetBSD Foundation, Inc.
@@ -30,6 +30,9 @@
 #include 
 #include 
 
+/* From sys/arch/x86/include/cpufunc.h */
+#define	OPTERON_MSR_PASSCODE	0x9c5a203aU
+
 	.text
 
 ENTRY(x86_cpuid2)
@@ -160,3 +163,12 @@ trycyrix486:
 is486dlc:
 	movl	$CPU_486DLC,%eax
 	ret
+
+ENTRY(rdmsr_locked)
+	movl	4(%esp), %ecx
+	pushl	%edi
+	movl	$OPTERON_MSR_PASSCODE, %edi
+	rdmsr
+	popl	%edi
+	ret
+END(rdmsr_locked)

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.95 src/usr.sbin/cpuctl/arch/i386.c:1.96
--- src/usr.sbin/cpuctl/arch/i386.c:1.95	Sun Mar 24 04:43:54 2019
+++ src/usr.sbin/cpuctl/arch/i386.c	Fri May 10 16:42:57 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.95 2019/03/24 04:43:54 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.96 2019/05/10 16:42:57 mlelstv Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.95 2019/03/24 04:43:54 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.96 2019/05/10 16:42:57 mlelstv Exp $");
 #endif /* not lint */
 
 #include 
@@ -119,6 +119,7 @@ struct cpu_info {
 	uint8_t		ci_coreid;
 	uint8_t		ci_smtid;
 	uint32_t	ci_initapicid;
+	uint32_t	ci_max_ext_cpuid;
 
 	uint32_t	ci_cur_xsave;
 	uint32_t	ci_max_xsave;
@@ -1925,6 +1926,76 @@ identifycpu_cpuids_intel(struct cpu_info
 }
 
 static void
+identifycpu_cpuids_amd(struct cpu_info *ci)
+{
+	const char *cpuname = ci->ci_dev;
+	u_int lp_max, core_max;
+	int n, cpu_family, apic_id, smt_bits, core_bits = 0;
+	uint32_t descs[4];
+
+	apic_id = ci->ci_initapicid;
+	cpu_family = CPUID_TO_FAMILY(ci->ci_signature);
+
+	if (cpu_family < 0xf)
+		return;
+
+	if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) {
+		x86_cpuid(1, descs);
+		lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES);
+
+		if (cpu_family >= 0x10 && ci->ci_max_ext_cpuid >= 0x808) {
+			x86_cpuid(0x808, descs);
+			core_max = (descs[2] & 0xff) + 1;
+			n = (descs[2] >> 12) & 0x0f;
+			if (n != 0)
+core_bits = n;
+		}
+	} else {
+		lp_max = 1;
+	}
+	core_max = lp_max;
+
+	smt_bits = ilog2((lp_max / core_max) - 1) + 1;
+	if (core_bits == 0)
+		core_bits = ilog2(core_max - 1) + 1;
+
+	if (cpu_family < 0x11) {
+		const uint64_t reg = rdmsr(MSR_NB_CFG);
+		if ((reg & NB_CFG_INITAPICCPUIDLO) == 0) {
+			const u_int node_id = apic_id & __BITS(0, 2);
+			apic_id = (cpu_family == 0xf) ?
+(apic_id >> core_bits) | (node_id << core_bits) :
+(apic_id >> 5) | (node_id << 2);
+		}
+	}
+
+	if (cpu_family == 0x17) {
+		x86_cpuid(0x801e, descs);
+		const u_int threads = ((descs[1] >> 8) & 0xff) + 1;
+		smt_bits = ilog2(threads);
+		core_bits -= smt_bits;
+	}
+
+	if (smt_bits + core_bits) {
+		if (smt_bits + core_bits < 32)
+			ci->ci_packageid = 0;
+	}
+	if (core_bits) {
+		u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1);
+		ci->ci_coreid = __SHIFTOUT(apic_id, core_mask);
+	}
+	if (smt_bits) {
+		u_int smt_mask = __BITS(0, smt_bits - 1);
+		ci->ci_smtid = __SHIFTOUT(apic_id, smt_mask);
+	}
+
+	aprint_verbose("%s: Cluster/Package ID %u\n", cpuname,
+	ci->ci_packageid);
+	aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid);
+	aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid);
+}
+
+static

CVS commit: src/usr.sbin/cpuctl/arch

2019-03-23 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Sun Mar 24 04:43:54 UTC 2019

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
 Add HAXM.


To generate a diff of this commit:
cvs rdiff -u -r1.94 -r1.95 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.94 src/usr.sbin/cpuctl/arch/i386.c:1.95
--- src/usr.sbin/cpuctl/arch/i386.c:1.94	Fri Mar 22 04:39:02 2019
+++ src/usr.sbin/cpuctl/arch/i386.c	Sun Mar 24 04:43:54 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.94 2019/03/22 04:39:02 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.95 2019/03/24 04:43:54 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.94 2019/03/22 04:39:02 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.95 2019/03/24 04:43:54 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -1716,6 +1716,7 @@ cpu_probe_hv_features(struct cpu_info *c
 		/*
 		 * HV vendor	ID string
 		 * +--
+		 * HAXM		"HAXMHAXMHAXM"
 		 * KVM		"KVMKVMKVM"
 		 * Microsoft	"Microsoft Hv"
 		 * QEMU(TCG)	"TCGTCGTCGTCG"
@@ -1723,7 +1724,9 @@ cpu_probe_hv_features(struct cpu_info *c
 		 * Xen		"XenVMMXenVMM"
 		 * NetBSD	"___ NVMM ___"
 		 */
-		if (strncmp(hv_sig, "KVMKVMKVM", 9) == 0)
+		if (strncmp(hv_sig, "HAXMHAXMHAXM", 12) == 0)
+			hv_name = "HAXM";
+		else if (strncmp(hv_sig, "KVMKVMKVM", 9) == 0)
 			hv_name = "KVM";
 		else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0)
 			hv_name = "Hyper-V";

CVS commit: src/usr.sbin/cpuctl/arch

2019-03-21 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Fri Mar 22 04:39:03 UTC 2019

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
 s/TGC/TCG/. Not Tokyo Game Show but Tiny Code Generator.


To generate a diff of this commit:
cvs rdiff -u -r1.93 -r1.94 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.93 src/usr.sbin/cpuctl/arch/i386.c:1.94
--- src/usr.sbin/cpuctl/arch/i386.c:1.93	Fri Mar 22 02:33:08 2019
+++ src/usr.sbin/cpuctl/arch/i386.c	Fri Mar 22 04:39:02 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.93 2019/03/22 02:33:08 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.94 2019/03/22 04:39:02 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.93 2019/03/22 02:33:08 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.94 2019/03/22 04:39:02 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -1718,7 +1718,7 @@ cpu_probe_hv_features(struct cpu_info *c
 		 * +--
 		 * KVM		"KVMKVMKVM"
 		 * Microsoft	"Microsoft Hv"
-		 * QEMU(TGC)	"TCGTCGTCGTCG"
+		 * QEMU(TCG)	"TCGTCGTCGTCG"
 		 * VMware	"VMwareVMware"
 		 * Xen		"XenVMMXenVMM"
 		 * NetBSD	"___ NVMM ___"
@@ -1728,7 +1728,7 @@ cpu_probe_hv_features(struct cpu_info *c
 		else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0)
 			hv_name = "Hyper-V";
 		else if (strncmp(hv_sig, "TCGTCGTCGTCG", 12) == 0)
-			hv_name = "QEMU(TGC)";
+			hv_name = "QEMU(TCG)";
 		else if (strncmp(hv_sig, "VMwareVMware", 12) == 0)
 			hv_name = "VMware";
 		else if (strncmp(hv_sig, "XenVMMXenVMM", 12) == 0)

CVS commit: src/usr.sbin/cpuctl/arch

2019-03-21 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Fri Mar 22 02:33:08 UTC 2019

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
- Dump CPUID leaf 0x4000 if available (for -v option).
- Regard "TCGTCGTCGTCG" as QEMU(TGC).


To generate a diff of this commit:
cvs rdiff -u -r1.92 -r1.93 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.92 src/usr.sbin/cpuctl/arch/i386.c:1.93
--- src/usr.sbin/cpuctl/arch/i386.c:1.92	Tue Feb  5 08:07:59 2019
+++ src/usr.sbin/cpuctl/arch/i386.c	Fri Mar 22 02:33:08 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.92 2019/02/05 08:07:59 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.93 2019/03/22 02:33:08 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.92 2019/02/05 08:07:59 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.93 2019/03/22 02:33:08 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -1718,6 +1718,7 @@ cpu_probe_hv_features(struct cpu_info *c
 		 * +--
 		 * KVM		"KVMKVMKVM"
 		 * Microsoft	"Microsoft Hv"
+		 * QEMU(TGC)	"TCGTCGTCGTCG"
 		 * VMware	"VMwareVMware"
 		 * Xen		"XenVMMXenVMM"
 		 * NetBSD	"___ NVMM ___"
@@ -1726,6 +1727,8 @@ cpu_probe_hv_features(struct cpu_info *c
 			hv_name = "KVM";
 		else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0)
 			hv_name = "Hyper-V";
+		else if (strncmp(hv_sig, "TCGTCGTCGTCG", 12) == 0)
+			hv_name = "QEMU(TGC)";
 		else if (strncmp(hv_sig, "VMwareVMware", 12) == 0)
 			hv_name = "VMware";
 		else if (strncmp(hv_sig, "XenVMMXenVMM", 12) == 0)
@@ -1791,6 +1794,25 @@ print_bits(const char *cpuname, const ch
 }
 
 static void
+dump_descs(uint32_t leafstart, uint32_t leafend, const char *cpuname,
+const char *blockname)
+{
+	uint32_t descs[4];
+	uint32_t leaf;
+
+	aprint_verbose("%s: highest %s info %08x\n", cpuname, blockname,
+	leafend);
+
+	if (verbose) {
+		for (leaf = leafstart; leaf <= leafend; leaf++) {
+			x86_cpuid(leaf, descs);
+			printf("%s: %08x: %08x %08x %08x %08x\n", cpuname,
+			leaf, descs[0], descs[1], descs[2], descs[3]);
+		}
+	}
+}
+
+static void
 identifycpu_cpuids_intel_0x04(struct cpu_info *ci)
 {
 	u_int lp_max = 1;	/* logical processors per package */
@@ -1933,29 +1955,12 @@ identifycpu(int fd, const char *cpuname)
 
 	ci = 
 	cpu_probe_base_features(ci, cpuname);
-	aprint_verbose("%s: highest basic info %08x\n", cpuname,
-	ci->ci_cpuid_level);
-	if (verbose) {
-		int bf;
-		
-		for (bf = 0; bf <= ci->ci_cpuid_level; bf++) {
-			x86_cpuid(bf, descs);
-			printf("%s: %08x: %08x %08x %08x %08x\n", cpuname,
-			bf, descs[0], descs[1], descs[2], descs[3]);
-		}
-	}
-	if (ci->ci_cpuid_extlevel >=  0x8000)
-		aprint_verbose("%s: highest extended info %08x\n", cpuname,
-		ci->ci_cpuid_extlevel);
-	if (verbose) {
-		unsigned int ef;
-
-		for (ef = 0x8000; ef <= ci->ci_cpuid_extlevel; ef++) {
-			x86_cpuid(ef, descs);
-			printf("%s: %08x: %08x %08x %08x %08x\n", cpuname,
-			ef, descs[0], descs[1], descs[2], descs[3]);
-		}
+	dump_descs(0x, ci->ci_cpuid_level, cpuname, "basic");
+	if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) {
+		x86_cpuid(0x4000, descs);
+		dump_descs(0x4000, descs[0], cpuname, "hypervisor");
 	}
+	dump_descs(0x8000, ci->ci_cpuid_extlevel, cpuname, "extended");
 
 	cpu_probe_hv_features(ci, cpuname);
 	cpu_probe_features(ci);

CVS commit: src/usr.sbin/cpuctl/arch

2019-02-05 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Tue Feb  5 08:07:59 UTC 2019

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
 Add Ice Lake and Tremont from the latest Intel SDM.


To generate a diff of this commit:
cvs rdiff -u -r1.91 -r1.92 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.91 src/usr.sbin/cpuctl/arch/i386.c:1.92
--- src/usr.sbin/cpuctl/arch/i386.c:1.91	Sun Jan  6 16:13:51 2019
+++ src/usr.sbin/cpuctl/arch/i386.c	Tue Feb  5 08:07:59 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.91 2019/01/06 16:13:51 maxv Exp $	*/
+/*	$NetBSD: i386.c,v 1.92 2019/02/05 08:07:59 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.91 2019/01/06 16:13:51 maxv Exp $");
+__RCSID("$NetBSD: i386.c,v 1.92 2019/02/05 08:07:59 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -382,7 +382,9 @@ const struct cpu_cpuid_nameclass i386_cp
 [0x5f] = "Atom (Goldmont, Denverton)",
 [0x66] = "Future Core (Cannon Lake)",
 [0x7a] = "Atom (Goldmont Plus)",
+[0x7e] = "Future Core (Ice Lake)",
 [0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)",
+[0x86] = "Atom (Tremont)",
 [0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake)",
 [0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake)",
 			},

CVS commit: src/usr.sbin/cpuctl/arch

2019-01-22 Thread Nick Hudson

Module Name:src
Committed By:   skrll
Date:   Wed Jan 23 07:41:54 UTC 2019

Modified Files:
src/usr.sbin/cpuctl/arch: aarch64.c

Log Message:
Fix mvfr0.fptrap = 0 description


To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/usr.sbin/cpuctl/arch/aarch64.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/aarch64.c
diff -u src/usr.sbin/cpuctl/arch/aarch64.c:1.5 src/usr.sbin/cpuctl/arch/aarch64.c:1.6
--- src/usr.sbin/cpuctl/arch/aarch64.c:1.5	Thu Dec 20 07:10:23 2018
+++ src/usr.sbin/cpuctl/arch/aarch64.c	Wed Jan 23 07:41:54 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: aarch64.c,v 1.5 2018/12/20 07:10:23 ryo Exp $	*/
+/*	$NetBSD: aarch64.c,v 1.6 2019/01/23 07:41:54 skrll Exp $	*/
 
 /*
  * Copyright (c) 2018 Ryo Shimizu 
@@ -29,7 +29,7 @@
 #include 
 
 #ifndef lint
-__RCSID("$NetBSD: aarch64.c,v 1.5 2018/12/20 07:10:23 ryo Exp $");
+__RCSID("$NetBSD: aarch64.c,v 1.6 2019/01/23 07:41:54 skrll Exp $");
 #endif /* no lint */
 
 #include 
@@ -312,7 +312,7 @@ struct fieldinfo mvfr0_fieldinfo[] = {
 	{
 		.bitpos = 12, .bitwidth = 4, .name = "FPTrap",
 		.info = (const char *[16]) { /* 16=4bit */
-			[0] = "VFPv2 support exception trapping",
+			[0] = "No floating point exception trapping support",
 			[1] = "VFPv2/VFPv3/VFPv4 support exception trapping"
 		}
 	},

CVS commit: src/usr.sbin/cpuctl/arch

2018-12-19 Thread Ryo Shimizu

Module Name:src
Committed By:   ryo
Date:   Thu Dec 20 07:10:23 UTC 2018

Modified Files:
src/usr.sbin/cpuctl/arch: aarch64.c

Log Message:
- show detail of debug feature register (ID_AA64DFR0_EL1)
- print raw value of registers when verbose flag is set.
- keep forward compatibility. read kernel's aarch64_sysctl_cpu_id, but avoid 
unknown system registers.


To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/usr.sbin/cpuctl/arch/aarch64.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/aarch64.c
diff -u src/usr.sbin/cpuctl/arch/aarch64.c:1.4 src/usr.sbin/cpuctl/arch/aarch64.c:1.5
--- src/usr.sbin/cpuctl/arch/aarch64.c:1.4	Mon Nov 26 18:08:41 2018
+++ src/usr.sbin/cpuctl/arch/aarch64.c	Thu Dec 20 07:10:23 2018
@@ -1,4 +1,4 @@
-/*	$NetBSD: aarch64.c,v 1.4 2018/11/26 18:08:41 ryo Exp $	*/
+/*	$NetBSD: aarch64.c,v 1.5 2018/12/20 07:10:23 ryo Exp $	*/
 
 /*
  * Copyright (c) 2018 Ryo Shimizu 
@@ -29,7 +29,7 @@
 #include 
 
 #ifndef lint
-__RCSID("$NetBSD: aarch64.c,v 1.4 2018/11/26 18:08:41 ryo Exp $");
+__RCSID("$NetBSD: aarch64.c,v 1.5 2018/12/20 07:10:23 ryo Exp $");
 #endif /* no lint */
 
 #include 
@@ -257,6 +257,32 @@ struct fieldinfo id_aa64mmfr0_fieldinfo[
 	{ .bitwidth = 0 }	/* end of table */
 };
 
+/* ID_AA64DFR0_EL1 - AArch64 Debug Feature Register 0 */
+struct fieldinfo id_aa64dfr0_fieldinfo[] = {
+	{
+		.bitpos = 0, .bitwidth = 4, .name = "DebugVer",
+		.info = (const char *[16]) { /* 16=4bit */
+			[6] = "v8-A debug architecture"
+		}
+	},
+	{
+		.bitpos = 4, .bitwidth = 4, .name = "TraceVer",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "Trace supported",
+			[1] = "Trace not supported"
+		}
+	},
+	{
+		.bitpos = 8, .bitwidth = 4, .name = "PMUVer",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "No Performance monitor",
+			[1] = "Performance monitor unit v3"
+		}
+	},
+	{ .bitwidth = 0 }	/* end of table */
+};
+
+
 /* MVFR0_EL1 - Media and VFP Feature Register 0 */
 struct fieldinfo mvfr0_fieldinfo[] = {
 	{
@@ -510,34 +536,89 @@ identify_mpidr(const char *cpuname, uint
 
 }
 
+/* AA64DFR0 - Debug feature register 0 */
+static void
+identify_dfr0(const char *cpuname, uint64_t dfr0)
+{
+	const char *setname = "debug feature 0";
+
+	printf("%s: %s: CTX_CMPs: %lu context-aware breakpoints\n",
+	cpuname, setname, __SHIFTOUT(dfr0, ID_AA64DFR0_EL1_CTX_CMPS) + 1);
+	printf("%s: %s: WRPs: %lu watchpoints\n",
+	cpuname, setname, __SHIFTOUT(dfr0, ID_AA64DFR0_EL1_WRPS) + 1);
+	printf("%s: %s: BRPs: %lu breakpoints\n",
+	cpuname, setname, __SHIFTOUT(dfr0, ID_AA64DFR0_EL1_BRPS) + 1);
+	print_fieldinfo(cpuname, setname,
+	id_aa64dfr0_fieldinfo, dfr0);
+}
+
 void
 identifycpu(int fd, const char *cpuname)
 {
 	char path[128];
 	size_t len;
-	struct aarch64_sysctl_cpu_id id;
+#define SYSCTL_CPU_ID_MAXSIZE	64
+	uint64_t sysctlbuf[SYSCTL_CPU_ID_MAXSIZE];
+	struct aarch64_sysctl_cpu_id *id =
+	(struct aarch64_sysctl_cpu_id *)sysctlbuf;
 
 	snprintf(path, sizeof path, "machdep.%s.cpu_id", cpuname);
-	len = sizeof(id);
-	if (sysctlbyname(path, , , 0, 0) == -1)
+	len = sizeof(sysctlbuf);
+	if (sysctlbyname(path, id, , 0, 0) == -1)
 		err(1, "couldn't get %s", path);
+	if (len != sizeof(struct aarch64_sysctl_cpu_id))
+		fprintf(stderr, "Warning: kernel version bumped?\n");
+
+	if (verbose) {
+		printf("%s: MIDR_EL1: 0x%08"PRIx64"\n",
+		cpuname, id->ac_midr);
+		printf("%s: MPIDR_EL1: 0x%016"PRIx64"\n",
+		cpuname, id->ac_mpidr);
+		printf("%s: ID_AA64DFR0_EL1: 0x%016"PRIx64"\n",
+		cpuname, id->ac_aa64dfr0);
+		printf("%s: ID_AA64DFR1_EL1: 0x%016"PRIx64"\n",
+		cpuname, id->ac_aa64dfr1);
+		printf("%s: ID_AA64ISAR0_EL1: 0x%016"PRIx64"\n",
+		cpuname, id->ac_aa64isar0);
+		printf("%s: ID_AA64ISAR1_EL1: 0x%016"PRIx64"\n",
+		cpuname, id->ac_aa64isar1);
+		printf("%s: ID_AA64MMFR0_EL1: 0x%016"PRIx64"\n",
+		cpuname, id->ac_aa64mmfr0);
+		printf("%s: ID_AA64MMFR1_EL1: 0x%016"PRIx64"\n",
+		cpuname, id->ac_aa64mmfr1);
+		printf("%s: ID_AA64MMFR2_EL1: 0x%016"PRIx64"\n",
+		cpuname, id->ac_aa64mmfr2);
+		printf("%s: ID_AA64PFR0_EL1: 0x%08"PRIx64"\n",
+		cpuname, id->ac_aa64pfr0);
+		printf("%s: ID_AA64PFR1_EL1: 0x%08"PRIx64"\n",
+		cpuname, id->ac_aa64pfr1);
+		printf("%s: ID_AA64ZFR0_EL1: 0x%016"PRIx64"\n",
+		cpuname, id->ac_aa64zfr0);
+		printf("%s: MVFR0_EL1: 0x%08"PRIx32"\n",
+		cpuname, id->ac_mvfr0);
+		printf("%s: MVFR1_EL1: 0x%08"PRIx32"\n",
+		cpuname, id->ac_mvfr1);
+		printf("%s: MVFR2_EL1: 0x%08"PRIx32"\n",
+		cpuname, id->ac_mvfr2);
+	}
 
-	identify_midr(cpuname, id.ac_midr);
-	identify_revidr(cpuname, id.ac_revidr);
-	identify_mpidr(cpuname, id.ac_mpidr);
+	identify_midr(cpuname, id->ac_midr);
+	identify_revidr(cpuname, id->ac_revidr);
+	identify_mpidr(cpuname, id->ac_mpidr);
 	print_fieldinfo(cpuname, "isa features 0",
-	id_aa64isar0_fieldinfo,

CVS commit: src/usr.sbin/cpuctl/arch

2018-11-26 Thread Ryo Shimizu

Module Name:src
Committed By:   ryo
Date:   Mon Nov 26 18:08:41 UTC 2018

Modified Files:
src/usr.sbin/cpuctl/arch: aarch64.c

Log Message:
Add ThunderX IDs


To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/usr.sbin/cpuctl/arch/aarch64.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/aarch64.c
diff -u src/usr.sbin/cpuctl/arch/aarch64.c:1.3 src/usr.sbin/cpuctl/arch/aarch64.c:1.4
--- src/usr.sbin/cpuctl/arch/aarch64.c:1.3	Tue Nov 20 01:59:51 2018
+++ src/usr.sbin/cpuctl/arch/aarch64.c	Mon Nov 26 18:08:41 2018
@@ -1,4 +1,4 @@
-/*	$NetBSD: aarch64.c,v 1.3 2018/11/20 01:59:51 mrg Exp $	*/
+/*	$NetBSD: aarch64.c,v 1.4 2018/11/26 18:08:41 ryo Exp $	*/
 
 /*
  * Copyright (c) 2018 Ryo Shimizu 
@@ -29,7 +29,7 @@
 #include 
 
 #ifndef lint
-__RCSID("$NetBSD: aarch64.c,v 1.3 2018/11/20 01:59:51 mrg Exp $");
+__RCSID("$NetBSD: aarch64.c,v 1.4 2018/11/26 18:08:41 ryo Exp $");
 #endif /* no lint */
 
 #include 
@@ -74,7 +74,11 @@ const struct cpuidtab cpuids[] = {
 	{ CPU_ID_CORTEXA72R0 & CPU_PARTMASK, "Cortex-A72", "Cortex", "V8-A" },
 	{ CPU_ID_CORTEXA73R0 & CPU_PARTMASK, "Cortex-A73", "Cortex", "V8-A" },
 	{ CPU_ID_CORTEXA55R1 & CPU_PARTMASK, "Cortex-A55", "Cortex", "V8.2-A" },
-	{ CPU_ID_CORTEXA75R2 & CPU_PARTMASK, "Cortex-A75", "Cortex", "V8.2-A" }
+	{ CPU_ID_CORTEXA75R2 & CPU_PARTMASK, "Cortex-A75", "Cortex", "V8.2-A" },
+	{ CPU_ID_THUNDERXRX, "Cavium ThunderX", "Cavium", "V8-A" },
+	{ CPU_ID_THUNDERX81XXRX, "Cavium ThunderX CN81XX", "Cavium", "V8-A" },
+	{ CPU_ID_THUNDERX83XXRX, "Cavium ThunderX CN83XX", "Cavium", "V8-A" },
+	{ CPU_ID_THUNDERX2RX, "Cavium ThunderX2", "Cavium", "V8.1-A" },
 };
 
 const struct impltab implids[] = {

CVS commit: src/usr.sbin/cpuctl/arch

2018-11-25 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Mon Nov 26 04:45:13 UTC 2018

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
 Print Intel CPUID Architectural Performance Monitoring leaf Fn000a.


To generate a diff of this commit:
cvs rdiff -u -r1.89 -r1.90 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.89 src/usr.sbin/cpuctl/arch/i386.c:1.90
--- src/usr.sbin/cpuctl/arch/i386.c:1.89	Thu Nov 22 06:15:06 2018
+++ src/usr.sbin/cpuctl/arch/i386.c	Mon Nov 26 04:45:13 2018
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.89 2018/11/22 06:15:06 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.90 2018/11/26 04:45:13 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.89 2018/11/22 06:15:06 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.90 2018/11/26 04:45:13 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -2217,12 +2217,18 @@ identifycpu(int fd, const char *cpuname)
 		int32_t bi_index;
 
 		for (bi_index = 1; bi_index <= ci->ci_cpuid_level; bi_index++) {
-#if 0
 			x86_cpuid(bi_index, descs);
 			switch (bi_index) {
-			case 0x0b:
+			case 0x0a:
+print_bits(cpuname, "Perfmon-eax",
+CPUID_PERF_FLAGS0, descs[0]);
+print_bits(cpuname, "Perfmon-ebx",
+CPUID_PERF_FLAGS1, descs[1]);
+print_bits(cpuname, "Perfmon-edx",
+CPUID_PERF_FLAGS3, descs[3]);
 break;
 			default:
+#if 0
 aprint_verbose("%s: basic %08x-eax %08x\n",
 cpuname, bi_index, descs[0]);
 aprint_verbose("%s: basic %08x-ebx %08x\n",
@@ -2231,9 +2237,9 @@ identifycpu(int fd, const char *cpuname)
 cpuname, bi_index, descs[2]);
 aprint_verbose("%s: basic %08x-edx %08x\n",
 cpuname, bi_index, descs[3]);
+#endif
 break;
 			}
-#endif
 		}
 	}

CVS commit: src/usr.sbin/cpuctl/arch

2018-11-21 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Thu Nov 22 06:15:06 UTC 2018

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
 Decode Intel/AMD MONITOR/MWAIT leaf.


To generate a diff of this commit:
cvs rdiff -u -r1.88 -r1.89 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.88 src/usr.sbin/cpuctl/arch/i386.c:1.89
--- src/usr.sbin/cpuctl/arch/i386.c:1.88	Wed Nov 21 12:19:51 2018
+++ src/usr.sbin/cpuctl/arch/i386.c	Thu Nov 22 06:15:06 2018
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.88 2018/11/21 12:19:51 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.89 2018/11/22 06:15:06 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.88 2018/11/21 12:19:51 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.89 2018/11/22 06:15:06 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -2160,6 +2160,29 @@ identifycpu(int fd, const char *cpuname)
 
 	identifycpu_cpuids(ci);
 
+	if ((ci->ci_cpuid_level >= 5)
+	&& ((cpu_vendor == CPUVENDOR_INTEL)
+		|| (cpu_vendor == CPUVENDOR_AMD))) {
+		uint16_t lmin, lmax;
+		x86_cpuid(5, descs);
+		
+		print_bits(cpuname, "MONITOR/MWAIT extensions",
+		CPUID_MON_FLAGS, descs[2]);
+		lmin = __SHIFTOUT(descs[0], CPUID_MON_MINSIZE);
+		lmax = __SHIFTOUT(descs[1], CPUID_MON_MAXSIZE);
+		aprint_normal("%s: monitor-line size %hu", cpuname, lmin);
+		if (lmin != lmax)
+			aprint_normal("-%hu", lmax);
+		aprint_normal("\n");
+
+		for (i = 0; i <= 7; i++) {
+			unsigned int num = CPUID_MON_SUBSTATE(descs[3], i);
+
+			if (num != 0)
+aprint_normal("%s: C%u substates %u\n",
+cpuname, i, num);
+		}
+	}
 	if ((ci->ci_cpuid_level >= 6)
 	&& ((cpu_vendor == CPUVENDOR_INTEL)
 		|| (cpu_vendor == CPUVENDOR_AMD))) {

CVS commit: src/usr.sbin/cpuctl/arch

2018-11-21 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Wed Nov 21 12:19:52 UTC 2018

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
 Decode package, core and SMT id if CPUID 0x0b is available on Intel processor.
If the value is different from the kernel value, we should fix the kernel code.

TODO: Use 0x1f if it's available.


To generate a diff of this commit:
cvs rdiff -u -r1.87 -r1.88 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.87 src/usr.sbin/cpuctl/arch/i386.c:1.88
--- src/usr.sbin/cpuctl/arch/i386.c:1.87	Wed Nov 21 10:34:53 2018
+++ src/usr.sbin/cpuctl/arch/i386.c	Wed Nov 21 12:19:51 2018
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.87 2018/11/21 10:34:53 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.88 2018/11/21 12:19:51 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.87 2018/11/21 10:34:53 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.88 2018/11/21 12:19:51 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -1786,23 +1786,14 @@ print_bits(const char *cpuname, const ch
 }
 
 static void
-identifycpu_cpuids(struct cpu_info *ci)
+identifycpu_cpuids_intel_0x04(struct cpu_info *ci)
 {
-	const char *cpuname = ci->ci_dev;
 	u_int lp_max = 1;	/* logical processors per package */
 	u_int smt_max;		/* smt per core */
 	u_int core_max = 1;	/* core per package */
 	u_int smt_bits, core_bits;
 	uint32_t descs[4];
 
-	aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid);
-	ci->ci_packageid = ci->ci_initapicid;
-	ci->ci_coreid = 0;
-	ci->ci_smtid = 0;
-	if (cpu_vendor != CPUVENDOR_INTEL) {
-		return;
-	}
-
 	/*
 	 * 253668.pdf 7.10.2
 	 */
@@ -1811,32 +1802,110 @@ identifycpu_cpuids(struct cpu_info *ci)
 		x86_cpuid(1, descs);
 		lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES);
 	}
-	if (ci->ci_cpuid_level >= 4) {
-		x86_cpuid2(4, 0, descs);
-		core_max = __SHIFTOUT(descs[0], CPUID_DCP_CORE_P_PKG) + 1;
-	}
+	x86_cpuid2(4, 0, descs);
+	core_max = __SHIFTOUT(descs[0], CPUID_DCP_CORE_P_PKG) + 1;
+
 	assert(lp_max >= core_max);
 	smt_max = lp_max / core_max;
 	smt_bits = ilog2(smt_max - 1) + 1;
 	core_bits = ilog2(core_max - 1) + 1;
-	if (smt_bits + core_bits) {
+
+	if (smt_bits + core_bits)
 		ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits);
+
+	if (core_bits)
+		ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid,
+		__BITS(smt_bits, smt_bits + core_bits - 1));
+
+	if (smt_bits)
+		ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid,
+		__BITS((int)0, (int)(smt_bits - 1)));
+}
+
+static void
+identifycpu_cpuids_intel_0x0b(struct cpu_info *ci)
+{
+	const char *cpuname = ci->ci_dev;
+	u_int smt_bits, core_bits, core_shift = 0, pkg_shift = 0;
+	uint32_t descs[4];
+	int i;
+
+	x86_cpuid(0x0b, descs);
+	if (descs[1] == 0) {
+		identifycpu_cpuids_intel_0x04(ci);
+		return;
+	}
+
+	for (i = 0; ; i++) {
+		unsigned int shiftnum, lvltype;
+		x86_cpuid2(0x0b, i, descs);
+
+		/* On invalid level, (EAX and) EBX return 0 */
+		if (descs[1] == 0)
+			break;
+
+		shiftnum = __SHIFTOUT(descs[0], CPUID_TOP_SHIFTNUM);
+		lvltype = __SHIFTOUT(descs[2], CPUID_TOP_LVLTYPE);
+		switch (lvltype) {
+		case CPUID_TOP_LVLTYPE_SMT:
+			core_shift = shiftnum;
+			break;
+		case CPUID_TOP_LVLTYPE_CORE:
+			pkg_shift = shiftnum;
+			break;
+		case CPUID_TOP_LVLTYPE_INVAL:
+			aprint_verbose("%s: Invalid level type\n", cpuname);
+			break;
+		default:
+			aprint_verbose("%s: Unknown level type(%d) \n",
+			cpuname, lvltype);
+			break;
+		}
 	}
+
+	assert(pkg_shift >= core_shift);
+	smt_bits = core_shift;
+	core_bits = pkg_shift - core_shift;
+
+	ci->ci_packageid = ci->ci_initapicid >> pkg_shift;
+
+	if (core_bits)
+		ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid,
+		__BITS(core_shift, pkg_shift - 1));
+
+	if (smt_bits)
+		ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid,
+		__BITS((int)0, core_shift - 1));
+}
+
+static void
+identifycpu_cpuids_intel(struct cpu_info *ci)
+{
+	const char *cpuname = ci->ci_dev;
+
+	if (ci->ci_cpuid_level >= 0x0b)
+		identifycpu_cpuids_intel_0x0b(ci);
+	else if (ci->ci_cpuid_level >= 4)
+		identifycpu_cpuids_intel_0x04(ci);
+
 	aprint_verbose("%s: Cluster/Package ID %u\n", cpuname,
 	ci->ci_packageid);
-	if (core_bits) {
-		u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1);
+	aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid);
+	aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid);
+}
 
-		ci->ci_coreid =
-		__SHIFTOUT(ci->ci_initapicid, core_mask);
-		aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid);
-	}
-	if (smt_bits) {
-		u_int smt_mask = __BITS((int)0, (int)(smt_bits - 1));
+static void
+identifycpu_cpuids(struct cpu_info *ci)
+{
+	const char *cpuname = ci->ci_dev;
 
-		ci->ci_smtid =

CVS commit: src/usr.sbin/cpuctl/arch

2018-11-20 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Wed Nov 21 06:10:25 UTC 2018

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
- Use ci_feat_val[7] as CPUID 7 %edx to match x86/cpu.h
- AMD also has CPUID 6.
- Remove unused code for coretemp.
- Consistently use descs[] instead of data[].


To generate a diff of this commit:
cvs rdiff -u -r1.85 -r1.86 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.85 src/usr.sbin/cpuctl/arch/i386.c:1.86
--- src/usr.sbin/cpuctl/arch/i386.c:1.85	Wed Jun 20 04:04:50 2018
+++ src/usr.sbin/cpuctl/arch/i386.c	Wed Nov 21 06:10:25 2018
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.85 2018/06/20 04:04:50 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.86 2018/11/21 06:10:25 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.85 2018/06/20 04:04:50 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.86 2018/11/21 06:10:25 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -98,7 +98,7 @@ struct cpu_info {
 	uint32_t	ci_signature;	 /* X86 cpuid type */
 	uint32_t	ci_family;	 /* from ci_signature */
 	uint32_t	ci_model;	 /* from ci_signature */
-	uint32_t	ci_feat_val[9];	 /* X86 CPUID feature bits
+	uint32_t	ci_feat_val[10]; /* X86 CPUID feature bits
 	  *	[0] basic features %edx
 	  *	[1] basic features %ecx
 	  *	[2] extended features %edx
@@ -106,8 +106,9 @@ struct cpu_info {
 	  *	[4] VIA padlock features
 	  *	[5] structure ext. feat. %ebx
 	  *	[6] structure ext. feat. %ecx
-	  *	[7] XCR0 bits (d:0 %eax)
-	  *	[8] xsave flags (d:1 %eax)
+	  * [7] structure ext. feat. %edx
+	  *	[8] XCR0 bits (d:0 %eax)
+	  *	[9] xsave flags (d:1 %eax)
 	  */
 	uint32_t	ci_cpu_class;	 /* CPU class */
 	uint32_t	ci_brand_id;	 /* Intel brand id */
@@ -1672,19 +1673,20 @@ cpu_probe_base_features(struct cpu_info 
 	x86_cpuid(7, descs);
 	ci->ci_feat_val[5] = descs[1];
 	ci->ci_feat_val[6] = descs[2];
+	ci->ci_feat_val[7] = descs[3];
 
 	if (ci->ci_cpuid_level < 0xd)
 		return;
 
 	/* Get support XCR0 bits */
 	x86_cpuid2(0xd, 0, descs);
-	ci->ci_feat_val[7] = descs[0];	/* Actually 64 bits */
+	ci->ci_feat_val[8] = descs[0];	/* Actually 64 bits */
 	ci->ci_cur_xsave = descs[1];
 	ci->ci_max_xsave = descs[2];
 
 	/* Additional flags (eg xsaveopt support) */
 	x86_cpuid2(0xd, 1, descs);
-	ci->ci_feat_val[8] = descs[0];	 /* Actually 64 bits */
+	ci->ci_feat_val[9] = descs[0];	 /* Actually 64 bits */
 }
 
 static void
@@ -2034,18 +2036,17 @@ identifycpu(int fd, const char *cpuname)
 	if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD))
 		print_bits(cpuname, "features5", CPUID_SEF_FLAGS,
 		ci->ci_feat_val[5]);
-	if (cpu_vendor == CPUVENDOR_INTEL)
+	if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD))
 		print_bits(cpuname, "features6", CPUID_SEF_FLAGS1,
 		ci->ci_feat_val[6]);
 
-	if ((cpu_vendor == CPUVENDOR_INTEL) && (ci->ci_cpuid_level >= 7)) {
-		x86_cpuid(7, descs);
-		print_bits(cpuname, "SEF edx", CPUID_SEF_FLAGS2, descs[3]);
-	}
+	if (cpu_vendor == CPUVENDOR_INTEL)
+		print_bits(cpuname, "features7", CPUID_SEF_FLAGS2,
+		ci->ci_feat_val[7]);
 
-	print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[7]);
+	print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[8]);
 	print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS,
-	ci->ci_feat_val[8]);
+	ci->ci_feat_val[9]);
 
 	if (ci->ci_max_xsave != 0) {
 		aprint_normal("%s: xsave area size: current %d, maximum %d",
@@ -2090,54 +2091,48 @@ identifycpu(int fd, const char *cpuname)
 
 	identifycpu_cpuids(ci);
 
-#ifdef INTEL_CORETEMP
-	if (cpu_vendor == CPUVENDOR_INTEL && ci->ci_cpuid_level >= 0x06)
-		coretemp_register(ci);
-#endif
-
+	if ((ci->ci_cpuid_level >= 6)
+	&& ((cpu_vendor == CPUVENDOR_INTEL)
+		|| (cpu_vendor == CPUVENDOR_AMD))) {
+		x86_cpuid(6, descs);
+		print_bits(cpuname, "DSPM-eax", CPUID_DSPM_FLAGS, descs[0]);
+		print_bits(cpuname, "DSPM-ecx", CPUID_DSPM_FLAGS1, descs[2]);
+	}
 	if (cpu_vendor == CPUVENDOR_AMD) {
-		uint32_t data[4];
-
-		x86_cpuid(0x8000, data);
-		if (data[0] >= 0x8007)
+		x86_cpuid(0x8000, descs);
+		if (descs[0] >= 0x8007)
 			powernow_probe(ci);
 
-		if ((data[0] >= 0x800a)
+		if ((descs[0] >= 0x800a)
 		&& (ci->ci_feat_val[3] & CPUID_SVM) != 0) {
-			x86_cpuid(0x800a, data);
+			x86_cpuid(0x800a, descs);
 			aprint_verbose("%s: SVM Rev. %d\n", cpuname,
-			data[0] & 0xf);
-			aprint_verbose("%s: SVM NASID %d\n", cpuname, data[1]);
+			descs[0] & 0xf);
+			aprint_verbose("%s: SVM NASID %d\n", cpuname,
+			descs[1]);
 			print_bits(cpuname, "SVM features",
-			CPUID_AMD_SVM_FLAGS,

CVS commit: src/usr.sbin/cpuctl/arch

2018-06-19 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Wed Jun 20 04:04:50 UTC 2018

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
 Whitespace fix. No functional change.


To generate a diff of this commit:
cvs rdiff -u -r1.84 -r1.85 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.84 src/usr.sbin/cpuctl/arch/i386.c:1.85
--- src/usr.sbin/cpuctl/arch/i386.c:1.84	Fri Mar 30 09:24:40 2018
+++ src/usr.sbin/cpuctl/arch/i386.c	Wed Jun 20 04:04:50 2018
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.84 2018/03/30 09:24:40 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.85 2018/06/20 04:04:50 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.84 2018/03/30 09:24:40 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.85 2018/06/20 04:04:50 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -92,7 +92,7 @@ __RCSID("$NetBSD: i386.c,v 1.84 2018/03/
 
 struct cpu_info {
 	const char	*ci_dev;
-	int32_t		ci_cpu_type; /* for cpu's without cpuid */
+	int32_t		ci_cpu_type;	 /* for cpu's without cpuid */
 	int32_t		ci_cpuid_level;	 /* highest cpuid supported */
 	uint32_t	ci_cpuid_extlevel; /* highest cpuid extended func lv */
 	uint32_t	ci_signature;	 /* X86 cpuid type */
@@ -161,9 +161,9 @@ static const struct x86_cache_info intel
 static const char * const i386_intel_brand[] = {
 	"",		/* Unsupported */
 	"Celeron",	/* Intel (R) Celeron (TM) processor */
-	"Pentium III",  /* Intel (R) Pentium (R) III processor */
+	"Pentium III",	/* Intel (R) Pentium (R) III processor */
 	"Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */
-	"Pentium III",  /* Intel (R) Pentium (R) III processor */
+	"Pentium III",	/* Intel (R) Pentium (R) III processor */
 	"",		/* 0x05: Reserved */
 	"Mobile Pentium III",/* Mobile Intel (R) Pentium (R) III processor-M */
 	"Mobile Celeron",   /* Mobile Intel (R) Celeron (R) processor */
@@ -177,11 +177,11 @@ static const char * const i386_intel_bra
 	"Mobile Celeron",   /* Mobile Intel (R) Celeron (R) processor */
 	"",		/* 0x10: Reserved */
 	"Mobile Genuine",   /* Moblie Genuine Intel (R) processor */
-	"Celeron M",/* Intel (R) Celeron (R) M processor */
+	"Celeron M",	/* Intel (R) Celeron (R) M processor */
 	"Mobile Celeron",   /* Mobile Intel (R) Celeron (R) processor */
-	"Celeron",  /* Intel (R) Celeron (R) processor */
+	"Celeron",	/* Intel (R) Celeron (R) processor */
 	"Mobile Genuine",   /* Moblie Genuine Intel (R) processor */
-	"Pentium M",/* Intel (R) Pentium (R) M processor */
+	"Pentium M",	/* Intel (R) Pentium (R) M processor */
 	"Mobile Celeron",   /* Mobile Intel (R) Celeron (R) processor */
 };
 
@@ -215,8 +215,8 @@ static void	powernow_probe(struct cpu_in
 static void	intel_family_new_probe(struct cpu_info *);
 static void	via_cpu_probe(struct cpu_info *);
 /* (Cache) Info functions */
-static void 	intel_cpu_cacheinfo(struct cpu_info *);
-static void 	amd_cpu_cacheinfo(struct cpu_info *);
+static void	intel_cpu_cacheinfo(struct cpu_info *);
+static void	amd_cpu_cacheinfo(struct cpu_info *);
 static void	via_cpu_cacheinfo(struct cpu_info *);
 static void	tmx86_get_longrun_status(u_int *, u_int *, u_int *);
 static void	transmeta_cpu_info(struct cpu_info *);
@@ -251,7 +251,7 @@ const struct cpu_nocpuid_nameclass i386_
 	  NULL, NULL, NULL },			/* CPU_486DLC */
 	{ CPUVENDOR_CYRIX, "Cyrix", "6x86",	CPUCLASS_486,
 	  NULL, NULL, NULL },		/* CPU_6x86 */
-	{ CPUVENDOR_NEXGEN,"NexGen","586",  CPUCLASS_386,
+	{ CPUVENDOR_NEXGEN,"NexGen","586",	CPUCLASS_386,
 	  NULL, NULL, NULL },			/* CPU_NX586 */
 };
 
@@ -1684,7 +1684,7 @@ cpu_probe_base_features(struct cpu_info 
 
 	/* Additional flags (eg xsaveopt support) */
 	x86_cpuid2(0xd, 1, descs);
-	ci->ci_feat_val[8] = descs[0];   /* Actually 64 bits */
+	ci->ci_feat_val[8] = descs[0];	 /* Actually 64 bits */
 }
 
 static void
@@ -1928,7 +1928,7 @@ identifycpu(int fd, const char *cpuname)
 			cpufam = >cpu_family[family - CPU_MINFAMILY];
 			name = cpufam->cpu_models[ci->ci_model];
 			if (name == NULL || *name == '\0')
-			name = cpufam->cpu_model_default;
+name = cpufam->cpu_model_default;
 			class = cpufam->cpu_class;
 			ci->ci_info = cpufam->cpu_info;
 
@@ -1944,7 +1944,7 @@ identifycpu(int fd, const char *cpuname)
 __arraycount(i386_intel_brand) &&
 i386_intel_brand[ci->ci_brand_id])
 	name =
-	 i386_intel_brand[ci->ci_brand_id];
+	i386_intel_brand[ci->ci_brand_id];
 			}
 
 			if (cpu_vendor == CPUVENDOR_AMD) {
@@ -2049,7 +2049,7 @@ identifycpu(int fd, const char *cpuname)
 
 	if (ci->ci_max_xsave != 0) {
 		aprint_normal("%s: xsave area size: current %d,

CVS commit: src/usr.sbin/cpuctl/arch

2018-05-08 Thread Ryo Shimizu

Module Name:src
Committed By:   ryo
Date:   Tue May  8 11:42:43 UTC 2018

Modified Files:
src/usr.sbin/cpuctl/arch: aarch64.c

Log Message:
TGran64 indication was actually the opposite


To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/usr.sbin/cpuctl/arch/aarch64.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/aarch64.c
diff -u src/usr.sbin/cpuctl/arch/aarch64.c:1.1 src/usr.sbin/cpuctl/arch/aarch64.c:1.2
--- src/usr.sbin/cpuctl/arch/aarch64.c:1.1	Thu May  3 15:47:36 2018
+++ src/usr.sbin/cpuctl/arch/aarch64.c	Tue May  8 11:42:43 2018
@@ -1,4 +1,4 @@
-/*	$NetBSD: aarch64.c,v 1.1 2018/05/03 15:47:36 ryo Exp $	*/
+/*	$NetBSD: aarch64.c,v 1.2 2018/05/08 11:42:43 ryo Exp $	*/
 
 /*
  * Copyright (c) 2018 Ryo Shimizu 
@@ -29,7 +29,7 @@
 #include 
 
 #ifndef lint
-__RCSID("$NetBSD: aarch64.c,v 1.1 2018/05/03 15:47:36 ryo Exp $");
+__RCSID("$NetBSD: aarch64.c,v 1.2 2018/05/08 11:42:43 ryo Exp $");
 #endif /* no lint */
 
 #include 
@@ -239,8 +239,8 @@ struct fieldinfo id_aa64mmfr0_fieldinfo[
 	{
 		.bitpos = 24, .bitwidth = 4, .name = "TGran64",
 		.info = (const char *[16]) { /* 16=4bit */
-			[0] = "No 64KB granule",
-			[15] = "64KB granule"
+			[0] = "64KB granule",
+			[15] = "No 64KB granule"
 		}
 	},
 	{

CVS commit: src/usr.sbin/cpuctl/arch

2018-05-03 Thread Ryo Shimizu

Module Name:src
Committed By:   ryo
Date:   Thu May  3 15:47:36 UTC 2018

Added Files:
src/usr.sbin/cpuctl/arch: aarch64.c

Log Message:
add aarch64 support for cpuctl identify.


To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1 src/usr.sbin/cpuctl/arch/aarch64.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Added files:

Index: src/usr.sbin/cpuctl/arch/aarch64.c
diff -u /dev/null src/usr.sbin/cpuctl/arch/aarch64.c:1.1
--- /dev/null	Thu May  3 15:47:36 2018
+++ src/usr.sbin/cpuctl/arch/aarch64.c	Thu May  3 15:47:36 2018
@@ -0,0 +1,619 @@
+/*	$NetBSD: aarch64.c,v 1.1 2018/05/03 15:47:36 ryo Exp $	*/
+
+/*
+ * Copyright (c) 2018 Ryo Shimizu 
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+
+#ifndef lint
+__RCSID("$NetBSD: aarch64.c,v 1.1 2018/05/03 15:47:36 ryo Exp $");
+#endif /* no lint */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include "../cpuctl.h"
+
+struct cpuidtab {
+	uint32_t cpu_partnum;
+	const char *cpu_name;
+	const char *cpu_class;
+	const char *cpu_architecture;
+};
+
+struct impltab {
+	uint32_t impl_id;
+	const char *impl_name;
+};
+
+struct fieldinfo {
+	int bitpos;
+	int bitwidth;
+	const char *name;
+	const char * const *info;
+};
+
+
+#define CPU_PARTMASK	(CPU_ID_IMPLEMENTOR_MASK | CPU_ID_PARTNO_MASK)
+const struct cpuidtab cpuids[] = {
+	{ CPU_ID_CORTEXA53R0 & CPU_PARTMASK, "Cortex-A53", "Cortex", "V8-A" },
+	{ CPU_ID_CORTEXA57R0 & CPU_PARTMASK, "Cortex-A57", "Cortex", "V8-A" },
+	{ CPU_ID_CORTEXA72R0 & CPU_PARTMASK, "Cortex-A72", "Cortex", "V8-A" },
+	{ CPU_ID_CORTEXA73R0 & CPU_PARTMASK, "Cortex-A73", "Cortex", "V8-A" },
+	{ CPU_ID_CORTEXA55R1 & CPU_PARTMASK, "Cortex-A55", "Cortex", "V8.2-A" },
+	{ CPU_ID_CORTEXA75R2 & CPU_PARTMASK, "Cortex-A75", "Cortex", "V8.2-A" }
+};
+
+const struct impltab implids[] = {
+	{ CPU_ID_ARM_LTD,	"ARM Limited"},
+	{ CPU_ID_BROADCOM,	"Broadcom Corporation"			},
+	{ CPU_ID_CAVIUM,	"Cavium Inc."},
+	{ CPU_ID_DEC,		"Digital Equipment Corporation"		},
+	{ CPU_ID_INFINEON,	"Infineon Technologies AG"		},
+	{ CPU_ID_MOTOROLA,	"Motorola or Freescale Semiconductor Inc." },
+	{ CPU_ID_NVIDIA,	"NVIDIA Corporation"			},
+	{ CPU_ID_APM,		"Applied Micro Circuits Corporation"	},
+	{ CPU_ID_QUALCOMM,	"Qualcomm Inc."},
+	{ CPU_ID_SAMSUNG,	"SAMSUNG"},
+	{ CPU_ID_TI,		"Texas Instruments"			},
+	{ CPU_ID_MARVELL,	"Marvell International Ltd."		},
+	{ CPU_ID_APPLE,		"Apple Inc."},
+	{ CPU_ID_FARADAY,	"Faraday Technology Corporation"	},
+	{ CPU_ID_INTEL,		"Intel Corporation"			}
+};
+
+/* ID_AA64PFR0_EL1 - AArch64 Processor Feature Register 0 */
+struct fieldinfo id_aa64pfr0_fieldinfo[] = {
+	{
+		.bitpos = 0, .bitwidth = 4, .name = "EL0",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "No EL0",
+			[1] = "AArch64",
+			[2] = "AArch64/AArch32"
+		}
+	},
+	{
+		.bitpos = 4, .bitwidth = 4, .name = "EL1",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "No EL1",
+			[1] = "AArch64",
+			[2] = "AArch64/AArch32"
+		}
+	},
+	{
+		.bitpos = 8, .bitwidth = 4, .name = "EL2",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "No EL2",
+			[1] = "AArch64",
+			[2] = "AArch64/AArch32"
+		}
+	},
+	{
+		.bitpos = 12, .bitwidth = 4, .name = "EL3",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "No EL3",
+			[1] = "AArch64",
+			[2] = "AArch64/AArch32"
+		}
+	},
+	{
+		.bitpos = 16, .bitwidth = 4, .name = "FP",
+		.info = (const char *[16]) { /* 16=4bit */
+			[0] = "Floating Point",
+			[15] = "No Floating Point"
+		}
+	},
+	{
+		.bitpos = 20, .bitwidth = 4, .name = "AdvSIMD",
+		.info = (const char

CVS commit: src/usr.sbin/cpuctl/arch

2018-03-30 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Fri Mar 30 09:24:40 UTC 2018

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
>From the latest Intel SDM:
- Add Xeon Phi 7215, 7285 and 7295
- Add Coffee Lake


To generate a diff of this commit:
cvs rdiff -u -r1.83 -r1.84 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.83 src/usr.sbin/cpuctl/arch/i386.c:1.84
--- src/usr.sbin/cpuctl/arch/i386.c:1.83	Fri Mar  9 08:49:32 2018
+++ src/usr.sbin/cpuctl/arch/i386.c	Fri Mar 30 09:24:40 2018
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.83 2018/03/09 08:49:32 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.84 2018/03/30 09:24:40 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.83 2018/03/09 08:49:32 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.84 2018/03/30 09:24:40 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -381,9 +381,9 @@ const struct cpu_cpuid_nameclass i386_cp
 [0x5f] = "Atom (Goldmont, Denverton)",
 [0x66] = "Future Core (Cannon Lake)",
 [0x7a] = "Atom (Goldmont Plus)",
-[0x85] = "Future Xeon Phi (Knights Mill)",
-[0x8e] = "7th gen Core (Kaby Lake)",
-[0x9e] = "7th gen Core (Kaby Lake)",
+[0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)",
+[0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake)",
+[0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake)",
 			},
 			"Pentium Pro, II or III",	/* Default */
 			NULL,

CVS commit: src/usr.sbin/cpuctl/arch

2018-03-05 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Mon Mar  5 10:54:05 UTC 2018

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
 Calculate way and number of entries correctly from CPUID leaf 18H.


To generate a diff of this commit:
cvs rdiff -u -r1.81 -r1.82 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.81 src/usr.sbin/cpuctl/arch/i386.c:1.82
--- src/usr.sbin/cpuctl/arch/i386.c:1.81	Mon Mar  5 05:50:37 2018
+++ src/usr.sbin/cpuctl/arch/i386.c	Mon Mar  5 10:54:05 2018
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.81 2018/03/05 05:50:37 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.82 2018/03/05 10:54:05 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.81 2018/03/05 05:50:37 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.82 2018/03/05 10:54:05 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -1094,6 +1094,8 @@ intel_cpu_cacheinfo(struct cpu_info *ci)
 	x86_cpuid(0x18, descs);
 	iterations = descs[0];
 	for (i = 0; i <= iterations; i++) {
+		bool full;
+
 		x86_cpuid2(0x18, i, descs);
 		type = __SHIFTOUT(descs[3], CPUID_DATP_TCTYPE);
 		if (type == CPUID_DATP_TCTYPE_N)
@@ -1158,8 +1160,11 @@ intel_cpu_cacheinfo(struct cpu_info *ci)
 		}
 		ways = __SHIFTOUT(descs[1], CPUID_DATP_WAYS);
 		sets = descs[2];
-		ci->ci_cinfo[caitype].cai_totalsize = sets; /* entries */
-		ci->ci_cinfo[caitype].cai_associativity = ways;
+		full = descs[3] & CPUID_DATP_FULLASSOC;
+		ci->ci_cinfo[caitype].cai_totalsize
+		= ways * sets; /* entries */
+		ci->ci_cinfo[caitype].cai_associativity
+		= full ? 0xff : ways;
 		ci->ci_cinfo[caitype].cai_linesize = linesize; /* page size */
 	}
 }

CVS commit: src/usr.sbin/cpuctl/arch

2018-03-04 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Mon Mar  5 05:50:37 UTC 2018

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
- Parse the TLB info from `cpuid leaf 18H' on Intel processor. Currently,
  this change doesn't decode perfectly.  Tested with Gemini Lake. It has
  two L2 Shared TLB. One is 4MB and another is 2MB/4MB but former isn't
  printed yet:

cpu0: ITLB 1 4KB entries 48-way
cpu0: DTLB 1 4KB entries 32-way
cpu0: L2 STLB 8 4MB entries 4-way

  Need some rework for struct x86_cache_info.
- Use aprint_error_dev() for error output.


To generate a diff of this commit:
cvs rdiff -u -r1.80 -r1.81 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.80 src/usr.sbin/cpuctl/arch/i386.c:1.81
--- src/usr.sbin/cpuctl/arch/i386.c:1.80	Tue Jan 16 08:23:18 2018
+++ src/usr.sbin/cpuctl/arch/i386.c	Mon Mar  5 05:50:37 2018
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.80 2018/01/16 08:23:18 mrg Exp $	*/
+/*	$NetBSD: i386.c,v 1.81 2018/03/05 05:50:37 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.80 2018/01/16 08:23:18 mrg Exp $");
+__RCSID("$NetBSD: i386.c,v 1.81 2018/03/05 05:50:37 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -1025,8 +1025,10 @@ intel_cpu_cacheinfo(struct cpu_info *ci)
 desc);
 if (cai != NULL)
 	ci->ci_cinfo[cai->cai_index] = *cai;
-else if ((verbose != 0) && (desc != 0xff))
-	printf("Unknown cacheinfo desc %02x\n",
+else if ((verbose != 0) && (desc != 0xff)
+&& (desc != 0xfe))
+	aprint_error_dev(ci->ci_dev, "error:"
+	" Unknown cacheinfo desc %02x\n",
 	desc);
 			}
 		}
@@ -1069,7 +1071,8 @@ intel_cpu_cacheinfo(struct cpu_info *ci)
 			break;
 		}
 		if (caitype == -1) {
-			printf("unknown cache level (%d & %d)\n",
+			aprint_error_dev(ci->ci_dev,
+			"error: unknown cache level (%d & %d)\n",
 			level, type);
 			continue;
 		}
@@ -1084,6 +1087,81 @@ intel_cpu_cacheinfo(struct cpu_info *ci)
 		ci->ci_cinfo[caitype].cai_associativity = ways;
 		ci->ci_cinfo[caitype].cai_linesize = linesize;
 	}
+
+	if (ci->ci_cpuid_level < 0x18)
+		return;
+	/* Parse the TLB info from `cpuid leaf 18H', if we have it. */
+	x86_cpuid(0x18, descs);
+	iterations = descs[0];
+	for (i = 0; i <= iterations; i++) {
+		x86_cpuid2(0x18, i, descs);
+		type = __SHIFTOUT(descs[3], CPUID_DATP_TCTYPE);
+		if (type == CPUID_DATP_TCTYPE_N)
+			continue;
+		level = __SHIFTOUT(descs[3], CPUID_DATP_TCLEVEL);
+		switch (level) {
+		case 1:
+			if (type == CPUID_DATP_TCTYPE_I)
+caitype = CAI_ITLB; /* XXX or ITLB2? */
+			else if (type == CPUID_DATP_TCTYPE_D)
+caitype = CAI_DTLB;
+			else
+caitype = -1;
+			break;
+		case 2:
+			if (type == CPUID_DATP_TCTYPE_I)
+caitype = CAI_L2_ITLB;
+			else if (type == CPUID_DATP_TCTYPE_D)
+caitype = CAI_L2_DTLB;
+			else if (type == CPUID_DATP_TCTYPE_U)
+caitype = CAI_L2_STLB;
+			else
+caitype = -1;
+			break;
+		case 3:
+			/* XXX need work for L3 TLB */
+			caitype = CAI_L3CACHE;
+			break;
+		default:
+			caitype = -1;
+			break;
+		}
+		if (caitype == -1) {
+			aprint_error_dev(ci->ci_dev,
+			"error: unknown TLB level (%d & %d)\n",
+			level, type);
+			continue;
+		}
+		switch (__SHIFTOUT(descs[1], CPUID_DATP_PGSIZE)) {
+		case CPUID_DATP_PGSIZE_4KB:
+			linesize = 4 * 1024;
+			break;
+		case CPUID_DATP_PGSIZE_2MB:
+			linesize = 2 * 1024 * 1024;
+			break;
+		case CPUID_DATP_PGSIZE_4MB:
+			linesize = 4 * 1024 * 1024;
+			break;
+		case CPUID_DATP_PGSIZE_1GB:
+			linesize = 1024 * 1024 * 1024;
+			break;
+		case CPUID_DATP_PGSIZE_2MB | CPUID_DATP_PGSIZE_4MB:
+			aprint_error_dev(ci->ci_dev,
+			"WARINING: Currently 2M/4M info can't print correctly\n");
+			linesize = 4 * 1024 * 1024;
+			break;
+		default:
+			aprint_error_dev(ci->ci_dev,
+			"error: Unknown size combination\n");
+			linesize = 4 * 1024;
+			break;
+		}
+		ways = __SHIFTOUT(descs[1], CPUID_DATP_WAYS);
+		sets = descs[2];
+		ci->ci_cinfo[caitype].cai_totalsize = sets; /* entries */
+		ci->ci_cinfo[caitype].cai_associativity = ways;
+		ci->ci_cinfo[caitype].cai_linesize = linesize; /* page size */
+	}
 }
 
 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] =

CVS commit: src/usr.sbin/cpuctl/arch

2018-01-09 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Wed Jan 10 07:08:35 UTC 2018

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
 Print Intel cpuid 7 %edx.

Example output of cpuctl -v identify 0:

+cpu0: 0007:  27ab  0c00
(snip)
+cpu0: SEF edx 0xc00


To generate a diff of this commit:
cvs rdiff -u -r1.78 -r1.79 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.78 src/usr.sbin/cpuctl/arch/i386.c:1.79
--- src/usr.sbin/cpuctl/arch/i386.c:1.78	Thu Oct 19 03:09:55 2017
+++ src/usr.sbin/cpuctl/arch/i386.c	Wed Jan 10 07:08:35 2018
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.78 2017/10/19 03:09:55 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.79 2018/01/10 07:08:35 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.78 2017/10/19 03:09:55 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.79 2018/01/10 07:08:35 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -1900,6 +1900,12 @@ identifycpu(int fd, const char *cpuname)
 	if (cpu_vendor == CPUVENDOR_INTEL)
 		print_bits(cpuname, "features6", CPUID_SEF_FLAGS1,
 		ci->ci_feat_val[6]);
+
+	if ((cpu_vendor == CPUVENDOR_INTEL) && (ci->ci_cpuid_level >= 7)) {
+		x86_cpuid(7, descs);
+		print_bits(cpuname, "SEF edx", CPUID_SEF_FLAGS2, descs[3]);
+	}
+
 	print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[7]);
 	print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS,
 	ci->ci_feat_val[8]);

CVS commit: src/usr.sbin/cpuctl/arch

2017-10-18 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Thu Oct 19 03:09:55 UTC 2017

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
Update from Intel SDM:
 0x55: Xeon Scalable (Skylake)
 0x57: Xeon Phi [357]200 (Knights Landing)
 0x66: Future Core (Cannon Lake)
 0x85: Future Xeon Phi (Knights Mill)


To generate a diff of this commit:
cvs rdiff -u -r1.77 -r1.78 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.77 src/usr.sbin/cpuctl/arch/i386.c:1.78
--- src/usr.sbin/cpuctl/arch/i386.c:1.77	Tue Oct 17 14:48:42 2017
+++ src/usr.sbin/cpuctl/arch/i386.c	Thu Oct 19 03:09:55 2017
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.77 2017/10/17 14:48:42 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.78 2017/10/19 03:09:55 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.77 2017/10/17 14:48:42 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.78 2017/10/19 03:09:55 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -371,16 +371,17 @@ const struct cpu_cpuid_nameclass i386_cp
 [0x4d] = "Atom C2000",
 [0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
 [0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme",
-[0x55] = "Future Xeon",
+[0x55] = "Xeon Scalable (Skylake)",
 [0x56] = "Xeon D-1500 (Broadwell)",
-[0x57] = "Xeon Phi [357]200",
+[0x57] = "Xeon Phi [357]200 (Knights Landing)",
 [0x5a] = "Atom E3500",
 [0x5c] = "Atom (Goldmont)",
 [0x5d] = "Atom X3-C3000 (Silvermont)",
 [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
 [0x5f] = "Atom (Goldmont, Denverton)",
+[0x66] = "Future Core (Cannon Lake)",
 [0x7a] = "Atom (Goldmont Plus)",
-[0x85] = "Future Xeon Phi",
+[0x85] = "Future Xeon Phi (Knights Mill)",
 [0x8e] = "7th gen Core (Kaby Lake)",
 [0x9e] = "7th gen Core (Kaby Lake)",
 			},

CVS commit: src/usr.sbin/cpuctl/arch

2017-10-17 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Tue Oct 17 14:48:43 UTC 2017

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
Update from the latest Intel SDM:
 0x5c: Atom (Goldmont)
 0x5f: Atom (Goldmont, Denverton)
 0x7a: Atom (Goldmont Plus)


To generate a diff of this commit:
cvs rdiff -u -r1.76 -r1.77 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.76 src/usr.sbin/cpuctl/arch/i386.c:1.77
--- src/usr.sbin/cpuctl/arch/i386.c:1.76	Mon Oct 16 10:10:48 2017
+++ src/usr.sbin/cpuctl/arch/i386.c	Tue Oct 17 14:48:42 2017
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.76 2017/10/16 10:10:48 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.77 2017/10/17 14:48:42 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.76 2017/10/16 10:10:48 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.77 2017/10/17 14:48:42 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -375,10 +375,11 @@ const struct cpu_cpuid_nameclass i386_cp
 [0x56] = "Xeon D-1500 (Broadwell)",
 [0x57] = "Xeon Phi [357]200",
 [0x5a] = "Atom E3500",
-[0x5c] = "Next Atom (Goldmont)",
+[0x5c] = "Atom (Goldmont)",
 [0x5d] = "Atom X3-C3000 (Silvermont)",
 [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
-[0x5f] = "Future Atom (Denverton)",
+[0x5f] = "Atom (Goldmont, Denverton)",
+[0x7a] = "Atom (Goldmont Plus)",
 [0x85] = "Future Xeon Phi",
 [0x8e] = "7th gen Core (Kaby Lake)",
 [0x9e] = "7th gen Core (Kaby Lake)",

CVS commit: src/usr.sbin/cpuctl/arch

2017-10-16 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Mon Oct 16 10:10:48 UTC 2017

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
- Print ci_feat_val[5] (Structured Extended Feature leaf Fn_0007 %ebx) on
  AMD, too.
- Print ci_feat_val[6] (Fn_0007 %ecx) on Intel.


To generate a diff of this commit:
cvs rdiff -u -r1.75 -r1.76 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.75 src/usr.sbin/cpuctl/arch/i386.c:1.76
--- src/usr.sbin/cpuctl/arch/i386.c:1.75	Thu Sep  7 06:40:42 2017
+++ src/usr.sbin/cpuctl/arch/i386.c	Mon Oct 16 10:10:48 2017
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.75 2017/09/07 06:40:42 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.76 2017/10/16 10:10:48 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.75 2017/09/07 06:40:42 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.76 2017/10/16 10:10:48 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -1892,7 +1892,12 @@ identifycpu(int fd, const char *cpuname)
 
 	print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK,
 	ci->ci_feat_val[4]);
-
+	if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD))
+		print_bits(cpuname, "features5", CPUID_SEF_FLAGS,
+		ci->ci_feat_val[5]);
+	if (cpu_vendor == CPUVENDOR_INTEL)
+		print_bits(cpuname, "features6", CPUID_SEF_FLAGS1,
+		ci->ci_feat_val[6]);
 	print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[7]);
 	print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS,
 	ci->ci_feat_val[8]);
@@ -1977,8 +1982,6 @@ identifycpu(int fd, const char *cpuname)
 			case 7:
 aprint_verbose("%s: SEF highest subleaf %08x\n",
 cpuname, data[0]);
-print_bits(cpuname, "SEF-main", CPUID_SEF_FLAGS,
-data[1]);
 break;
 #if 0
 			default:

CVS commit: src/usr.sbin/cpuctl/arch

2016-10-10 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Tue Oct 11 04:16:28 UTC 2016

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
Update from the latest Intel SDM:
 - Denverton
 - Future Xeon Phi
 - 7th gen Core (Kaby Lake)


To generate a diff of this commit:
cvs rdiff -u -r1.73 -r1.74 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.73 src/usr.sbin/cpuctl/arch/i386.c:1.74
--- src/usr.sbin/cpuctl/arch/i386.c:1.73	Thu Jul 21 08:37:18 2016
+++ src/usr.sbin/cpuctl/arch/i386.c	Tue Oct 11 04:16:28 2016
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.73 2016/07/21 08:37:18 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.74 2016/10/11 04:16:28 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.73 2016/07/21 08:37:18 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.74 2016/10/11 04:16:28 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -378,9 +378,10 @@ const struct cpu_cpuid_nameclass i386_cp
 [0x5c] = "Next Atom (Goldmont)",
 [0x5d] = "Atom X3-C3000 (Silvermont)",
 [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
-[0x5f] = "Future Atom (Goldmont)",
-[0x8e] = "Future Core",
-[0x9e] = "Future Core",
+[0x5f] = "Future Atom (Denverton)",
+[0x85] = "Future Xeon Phi",
+[0x8e] = "7th gen Core (Kaby Lake)",
+[0x9e] = "7th gen Core (Kaby Lake)",
 			},
 			"Pentium Pro, II or III",	/* Default */
 			NULL,

CVS commit: src/usr.sbin/cpuctl/arch

2016-07-21 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Thu Jul 21 08:37:18 UTC 2016

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
Update processor families from the latest Intel SDM:
- 06_4FH: Add Xeon E7 v4 and Core i7-69xx Extreme Edition
- 06_57H: Xeon Phi [357]200


To generate a diff of this commit:
cvs rdiff -u -r1.72 -r1.73 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.72 src/usr.sbin/cpuctl/arch/i386.c:1.73
--- src/usr.sbin/cpuctl/arch/i386.c:1.72	Wed Apr 27 08:53:28 2016
+++ src/usr.sbin/cpuctl/arch/i386.c	Thu Jul 21 08:37:18 2016
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.72 2016/04/27 08:53:28 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.73 2016/07/21 08:37:18 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.72 2016/04/27 08:53:28 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.73 2016/07/21 08:37:18 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -370,10 +370,10 @@ const struct cpu_cpuid_nameclass i386_cp
 [0x4c] = "Atom X[57]-Z8000 (Airmont)",
 [0x4d] = "Atom C2000",
 [0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
-[0x4f] = "Xeon E5 v4 (Broadwell)",
+[0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme",
 [0x55] = "Future Xeon",
 [0x56] = "Xeon D-1500 (Broadwell)",
-[0x57] = "Next gen Xeon Phi",
+[0x57] = "Xeon Phi [357]200",
 [0x5a] = "Atom E3500",
 [0x5c] = "Next Atom (Goldmont)",
 [0x5d] = "Atom X3-C3000 (Silvermont)",

CVS commit: src/usr.sbin/cpuctl/arch

2016-04-27 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Wed Apr 27 08:53:28 UTC 2016

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
Add some name from the latest Intel SDM.
 - Quark X1000, Xeon E5 v4 and the future processors.


To generate a diff of this commit:
cvs rdiff -u -r1.71 -r1.72 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.71 src/usr.sbin/cpuctl/arch/i386.c:1.72
--- src/usr.sbin/cpuctl/arch/i386.c:1.71	Wed Apr 27 06:58:06 2016
+++ src/usr.sbin/cpuctl/arch/i386.c	Wed Apr 27 08:53:28 2016
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.71 2016/04/27 06:58:06 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.72 2016/04/27 08:53:28 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.71 2016/04/27 06:58:06 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.72 2016/04/27 08:53:28 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -300,7 +300,7 @@ const struct cpu_cpuid_nameclass i386_cp
 "Pentium (P54C)", "Pentium (P24T)",
 "Pentium/MMX", "Pentium", 0,
 "Pentium (P54C)", "Pentium/MMX (Tillamook)",
-0, 0, 0, 0, 0, 0, 0,
+"Quark X1000", 0, 0, 0, 0, 0, 0,
 			},
 			"Pentium",	/* Default */
 			NULL,
@@ -370,12 +370,17 @@ const struct cpu_cpuid_nameclass i386_cp
 [0x4c] = "Atom X[57]-Z8000 (Airmont)",
 [0x4d] = "Atom C2000",
 [0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
-[0x4f] = "Future gen Xeon (Broadwell)",
+[0x4f] = "Xeon E5 v4 (Broadwell)",
+[0x55] = "Future Xeon",
 [0x56] = "Xeon D-1500 (Broadwell)",
 [0x57] = "Next gen Xeon Phi",
 [0x5a] = "Atom E3500",
+[0x5c] = "Next Atom (Goldmont)",
 [0x5d] = "Atom X3-C3000 (Silvermont)",
 [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
+[0x5f] = "Future Atom (Goldmont)",
+[0x8e] = "Future Core",
+[0x9e] = "Future Core",
 			},
 			"Pentium Pro, II or III",	/* Default */
 			NULL,

CVS commit: src/usr.sbin/cpuctl/arch

2016-04-27 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Wed Apr 27 06:58:06 UTC 2016

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
- Add structure extended feature registers into ci_feat_val[]. The locations
  are the same as x86/include/cpu.h. Curreltly those values are not used yet.
- KNF.


To generate a diff of this commit:
cvs rdiff -u -r1.70 -r1.71 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.70 src/usr.sbin/cpuctl/arch/i386.c:1.71
--- src/usr.sbin/cpuctl/arch/i386.c:1.70	Fri Jan  8 02:28:44 2016
+++ src/usr.sbin/cpuctl/arch/i386.c	Wed Apr 27 06:58:06 2016
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.70 2016/01/08 02:28:44 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.71 2016/04/27 06:58:06 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.70 2016/01/08 02:28:44 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.71 2016/04/27 06:58:06 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -98,14 +98,16 @@ struct cpu_info {
 	uint32_t	ci_signature;	 /* X86 cpuid type */
 	uint32_t	ci_family;	 /* from ci_signature */
 	uint32_t	ci_model;	 /* from ci_signature */
-	uint32_t	ci_feat_val[8];	 /* X86 CPUID feature bits
+	uint32_t	ci_feat_val[9];	 /* X86 CPUID feature bits
 	  *	[0] basic features %edx
 	  *	[1] basic features %ecx
 	  *	[2] extended features %edx
 	  *	[3] extended features %ecx
 	  *	[4] VIA padlock features
-	  *	[5] XCR0 bits (d:0 %eax)
-	  *	[6] xsave flags (d:1 %eax)
+	  *	[5] structure ext. feat. %ebx
+	  *	[6] structure ext. feat. %ecx
+	  *	[7] XCR0 bits (d:0 %eax)
+	  *	[8] xsave flags (d:1 %eax)
 	  */
 	uint32_t	ci_cpu_class;	 /* CPU class */
 	uint32_t	ci_brand_id;	 /* Intel brand id */
@@ -163,7 +165,7 @@ static const char * const i386_intel_bra
 	"Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */
 	"Pentium III",  /* Intel (R) Pentium (R) III processor */
 	"",		/* 0x05: Reserved */
-	"Mobile Pentium III", /* Mobile Intel (R) Pentium (R) III processor-M */
+	"Mobile Pentium III",/* Mobile Intel (R) Pentium (R) III processor-M */
 	"Mobile Celeron",   /* Mobile Intel (R) Celeron (R) processor */
 	"Pentium 4",	/* Intel (R) Pentium (R) 4 processor */
 	"Pentium 4",	/* Intel (R) Pentium (R) 4 processor */
@@ -1519,18 +1521,25 @@ cpu_probe_base_features(struct cpu_info 
 		ci->ci_cpu_serial[1] = descs[3];
 	}
 
+	if (ci->ci_cpuid_level < 0x7)
+		return;
+
+	x86_cpuid(7, descs);
+	ci->ci_feat_val[5] = descs[1];
+	ci->ci_feat_val[6] = descs[2];
+
 	if (ci->ci_cpuid_level < 0xd)
 		return;
 
 	/* Get support XCR0 bits */
 	x86_cpuid2(0xd, 0, descs);
-	ci->ci_feat_val[5] = descs[0];	/* Actually 64 bits */
+	ci->ci_feat_val[7] = descs[0];	/* Actually 64 bits */
 	ci->ci_cur_xsave = descs[1];
 	ci->ci_max_xsave = descs[2];
 
 	/* Additional flags (eg xsaveopt support) */
 	x86_cpuid2(0xd, 1, descs);
-	ci->ci_feat_val[6] = descs[0];   /* Actually 64 bits */
+	ci->ci_feat_val[8] = descs[0];   /* Actually 64 bits */
 }
 
 static void
@@ -1878,9 +1887,9 @@ identifycpu(int fd, const char *cpuname)
 	print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK,
 	ci->ci_feat_val[4]);
 
-	print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[5]);
+	print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[7]);
 	print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS,
-	ci->ci_feat_val[6]);
+	ci->ci_feat_val[8]);
 
 	if (ci->ci_max_xsave != 0) {
 		aprint_normal("%s: xsave area size: current %d, maximum %d",
@@ -1902,9 +1911,8 @@ identifycpu(int fd, const char *cpuname)
 		ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536);
 	}
 
-	if (ci->ci_cpu_class == CPUCLASS_386) {
+	if (ci->ci_cpu_class == CPUCLASS_386)
 		errx(1, "NetBSD requires an 80486 or later processor");
-	}
 
 	if (ci->ci_cpu_type == CPU_486DLC) {
 #ifndef CYRIX_CACHE_WORKS

CVS commit: src/usr.sbin/cpuctl/arch

2016-01-07 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Fri Jan  8 02:28:44 UTC 2016

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
>From the latest Intel SDM:
- Add Xeon E3-1200 v5
- Change 0x1c from "Atom Family" to "45nm Atom Family"


To generate a diff of this commit:
cvs rdiff -u -r1.69 -r1.70 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.69 src/usr.sbin/cpuctl/arch/i386.c:1.70
--- src/usr.sbin/cpuctl/arch/i386.c:1.69	Fri Dec  4 05:34:59 2015
+++ src/usr.sbin/cpuctl/arch/i386.c	Fri Jan  8 02:28:44 2016
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.69 2015/12/04 05:34:59 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.70 2016/01/08 02:28:44 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.69 2015/12/04 05:34:59 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.70 2016/01/08 02:28:44 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -333,7 +333,7 @@ const struct cpu_cpuid_nameclass i386_cp
 	 "Core 2 Quad 8xxx and 9xxx",
 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx "
 	 "(Nehalem)",
-[0x1c] = "Atom Family",
+[0x1c] = "45nm Atom Family",
 [0x1d] = "XeonMP 74xx (Nehalem)",
 [0x1e] = "Core i7 and i5",
 [0x1f] = "Core i7 and i5",
@@ -367,13 +367,13 @@ const struct cpu_cpuid_nameclass i386_cp
 [0x4a] = "Atom Z3400",
 [0x4c] = "Atom X[57]-Z8000 (Airmont)",
 [0x4d] = "Atom C2000",
-[0x4e] = "6th gen Core, Xeon E3-1500 v5 (Skylake)",
+[0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
 [0x4f] = "Future gen Xeon (Broadwell)",
 [0x56] = "Xeon D-1500 (Broadwell)",
 [0x57] = "Next gen Xeon Phi",
 [0x5a] = "Atom E3500",
 [0x5d] = "Atom X3-C3000 (Silvermont)",
-[0x5e] = "6th gen Core, Xeon E3-1500 v5 (Skylake)",
+[0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
 			},
 			"Pentium Pro, II or III",	/* Default */
 			NULL,

CVS commit: src/usr.sbin/cpuctl/arch

2015-12-03 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Fri Dec  4 05:34:59 UTC 2015

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
 Model 0x5e is also 6th gen Core or Xeon E3-1500 v5 like model 0x4e.


To generate a diff of this commit:
cvs rdiff -u -r1.68 -r1.69 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.68 src/usr.sbin/cpuctl/arch/i386.c:1.69
--- src/usr.sbin/cpuctl/arch/i386.c:1.68	Mon Oct 19 02:47:05 2015
+++ src/usr.sbin/cpuctl/arch/i386.c	Fri Dec  4 05:34:59 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.68 2015/10/19 02:47:05 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.69 2015/12/04 05:34:59 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.68 2015/10/19 02:47:05 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.69 2015/12/04 05:34:59 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -373,7 +373,7 @@ const struct cpu_cpuid_nameclass i386_cp
 [0x57] = "Next gen Xeon Phi",
 [0x5a] = "Atom E3500",
 [0x5d] = "Atom X3-C3000 (Silvermont)",
-[0x5e] = "Next gen Core (Skylake)",
+[0x5e] = "6th gen Core, Xeon E3-1500 v5 (Skylake)",
 			},
 			"Pentium Pro, II or III",	/* Default */
 			NULL,

CVS commit: src/usr.sbin/cpuctl/arch

2015-10-18 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Mon Oct 19 02:47:05 UTC 2015

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
 Add 6th gen Core, Xeon E3-1500 v5 and Xeon D-1500 from the latest Intel SDM.


To generate a diff of this commit:
cvs rdiff -u -r1.67 -r1.68 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.67 src/usr.sbin/cpuctl/arch/i386.c:1.68
--- src/usr.sbin/cpuctl/arch/i386.c:1.67	Wed Jul  1 15:46:26 2015
+++ src/usr.sbin/cpuctl/arch/i386.c	Mon Oct 19 02:47:05 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.67 2015/07/01 15:46:26 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.68 2015/10/19 02:47:05 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include 
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.67 2015/07/01 15:46:26 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.68 2015/10/19 02:47:05 msaitoh Exp $");
 #endif /* not lint */
 
 #include 
@@ -367,9 +367,9 @@ const struct cpu_cpuid_nameclass i386_cp
 [0x4a] = "Atom Z3400",
 [0x4c] = "Atom X[57]-Z8000 (Airmont)",
 [0x4d] = "Atom C2000",
-[0x4e] = "Next gen Core (Skylake)",
+[0x4e] = "6th gen Core, Xeon E3-1500 v5 (Skylake)",
 [0x4f] = "Future gen Xeon (Broadwell)",
-[0x56] = "Next gen Xeon D (Broadwell)",
+[0x56] = "Xeon D-1500 (Broadwell)",
 [0x57] = "Next gen Xeon Phi",
 [0x5a] = "Atom E3500",
 [0x5d] = "Atom X3-C3000 (Silvermont)",

CVS commit: src/usr.sbin/cpuctl/arch

2015-07-01 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Wed Jul  1 15:46:26 UTC 2015

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
 Add Xeon E5-4600 v3,  Xeon E3-1200 v4 etc. from the latest Intel SDM.


To generate a diff of this commit:
cvs rdiff -u -r1.66 -r1.67 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.66 src/usr.sbin/cpuctl/arch/i386.c:1.67
--- src/usr.sbin/cpuctl/arch/i386.c:1.66	Fri May  8 07:29:08 2015
+++ src/usr.sbin/cpuctl/arch/i386.c	Wed Jul  1 15:46:26 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.66 2015/05/08 07:29:08 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.67 2015/07/01 15:46:26 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.66 2015/05/08 07:29:08 msaitoh Exp $);
+__RCSID($NetBSD: i386.c,v 1.67 2015/07/01 15:46:26 msaitoh Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -354,26 +354,26 @@ const struct cpu_cpuid_nameclass i386_cp
 	 Ivy Bridge,
 [0x3c] = 4th gen Core, Xeon E3-12xx v3 
 	 (Haswell),
-[0x3d] = Core M-5xxx, Future 5th gen Core (Broadwell),
+[0x3d] = Core M-5xxx, 5th gen Core (Broadwell),
 [0x3e] = Xeon E5/E7 v2 (Ivy Bridge-E), 
 	 Core i7-49xx Extreme,
-[0x3f] = Xeon E5-2600/1600 v3 (Haswell-E), 
+[0x3f] = Xeon E5-4600/2600/1600 v3, Xeon E7 v3 (Haswell-E), 
 	 Core i7-59xx Extreme,
 [0x45] = 4th gen Core, Xeon E3-12xx v3 
 	 (Haswell),
 [0x46] = 4th gen Core, Xeon E3-12xx v3 
 	 (Haswell),
-[0x47] = 5th gen Core (Broadwell),
+[0x47] = 5th gen Core, Xeon E3-1200 v4 (Broadwell),
 [0x4a] = Atom Z3400,
 [0x4c] = Atom X[57]-Z8000 (Airmont),
 [0x4d] = Atom C2000,
-[0x4e] = Next gen Core (Sky Lake),
+[0x4e] = Next gen Core (Skylake),
 [0x4f] = Future gen Xeon (Broadwell),
 [0x56] = Next gen Xeon D (Broadwell),
 [0x57] = Next gen Xeon Phi,
 [0x5a] = Atom E3500,
 [0x5d] = Atom X3-C3000 (Silvermont),
-[0x5e] = Next gen Core (Sky Lake),
+[0x5e] = Next gen Core (Skylake),
 			},
 			Pentium Pro, II or III,	/* Default */
 			NULL,

CVS commit: src/usr.sbin/cpuctl/arch

2015-05-08 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Fri May  8 07:29:08 UTC 2015

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
Update some Intel CPU models (Sky Lake, Broadwell and Atom X[357]).


To generate a diff of this commit:
cvs rdiff -u -r1.65 -r1.66 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.65 src/usr.sbin/cpuctl/arch/i386.c:1.66
--- src/usr.sbin/cpuctl/arch/i386.c:1.65	Fri Mar 27 05:31:34 2015
+++ src/usr.sbin/cpuctl/arch/i386.c	Fri May  8 07:29:08 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.65 2015/03/27 05:31:34 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.66 2015/05/08 07:29:08 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.65 2015/03/27 05:31:34 msaitoh Exp $);
+__RCSID($NetBSD: i386.c,v 1.66 2015/05/08 07:29:08 msaitoh Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -363,15 +363,17 @@ const struct cpu_cpuid_nameclass i386_cp
 	 (Haswell),
 [0x46] = 4th gen Core, Xeon E3-12xx v3 
 	 (Haswell),
+[0x47] = 5th gen Core (Broadwell),
 [0x4a] = Atom Z3400,
-[0x4c] = Atom Z8000,
+[0x4c] = Atom X[57]-Z8000 (Airmont),
 [0x4d] = Atom C2000,
-[0x4e] = Future gen Core,
+[0x4e] = Next gen Core (Sky Lake),
 [0x4f] = Future gen Xeon (Broadwell),
 [0x56] = Next gen Xeon D (Broadwell),
 [0x57] = Next gen Xeon Phi,
 [0x5a] = Atom E3500,
-[0x5d] = Future Atom (Silvermont),
+[0x5d] = Atom X3-C3000 (Silvermont),
+[0x5e] = Next gen Core (Sky Lake),
 			},
 			Pentium Pro, II or III,	/* Default */
 			NULL,

CVS commit: src/usr.sbin/cpuctl/arch

2015-03-26 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Fri Mar 27 05:31:35 UTC 2015

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
Update from Intel SDM:
- Add Atom Z8000, Future gen Xeon (Broadwell), Next gen Xeon Phi and so on.
- Add comments.


To generate a diff of this commit:
cvs rdiff -u -r1.64 -r1.65 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.64 src/usr.sbin/cpuctl/arch/i386.c:1.65
--- src/usr.sbin/cpuctl/arch/i386.c:1.64	Thu Dec 11 12:21:44 2014
+++ src/usr.sbin/cpuctl/arch/i386.c	Fri Mar 27 05:31:34 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.64 2014/12/11 12:21:44 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.65 2015/03/27 05:31:34 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.64 2014/12/11 12:21:44 msaitoh Exp $);
+__RCSID($NetBSD: i386.c,v 1.65 2015/03/27 05:31:34 msaitoh Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -349,12 +349,12 @@ const struct cpu_cpuid_nameclass i386_cp
 [0x2f] = Xeon E7 family,
 [0x35] = Atom Family,
 [0x36] = Atom S1000,
-[0x37] = Atom E3000, Z3000,
+[0x37] = Atom E3000, Z3[67]00,
 [0x3a] = Xeon E3-1200v2 and 3rd gen core, 
 	 Ivy Bridge,
 [0x3c] = 4th gen Core, Xeon E3-12xx v3 
 	 (Haswell),
-[0x3d] = Core M-5xxx (Broadwell),
+[0x3d] = Core M-5xxx, Future 5th gen Core (Broadwell),
 [0x3e] = Xeon E5/E7 v2 (Ivy Bridge-E), 
 	 Core i7-49xx Extreme,
 [0x3f] = Xeon E5-2600/1600 v3 (Haswell-E), 
@@ -363,12 +363,15 @@ const struct cpu_cpuid_nameclass i386_cp
 	 (Haswell),
 [0x46] = 4th gen Core, Xeon E3-12xx v3 
 	 (Haswell),
-[0x4a] = Future Atom E3000, Z3000,
+[0x4a] = Atom Z3400,
+[0x4c] = Atom Z8000,
 [0x4d] = Atom C2000,
-[0x4e] = Future Core,
-[0x56] = Future Xeon,
-[0x5a] = Future Atom E3000, Z3000,
-[0x5d] = Future Atom E3000, Z3000,
+[0x4e] = Future gen Core,
+[0x4f] = Future gen Xeon (Broadwell),
+[0x56] = Next gen Xeon D (Broadwell),
+[0x57] = Next gen Xeon Phi,
+[0x5a] = Atom E3500,
+[0x5d] = Future Atom (Silvermont),
 			},
 			Pentium Pro, II or III,	/* Default */
 			NULL,
@@ -996,6 +999,11 @@ intel_cpu_cacheinfo(struct cpu_info *ci)
 			if (descs[i]  0x8000)
 continue;
 			for (j = 0; j  4; j++) {
+/*
+ * The least significant byte in EAX
+ * ((desc[0]  0)  0xff) is always 0x01 and
+ * it should be ignored.
+ */
 if (i == 0  j == 0)
 	continue;
 desc = (descs[i]  (j * 8))  0xff;

CVS commit: src/usr.sbin/cpuctl/arch

2015-03-01 Thread Tobias Nygren

Module Name:src
Committed By:   tnn
Date:   Sun Mar  1 18:02:42 UTC 2015

Modified Files:
src/usr.sbin/cpuctl/arch: i386-asm.S x86_64-asm.S

Log Message:
xgetbv expects XCR0 to be speficied in %ecx, don't leave %ecx undefined


To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/usr.sbin/cpuctl/arch/i386-asm.S
cvs rdiff -u -r1.4 -r1.5 src/usr.sbin/cpuctl/arch/x86_64-asm.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386-asm.S
diff -u src/usr.sbin/cpuctl/arch/i386-asm.S:1.3 src/usr.sbin/cpuctl/arch/i386-asm.S:1.4
--- src/usr.sbin/cpuctl/arch/i386-asm.S:1.3	Mon Jan  7 23:20:42 2013
+++ src/usr.sbin/cpuctl/arch/i386-asm.S	Sun Mar  1 18:02:42 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386-asm.S,v 1.3 2013/01/07 23:20:42 dsl Exp $	*/
+/*	$NetBSD: i386-asm.S,v 1.4 2015/03/01 18:02:42 tnn Exp $	*/
 
 /*-
  * Copyright (c) 1998, 2000, 2004, 2006, 2007 The NetBSD Foundation, Inc.
@@ -49,6 +49,7 @@ ENTRY(x86_cpuid2)
 END(x86_cpuid2)
 
 ENTRY(x86_xgetbv)
+	xorl	%ecx, %ecx
 	xgetbv
 	ret
 END(x86_xgetbv)

Index: src/usr.sbin/cpuctl/arch/x86_64-asm.S
diff -u src/usr.sbin/cpuctl/arch/x86_64-asm.S:1.4 src/usr.sbin/cpuctl/arch/x86_64-asm.S:1.5
--- src/usr.sbin/cpuctl/arch/x86_64-asm.S:1.4	Mon Jan  7 23:20:42 2013
+++ src/usr.sbin/cpuctl/arch/x86_64-asm.S	Sun Mar  1 18:02:42 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: x86_64-asm.S,v 1.4 2013/01/07 23:20:42 dsl Exp $	*/
+/*	$NetBSD: x86_64-asm.S,v 1.5 2015/03/01 18:02:42 tnn Exp $	*/
 
 /*-
  * Copyright (c) 2007 The NetBSD Foundation, Inc.
@@ -44,6 +44,7 @@ ENTRY(x86_cpuid2)
 	ret
 
 ENTRY(x86_xgetbv)
+	xorl	%ecx, %ecx
 	xgetbv
 	ret

CVS commit: src/usr.sbin/cpuctl/arch

2014-12-11 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Thu Dec 11 10:07:45 UTC 2014

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
Add newline if ci_tsc_freq is 0 to not to break the output.


To generate a diff of this commit:
cvs rdiff -u -r1.62 -r1.63 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.62 src/usr.sbin/cpuctl/arch/i386.c:1.63
--- src/usr.sbin/cpuctl/arch/i386.c:1.62	Thu Nov 20 10:31:10 2014
+++ src/usr.sbin/cpuctl/arch/i386.c	Thu Dec 11 10:07:45 2014
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.62 2014/11/20 10:31:10 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.63 2014/12/11 10:07:45 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.62 2014/11/20 10:31:10 msaitoh Exp $);
+__RCSID($NetBSD: i386.c,v 1.63 2014/12/11 10:07:45 msaitoh Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -1836,9 +1836,10 @@ identifycpu(int fd, const char *cpuname)
 	aprint_normal( (%s-class), classnames[class]);
 
 	if (ci-ci_tsc_freq != 0)
-		aprint_normal(, %ju.%02ju MHz\n,
+		aprint_normal(, %ju.%02ju MHz,
 		((uintmax_t)ci-ci_tsc_freq + 4999) / 100,
 		(((uintmax_t)ci-ci_tsc_freq + 4999) / 1) % 100);
+	aprint_normal(\n);
 
 	aprint_normal_dev(ci-ci_dev, family %#x model %#x stepping %#x,
 	ci-ci_family, ci-ci_model, CPUID_TO_STEPPING(ci-ci_signature));

CVS commit: src/usr.sbin/cpuctl/arch

2014-12-11 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Thu Dec 11 12:21:44 UTC 2014

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
 Don't print the microcode version if the ioctl failed to not to
print garbage.


To generate a diff of this commit:
cvs rdiff -u -r1.63 -r1.64 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.63 src/usr.sbin/cpuctl/arch/i386.c:1.64
--- src/usr.sbin/cpuctl/arch/i386.c:1.63	Thu Dec 11 10:07:45 2014
+++ src/usr.sbin/cpuctl/arch/i386.c	Thu Dec 11 12:21:44 2014
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.63 2014/12/11 10:07:45 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.64 2014/12/11 12:21:44 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.63 2014/12/11 10:07:45 msaitoh Exp $);
+__RCSID($NetBSD: i386.c,v 1.64 2014/12/11 12:21:44 msaitoh Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -1995,6 +1995,8 @@ identifycpu(int fd, const char *cpuname)
 		ucode_64.loader_version = ucode.loader_version;
 		if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, ucode_64)  0)
 			return;
+#else
+		return;
 #endif
 	}

CVS commit: src/usr.sbin/cpuctl/arch

2014-11-20 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Thu Nov 20 10:31:10 UTC 2014

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
 Move some printf()s from cpu_probe_base_features() to identifycpu().
Those printf()s are used for identify command but cpu_probe_base_features()
is shared by ucodeupdate_check(), too. This change fixes a problem that
the ucode command print extra output.


To generate a diff of this commit:
cvs rdiff -u -r1.61 -r1.62 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.61 src/usr.sbin/cpuctl/arch/i386.c:1.62
--- src/usr.sbin/cpuctl/arch/i386.c:1.61	Tue Nov 11 08:23:17 2014
+++ src/usr.sbin/cpuctl/arch/i386.c	Thu Nov 20 10:31:10 2014
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.61 2014/11/11 08:23:17 skrll Exp $	*/
+/*	$NetBSD: i386.c,v 1.62 2014/11/20 10:31:10 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.61 2014/11/11 08:23:17 skrll Exp $);
+__RCSID($NetBSD: i386.c,v 1.62 2014/11/20 10:31:10 msaitoh Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -1444,40 +1444,17 @@ cpu_probe_base_features(struct cpu_info 
 	ci-ci_vendor[1] = descs[3];
 	ci-ci_vendor[3] = 0;
 
-	aprint_verbose(%s: highest basic info %08x\n, cpuname,
-	ci-ci_cpuid_level);
-	if (verbose) {
-		int bf;
-		
-		for (bf = 0; bf = ci-ci_cpuid_level; bf++) {
-			x86_cpuid(bf, descs);
-			printf(%s: %08x: %08x %08x %08x %08x\n, cpuname,
-			bf, descs[0], descs[1], descs[2], descs[3]);
-		}
-	}
-
 	/*
 	 * Fn8000_:
 	 * - Get cpuid extended function's max level.
 	 */
 	x86_cpuid(0x8000, descs);
-	if (descs[0] =  0x8000) {
+	if (descs[0] = 0x8000)
 		ci-ci_cpuid_extlevel = descs[0];
-		aprint_verbose(%s: highest extended info %08x\n, cpuname,
-		ci-ci_cpuid_extlevel);
-	} else {
+	else {
 		/* Set lower value than 0x8000 */
 		ci-ci_cpuid_extlevel = 0;
 	}
-	if (verbose) {
-		unsigned int ef;
-
-		for (ef = 0x8000; ef = ci-ci_cpuid_extlevel; ef++) {
-			x86_cpuid(ef, descs);
-			printf(%s: %08x: %08x %08x %08x %08x\n, cpuname,
-			ef, descs[0], descs[1], descs[2], descs[3]);
-		}
-	}
 
 	/*
 	 * Fn8000_000[2-4]:
@@ -1706,6 +1683,7 @@ identifycpu(int fd, const char *cpuname)
 	const struct cpu_cpuid_nameclass *cpup = NULL;
 	const struct cpu_cpuid_family *cpufam;
 	struct cpu_info *ci, cistore;
+	u_int descs[4];
 	size_t sz;
 	struct cpu_ucode_version ucode;
 	union {
@@ -1715,6 +1693,30 @@ identifycpu(int fd, const char *cpuname)
 
 	ci = cistore;
 	cpu_probe_base_features(ci, cpuname);
+	aprint_verbose(%s: highest basic info %08x\n, cpuname,
+	ci-ci_cpuid_level);
+	if (verbose) {
+		int bf;
+		
+		for (bf = 0; bf = ci-ci_cpuid_level; bf++) {
+			x86_cpuid(bf, descs);
+			printf(%s: %08x: %08x %08x %08x %08x\n, cpuname,
+			bf, descs[0], descs[1], descs[2], descs[3]);
+		}
+	}
+	if (ci-ci_cpuid_extlevel =  0x8000)
+		aprint_verbose(%s: highest extended info %08x\n, cpuname,
+		ci-ci_cpuid_extlevel);
+	if (verbose) {
+		unsigned int ef;
+
+		for (ef = 0x8000; ef = ci-ci_cpuid_extlevel; ef++) {
+			x86_cpuid(ef, descs);
+			printf(%s: %08x: %08x %08x %08x %08x\n, cpuname,
+			ef, descs[0], descs[1], descs[2], descs[3]);
+		}
+	}
+
 	cpu_probe_hv_features(ci, cpuname);
 	cpu_probe_features(ci);

CVS commit: src/usr.sbin/cpuctl/arch

2014-11-11 Thread Nick Hudson

Module Name:src
Committed By:   skrll
Date:   Tue Nov 11 08:23:17 UTC 2014

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
kern/49379: Hypervisor's name typo


To generate a diff of this commit:
cvs rdiff -u -r1.60 -r1.61 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.60 src/usr.sbin/cpuctl/arch/i386.c:1.61
--- src/usr.sbin/cpuctl/arch/i386.c:1.60	Fri Nov  7 05:37:05 2014
+++ src/usr.sbin/cpuctl/arch/i386.c	Tue Nov 11 08:23:17 2014
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.60 2014/11/07 05:37:05 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.61 2014/11/11 08:23:17 skrll Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.60 2014/11/07 05:37:05 msaitoh Exp $);
+__RCSID($NetBSD: i386.c,v 1.61 2014/11/11 08:23:17 skrll Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -1579,7 +1579,7 @@ cpu_probe_hv_features(struct cpu_info *c
 		if (strncmp(hv_sig, KVMKVMKVM, 9) == 0)
 			hv_name = KVM;
 		else if (strncmp(hv_sig, Microsoft Hv, 12) == 0)
-			hv_name = Hypver-V;
+			hv_name = Hyper-V;
 		else if (strncmp(hv_sig, VMwareVMware, 12) == 0)
 			hv_name = VMware;
 		else if (strncmp(hv_sig, XenVMMXenVMM, 12) == 0)

CVS commit: src/usr.sbin/cpuctl/arch

2014-11-06 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Fri Nov  7 05:37:05 UTC 2014

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
Add code to detect hypervisor. The code was based from FreeBSD and ported
by Kengo Nakahara.


To generate a diff of this commit:
cvs rdiff -u -r1.59 -r1.60 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.59 src/usr.sbin/cpuctl/arch/i386.c:1.60
--- src/usr.sbin/cpuctl/arch/i386.c:1.59	Tue Sep  9 15:14:39 2014
+++ src/usr.sbin/cpuctl/arch/i386.c	Fri Nov  7 05:37:05 2014
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.59 2014/09/09 15:14:39 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.60 2014/11/07 05:37:05 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.59 2014/09/09 15:14:39 msaitoh Exp $);
+__RCSID($NetBSD: i386.c,v 1.60 2014/11/07 05:37:05 msaitoh Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -220,6 +220,7 @@ static void	tmx86_get_longrun_status(u_i
 static void	transmeta_cpu_info(struct cpu_info *);
 /* Common functions */
 static void	cpu_probe_base_features(struct cpu_info *, const char *);
+static void	cpu_probe_hv_features(struct cpu_info *, const char *);
 static void	cpu_probe_features(struct cpu_info *);
 static void	print_bits(const char *, const char *, const char *, uint32_t);
 static void	identifycpu_cpuids(struct cpu_info *);
@@ -1546,6 +1547,51 @@ cpu_probe_base_features(struct cpu_info 
 }
 
 static void
+cpu_probe_hv_features(struct cpu_info *ci, const char *cpuname)
+{
+	uint32_t descs[4];
+	char hv_sig[13];
+	char *p;
+	const char *hv_name;
+	int i;
+
+	/*
+	 * [RFC] CPUID usage for interaction between Hypervisors and Linux.
+	 * http://lkml.org/lkml/2008/10/1/246
+	 *
+	 * KB1009458: Mechanisms to determine if software is running in
+	 * a VMware virtual machine
+	 * http://kb.vmware.com/kb/1009458
+	 */
+	if ((ci-ci_feat_val[1]  CPUID2_RAZ) != 0) {
+		x86_cpuid(0x4000, descs);
+		for (i = 1, p = hv_sig; i  4; i++, p += sizeof(descs) / 4)
+			memcpy(p, descs[i], sizeof(descs[i]));
+		*p = '\0';
+		/*
+		 * HV vendor	ID string
+		 * +--
+		 * KVM		KVMKVMKVM
+		 * Microsoft	Microsoft Hv
+		 * VMware	VMwareVMware
+		 * Xen		XenVMMXenVMM
+		 */
+		if (strncmp(hv_sig, KVMKVMKVM, 9) == 0)
+			hv_name = KVM;
+		else if (strncmp(hv_sig, Microsoft Hv, 12) == 0)
+			hv_name = Hypver-V;
+		else if (strncmp(hv_sig, VMwareVMware, 12) == 0)
+			hv_name = VMware;
+		else if (strncmp(hv_sig, XenVMMXenVMM, 12) == 0)
+			hv_name = Xen;
+		else
+			hv_name = unknown;
+
+		printf(%s: Running on hypervisor: %s\n, cpuname, hv_name);
+	}
+}
+
+static void
 cpu_probe_features(struct cpu_info *ci)
 {
 	const struct cpu_cpuid_nameclass *cpup = NULL;
@@ -1669,6 +1715,7 @@ identifycpu(int fd, const char *cpuname)
 
 	ci = cistore;
 	cpu_probe_base_features(ci, cpuname);
+	cpu_probe_hv_features(ci, cpuname);
 	cpu_probe_features(ci);
 
 	if (ci-ci_cpu_type = 0) {

CVS commit: src/usr.sbin/cpuctl/arch

2014-09-09 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Tue Sep  9 15:14:39 UTC 2014

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
Update CPUID signature values from the latest Intel SDM.
- Core M-5xxx
- Core i7 extreme
- Future Core (0x4e)
- Future Xeon (0x56)


To generate a diff of this commit:
cvs rdiff -u -r1.58 -r1.59 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.58 src/usr.sbin/cpuctl/arch/i386.c:1.59
--- src/usr.sbin/cpuctl/arch/i386.c:1.58	Fri Jul 25 14:18:49 2014
+++ src/usr.sbin/cpuctl/arch/i386.c	Tue Sep  9 15:14:39 2014
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.58 2014/07/25 14:18:49 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.59 2014/09/09 15:14:39 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.58 2014/07/25 14:18:49 msaitoh Exp $);
+__RCSID($NetBSD: i386.c,v 1.59 2014/09/09 15:14:39 msaitoh Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -353,15 +353,19 @@ const struct cpu_cpuid_nameclass i386_cp
 	 Ivy Bridge,
 [0x3c] = 4th gen Core, Xeon E3-12xx v3 
 	 (Haswell),
-[0x3d] = Core M based on Broadwell,
-[0x3e] = Xeon E5/E7, Ivy Bridge-EP,
-[0x3f] = Next gen Xeon based on Haswell,
+[0x3d] = Core M-5xxx (Broadwell),
+[0x3e] = Xeon E5/E7 v2 (Ivy Bridge-E), 
+	 Core i7-49xx Extreme,
+[0x3f] = Xeon E5-2600/1600 v3 (Haswell-E), 
+	 Core i7-59xx Extreme,
 [0x45] = 4th gen Core, Xeon E3-12xx v3 
 	 (Haswell),
 [0x46] = 4th gen Core, Xeon E3-12xx v3 
 	 (Haswell),
 [0x4a] = Future Atom E3000, Z3000,
 [0x4d] = Atom C2000,
+[0x4e] = Future Core,
+[0x56] = Future Xeon,
 [0x5a] = Future Atom E3000, Z3000,
 [0x5d] = Future Atom E3000, Z3000,
 			},

CVS commit: src/usr.sbin/cpuctl/arch

2014-07-25 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Fri Jul 25 13:52:26 UTC 2014

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
Update table for processor families and processor number series from the
latest Intel SDM.
- Atom Z3000 (0x37)
- Core M based on Broadwell (0x3d)
- Next gen Xeon based on Haswell (0x3f)


To generate a diff of this commit:
cvs rdiff -u -r1.56 -r1.57 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.56 src/usr.sbin/cpuctl/arch/i386.c:1.57
--- src/usr.sbin/cpuctl/arch/i386.c:1.56	Thu Jul  3 04:11:37 2014
+++ src/usr.sbin/cpuctl/arch/i386.c	Fri Jul 25 13:52:26 2014
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.56 2014/07/03 04:11:37 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.57 2014/07/25 13:52:26 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.56 2014/07/03 04:11:37 msaitoh Exp $);
+__RCSID($NetBSD: i386.c,v 1.57 2014/07/25 13:52:26 msaitoh Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -348,14 +348,14 @@ const struct cpu_cpuid_nameclass i386_cp
 [0x2f] = Xeon E7 family,
 [0x35] = Atom Family,
 [0x36] = Atom S1000,
-[0x37] = Atom C2000, E3000,
+[0x37] = Atom E3000, Z3000,
 [0x3a] = Xeon E3-1200v2 and 3rd gen core, 
 	 Ivy Bridge,
 [0x3c] = 4th gen Core, Xeon E3-12xx v3 
 	 (Haswell),
-[0x3d] = Next gen Core,
+[0x3d] = Core M based on Broadwell,
 [0x3e] = Xeon E5/E7, Ivy Bridge-EP,
-[0x3f] = Future gen Xeon,
+[0x3f] = Next gen Xeon based on Haswell,
 [0x45] = 4th gen Core, Xeon E3-12xx v3 
 	 (Haswell),
 [0x46] = 4th gen Core, Xeon E3-12xx v3

CVS commit: src/usr.sbin/cpuctl/arch

2014-07-25 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Fri Jul 25 14:18:49 UTC 2014

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
More update:
- Future Atom E3000, Z3000 (0x4a, 0x5a, 0x5d)
- Atom C2000 (0x4d)


To generate a diff of this commit:
cvs rdiff -u -r1.57 -r1.58 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.57 src/usr.sbin/cpuctl/arch/i386.c:1.58
--- src/usr.sbin/cpuctl/arch/i386.c:1.57	Fri Jul 25 13:52:26 2014
+++ src/usr.sbin/cpuctl/arch/i386.c	Fri Jul 25 14:18:49 2014
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.57 2014/07/25 13:52:26 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.58 2014/07/25 14:18:49 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.57 2014/07/25 13:52:26 msaitoh Exp $);
+__RCSID($NetBSD: i386.c,v 1.58 2014/07/25 14:18:49 msaitoh Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -360,7 +360,10 @@ const struct cpu_cpuid_nameclass i386_cp
 	 (Haswell),
 [0x46] = 4th gen Core, Xeon E3-12xx v3 
 	 (Haswell),
-[0x4d] = Atom C2000, E3000,
+[0x4a] = Future Atom E3000, Z3000,
+[0x4d] = Atom C2000,
+[0x5a] = Future Atom E3000, Z3000,
+[0x5d] = Future Atom E3000, Z3000,
 			},
 			Pentium Pro, II or III,	/* Default */
 			NULL,

CVS commit: src/usr.sbin/cpuctl/arch

2014-07-02 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Thu Jul  3 04:11:37 UTC 2014

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
Exclude descriptor 0xff of CPUID leaf 2. 0xff means the cacheinfo is in leaf 4.


To generate a diff of this commit:
cvs rdiff -u -r1.55 -r1.56 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.55 src/usr.sbin/cpuctl/arch/i386.c:1.56
--- src/usr.sbin/cpuctl/arch/i386.c:1.55	Tue May 27 04:18:00 2014
+++ src/usr.sbin/cpuctl/arch/i386.c	Thu Jul  3 04:11:37 2014
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.55 2014/05/27 04:18:00 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.56 2014/07/03 04:11:37 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.55 2014/05/27 04:18:00 msaitoh Exp $);
+__RCSID($NetBSD: i386.c,v 1.56 2014/07/03 04:11:37 msaitoh Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -997,7 +997,7 @@ intel_cpu_cacheinfo(struct cpu_info *ci)
 desc);
 if (cai != NULL)
 	ci-ci_cinfo[cai-cai_index] = *cai;
-else if (verbose)
+else if ((verbose != 0)  (desc != 0xff))
 	printf(Unknown cacheinfo desc %02x\n,
 	desc);
 			}

CVS commit: src/usr.sbin/cpuctl/arch

2014-05-26 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Tue May 27 04:18:01 UTC 2014

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
If -v is set and unknown cacheinfo desc is found, print it.


To generate a diff of this commit:
cvs rdiff -u -r1.54 -r1.55 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.54 src/usr.sbin/cpuctl/arch/i386.c:1.55
--- src/usr.sbin/cpuctl/arch/i386.c:1.54	Sat Jan  4 18:13:48 2014
+++ src/usr.sbin/cpuctl/arch/i386.c	Tue May 27 04:18:00 2014
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.54 2014/01/04 18:13:48 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.55 2014/05/27 04:18:00 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.54 2014/01/04 18:13:48 msaitoh Exp $);
+__RCSID($NetBSD: i386.c,v 1.55 2014/05/27 04:18:00 msaitoh Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -997,6 +997,9 @@ intel_cpu_cacheinfo(struct cpu_info *ci)
 desc);
 if (cai != NULL)
 	ci-ci_cinfo[cai-cai_index] = *cai;
+else if (verbose)
+	printf(Unknown cacheinfo desc %02x\n,
+	desc);
 			}
 		}
 		x86_cpuid(2, descs);

CVS commit: src/usr.sbin/cpuctl/arch

2014-01-04 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Sat Jan  4 18:13:48 UTC 2014

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
- Rename x86_print_cacheinfo() to x86_print_cache_and_tlb_info() because
  this function prints TLB info, too.
- Remove an extra printf when verbose flag is set.
- Print the highest extended info level as the basic info level.
- Sort function.


To generate a diff of this commit:
cvs rdiff -u -r1.53 -r1.54 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.53 src/usr.sbin/cpuctl/arch/i386.c:1.54
--- src/usr.sbin/cpuctl/arch/i386.c:1.53	Mon Dec 23 12:35:33 2013
+++ src/usr.sbin/cpuctl/arch/i386.c	Sat Jan  4 18:13:48 2014
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.53 2013/12/23 12:35:33 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.54 2014/01/04 18:13:48 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.53 2013/12/23 12:35:33 msaitoh Exp $);
+__RCSID($NetBSD: i386.c,v 1.54 2014/01/04 18:13:48 msaitoh Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -223,13 +223,13 @@ static void	cpu_probe_base_features(stru
 static void	cpu_probe_features(struct cpu_info *);
 static void	print_bits(const char *, const char *, const char *, uint32_t);
 static void	identifycpu_cpuids(struct cpu_info *);
+static const struct x86_cache_info *cache_info_lookup(
+const struct x86_cache_info *, uint8_t);
 static const char *print_cache_config(struct cpu_info *, int, const char *,
 const char *);
 static const char *print_tlb_config(struct cpu_info *, int, const char *,
 const char *);
-static const struct x86_cache_info *cache_info_lookup(
-const struct x86_cache_info *, uint8_t);
-static void	x86_print_cacheinfo(struct cpu_info *);
+static void	x86_print_cache_and_tlb_info(struct cpu_info *);
 
 /*
  * Note: these are just the ones that may not have a cpuid instruction.
@@ -1432,11 +1432,12 @@ cpu_probe_base_features(struct cpu_info 
 	ci-ci_vendor[2] = descs[2];
 	ci-ci_vendor[1] = descs[3];
 	ci-ci_vendor[3] = 0;
+
+	aprint_verbose(%s: highest basic info %08x\n, cpuname,
+	ci-ci_cpuid_level);
 	if (verbose) {
 		int bf;
 		
-		printf(%s: cpuid basic function max = %08x\n, cpuname,
-		descs[0]);
 		for (bf = 0; bf = ci-ci_cpuid_level; bf++) {
 			x86_cpuid(bf, descs);
 			printf(%s: %08x: %08x %08x %08x %08x\n, cpuname,
@@ -1449,17 +1450,17 @@ cpu_probe_base_features(struct cpu_info 
 	 * - Get cpuid extended function's max level.
 	 */
 	x86_cpuid(0x8000, descs);
-	if (descs[0] =  0x8000)
+	if (descs[0] =  0x8000) {
 		ci-ci_cpuid_extlevel = descs[0];
-	else {
+		aprint_verbose(%s: highest extended info %08x\n, cpuname,
+		ci-ci_cpuid_extlevel);
+	} else {
 		/* Set lower value than 0x8000 */
 		ci-ci_cpuid_extlevel = 0;
 	}
 	if (verbose) {
 		unsigned int ef;
 
-		printf(%s: cpuid extended function max = %08x\n, cpuname,
-		descs[0]);
 		for (ef = 0x8000; ef = ci-ci_cpuid_extlevel; ef++) {
 			x86_cpuid(ef, descs);
 			printf(%s: %08x: %08x %08x %08x %08x\n, cpuname,
@@ -1594,7 +1595,6 @@ identifycpu_cpuids(struct cpu_info *ci)
 	u_int core_max = 1;	/* core per package */
 	u_int smt_bits, core_bits;
 	uint32_t descs[4];
-	uint32_t highest_basic_info;
 
 	aprint_verbose(%s: Initial APIC ID %u\n, cpuname, ci-ci_initapicid);
 	ci-ci_packageid = ci-ci_initapicid;
@@ -1612,9 +1612,7 @@ identifycpu_cpuids(struct cpu_info *ci)
 		x86_cpuid(1, descs);
 		lp_max = (descs[1]  16)  0xff;
 	}
-	x86_cpuid(0, descs);
-	highest_basic_info = descs[0];
-	if (highest_basic_info = 4) {
+	if (ci-ci_cpuid_level = 4) {
 		x86_cpuid2(4, 0, descs);
 		core_max = (descs[0]  26) + 1;
 	}
@@ -1824,7 +1822,7 @@ identifycpu(int fd, const char *cpuname)
 			x86_xgetbv());
 	}
 
-	x86_print_cacheinfo(ci);
+	x86_print_cache_and_tlb_info(ci);
 
 	if (ci-ci_cpuid_level = 3  (ci-ci_feat_val[0]  CPUID_PN)) {
 		aprint_verbose(%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n,
@@ -1881,14 +1879,9 @@ identifycpu(int fd, const char *cpuname)
 		}
 	} else if (cpu_vendor == CPUVENDOR_INTEL) {
 		uint32_t data[4];
-		uint32_t highest_basic_info;
-		uint32_t bi_index;
+		int32_t bi_index;
 
-		x86_cpuid(0x, data);
-		highest_basic_info = data[0];
-		aprint_verbose(%s: highest basic info %08x\n, cpuname,
-		highest_basic_info);
-		for (bi_index = 1; bi_index = highest_basic_info; bi_index++) {
+		for (bi_index = 1; bi_index = ci-ci_cpuid_level; bi_index++) {
 			x86_cpuid(bi_index, data);
 			switch (bi_index) {
 			case 6:
@@ -1952,6 +1945,19 @@ identifycpu(int fd, const char *cpuname)
 		   ucvers.intel1.ucodeversion, ucvers.intel1.platformid);
 }
 
+static const struct x86_cache_info *

CVS commit: src/usr.sbin/cpuctl/arch

2013-12-23 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Mon Dec 23 10:13:59 UTC 2013

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
Add comments. Remove comments. No functional change.


To generate a diff of this commit:
cvs rdiff -u -r1.50 -r1.51 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.50 src/usr.sbin/cpuctl/arch/i386.c:1.51
--- src/usr.sbin/cpuctl/arch/i386.c:1.50	Fri Nov 15 08:47:55 2013
+++ src/usr.sbin/cpuctl/arch/i386.c	Mon Dec 23 10:13:59 2013
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.50 2013/11/15 08:47:55 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.51 2013/12/23 10:13:59 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.50 2013/11/15 08:47:55 msaitoh Exp $);
+__RCSID($NetBSD: i386.c,v 1.51 2013/12/23 10:13:59 msaitoh Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -200,7 +200,7 @@ static int use_pae, largepagesize;
 
 /* Setup functions */
 static void	disable_tsc(struct cpu_info *);
-static void	amd_family5_setup(struct cpu_info *); /* alike cpu_probe_k5 */
+static void	amd_family5_setup(struct cpu_info *);
 static void	cyrix6x86_cpu_setup(struct cpu_info *);
 static void	winchip_cpu_setup(struct cpu_info *);
 /* Brand/Model name functions */
@@ -212,22 +212,20 @@ static void	powernow_probe(struct cpu_in
 static void	intel_family_new_probe(struct cpu_info *);
 static void	via_cpu_probe(struct cpu_info *);
 /* (Cache) Info functions */
-static void 	amd_cpu_cacheinfo(struct cpu_info *); /* alike */
+static void 	amd_cpu_cacheinfo(struct cpu_info *);
 static void	via_cpu_cacheinfo(struct cpu_info *);
 static void	tmx86_get_longrun_status(u_int *, u_int *, u_int *);
 static void	transmeta_cpu_info(struct cpu_info *);
 /* Common functions */
 static void	cpu_probe_base_features(struct cpu_info *, const char *);
-	/* alike cpu_probe() */
 static void	cpu_probe_features(struct cpu_info *);
 static void	print_bits(const char *, const char *, const char *, uint32_t);
-/* XXX identifycpu alike cpu_identify */
 static void	identifycpu_cpuids(struct cpu_info *);
 static const char *print_cache_config(struct cpu_info *, int, const char *,
 const char *);
 static const char *print_tlb_config(struct cpu_info *, int, const char *,
 const char *);
-static const struct x86_cache_info *cache_info_lookup( /* XXX same */
+static const struct x86_cache_info *cache_info_lookup(
 const struct x86_cache_info *, uint8_t);
 static void	x86_print_cacheinfo(struct cpu_info *);
 
@@ -1324,13 +1322,28 @@ cpu_probe_base_features(struct cpu_info 
 		return;
 	}
 
+	/*
+	 * This CPU supports cpuid instruction, so we can call x86_cpuid()
+	 * function.
+	 */
+
+	/*
+	 * Fn_:
+	 * - Save cpuid max level.
+	 * - Save vendor string.
+	 */
 	x86_cpuid(0, descs);
 	ci-ci_cpuid_level = descs[0];
+	/* Save vendor string */
 	ci-ci_vendor[0] = descs[1];
 	ci-ci_vendor[2] = descs[2];
 	ci-ci_vendor[1] = descs[3];
 	ci-ci_vendor[3] = 0;
 
+	/*
+	 * Fn8000_000[2-4]:
+	 * - Save brand string.
+	 */
 	x86_cpuid(0x8000, brand);
 	if (brand[0] = 0x8004) {
 		x86_cpuid(0x8002, brand);
@@ -1345,6 +1358,11 @@ cpu_probe_base_features(struct cpu_info 
 	if (ci-ci_cpuid_level  1)
 		return;
 
+	/*
+	 * Fn_0001:
+	 * - Get CPU family, model and stepping (from eax).
+	 * - Initial local APIC ID and brand ID (from ebx)
+	 */
 	x86_cpuid(1, descs);
 	ci-ci_signature = descs[0];
 
@@ -1354,6 +1372,7 @@ cpu_probe_base_features(struct cpu_info 
 
 	/* Brand is low order 8 bits of ebx */
 	ci-ci_brand_id = descs[1]  0xff;
+	/* Initial local APIC ID */
 	ci-ci_initapicid = (descs[1]  24)  0xff;
 
 	ci-ci_feat_val[1] = descs[2];
@@ -1599,6 +1618,7 @@ identifycpu(int fd, const char *cpuname)
 	cpu_probe_features(ci);
 
 	if (ci-ci_cpu_type = 0) {
+		/* Old pre-cpuid instruction cpu */
 		if (ci-ci_cpu_type = (int)__arraycount(i386_nocpuid_cpus))
 			errx(1, unknown cpu type %d, ci-ci_cpu_type);
 		name = i386_nocpuid_cpus[ci-ci_cpu_type].cpu_name;
@@ -1608,6 +1628,7 @@ identifycpu(int fd, const char *cpuname)
 		ci-ci_info = i386_nocpuid_cpus[ci-ci_cpu_type].cpu_info;
 		modifier = ;
 	} else {
+		/* CPU which support cpuid instruction */
 		modif = (ci-ci_signature  12)  0x3;
 		family = ci-ci_family;
 		if (family  CPU_MINFAMILY)

CVS commit: src/usr.sbin/cpuctl/arch

2013-12-23 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Mon Dec 23 11:17:20 UTC 2013

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
CPUID leaf 2 and 4 are only for Intel processors.


To generate a diff of this commit:
cvs rdiff -u -r1.51 -r1.52 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.51 src/usr.sbin/cpuctl/arch/i386.c:1.52
--- src/usr.sbin/cpuctl/arch/i386.c:1.51	Mon Dec 23 10:13:59 2013
+++ src/usr.sbin/cpuctl/arch/i386.c	Mon Dec 23 11:17:20 2013
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.51 2013/12/23 10:13:59 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.52 2013/12/23 11:17:20 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.51 2013/12/23 10:13:59 msaitoh Exp $);
+__RCSID($NetBSD: i386.c,v 1.52 2013/12/23 11:17:20 msaitoh Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -94,6 +94,7 @@ struct cpu_info {
 	const char	*ci_dev;
 	int32_t		ci_cpu_type; /* for cpu's without cpuid */
 	int32_t		ci_cpuid_level;	 /* highest cpuid supported */
+	uint32_t	ci_cpuid_extlevel; /* highest cpuid extended func lv */
 	uint32_t	ci_signature;	 /* X86 cpuid type */
 	uint32_t	ci_family;	 /* from ci_signature */
 	uint32_t	ci_model;	 /* from ci_signature */
@@ -212,6 +213,7 @@ static void	powernow_probe(struct cpu_in
 static void	intel_family_new_probe(struct cpu_info *);
 static void	via_cpu_probe(struct cpu_info *);
 /* (Cache) Info functions */
+static void 	intel_cpu_cacheinfo(struct cpu_info *);
 static void 	amd_cpu_cacheinfo(struct cpu_info *);
 static void	via_cpu_cacheinfo(struct cpu_info *);
 static void	tmx86_get_longrun_status(u_int *, u_int *, u_int *);
@@ -285,7 +287,7 @@ const struct cpu_cpuid_nameclass i386_cp
 			486,		/* Default */
 			NULL,
 			NULL,
-			NULL,
+			intel_cpu_cacheinfo,
 		},
 		/* Family 5 */
 		{
@@ -300,7 +302,7 @@ const struct cpu_cpuid_nameclass i386_cp
 			Pentium,	/* Default */
 			NULL,
 			NULL,
-			NULL,
+			intel_cpu_cacheinfo,
 		},
 		/* Family 6 */
 		{
@@ -363,7 +365,7 @@ const struct cpu_cpuid_nameclass i386_cp
 			Pentium Pro, II or III,	/* Default */
 			NULL,
 			intel_family_new_probe,
-			NULL,
+			intel_cpu_cacheinfo,
 		},
 		/* Family  6 */
 		{
@@ -375,7 +377,7 @@ const struct cpu_cpuid_nameclass i386_cp
 			Pentium 4,	/* Default */
 			NULL,
 			intel_family_new_probe,
-			NULL,
+			intel_cpu_cacheinfo,
 		} }
 	},
 	{
@@ -956,6 +958,103 @@ amd_family6_probe(struct cpu_info *ci)
 		}
 }
 
+static void
+intel_cpu_cacheinfo(struct cpu_info *ci)
+{
+	const struct x86_cache_info *cai;
+	u_int descs[4];
+	int iterations, i, j;
+	int type, level;
+	int ways, partitions, linesize, sets;
+	int caitype = -1;
+	int totalsize;
+	uint8_t desc;
+
+	/* Return if the cpu is old pre-cpuid instruction cpu */
+	if (ci-ci_cpu_type = 0)
+		return;
+
+	if (ci-ci_cpuid_level  2)
+		return;
+
+	/*
+	 * Parse the cache info from `cpuid leaf 2', if we have it.
+	 * XXX This is kinda ugly, but hey, so is the architecture...
+	 */
+	x86_cpuid(2, descs);
+	iterations = descs[0]  0xff;
+	while (iterations--  0) {
+		for (i = 0; i  4; i++) {
+			if (descs[i]  0x8000)
+continue;
+			for (j = 0; j  4; j++) {
+if (i == 0  j == 0)
+	continue;
+desc = (descs[i]  (j * 8))  0xff;
+if (desc == 0)
+	continue;
+cai = cache_info_lookup(intel_cpuid_cache_info,
+desc);
+if (cai != NULL)
+	ci-ci_cinfo[cai-cai_index] = *cai;
+			}
+		}
+		x86_cpuid(2, descs);
+	}
+
+	if (ci-ci_cpuid_level  4)
+		return;
+
+	/* Parse the cache info from `cpuid leaf 4', if we have it. */
+	for (i = 0; ; i++) {
+		x86_cpuid2(4, i, descs);
+		type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE);
+		if (type == CPUID_DCP_CACHETYPE_N)
+			break;
+		level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL);
+		switch (level) {
+		case 1:
+			if (type == CPUID_DCP_CACHETYPE_I)
+caitype = CAI_ICACHE;
+			else if (type == CPUID_DCP_CACHETYPE_D)
+caitype = CAI_DCACHE;
+			else
+caitype = -1;
+			break;
+		case 2:
+			if (type == CPUID_DCP_CACHETYPE_U)
+caitype = CAI_L2CACHE;
+			else
+caitype = -1;
+			break;
+		case 3:
+			if (type == CPUID_DCP_CACHETYPE_U)
+caitype = CAI_L3CACHE;
+			else
+caitype = -1;
+			break;
+		default:
+			caitype = -1;
+			break;
+		}
+		if (caitype == -1) {
+			printf(unknown cache leveltype (%d  %d)\n,
+			level, type);
+			continue;
+		}
+		ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1;
+		partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS)
+		+ 1;
+		linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE)
+		+ 1;
+		sets = descs[2] + 1;
+		totalsize = ways * partitions * linesize * sets;
+		ci-ci_cinfo[caitype].cai_totalsize = totalsize;
+

CVS commit: src/usr.sbin/cpuctl/arch

2013-11-07 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Thu Nov  7 18:18:59 UTC 2013

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
Update some processor names.


To generate a diff of this commit:
cvs rdiff -u -r1.47 -r1.48 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.47 src/usr.sbin/cpuctl/arch/i386.c:1.48
--- src/usr.sbin/cpuctl/arch/i386.c:1.47	Wed Oct 30 08:42:16 2013
+++ src/usr.sbin/cpuctl/arch/i386.c	Thu Nov  7 18:18:59 2013
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.47 2013/10/30 08:42:16 mrg Exp $	*/
+/*	$NetBSD: i386.c,v 1.48 2013/11/07 18:18:59 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.47 2013/10/30 08:42:16 mrg Exp $);
+__RCSID($NetBSD: i386.c,v 1.48 2013/11/07 18:18:59 msaitoh Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -342,18 +342,19 @@ const struct cpu_cpuid_nameclass i386_cp
 [0x2a] = Xeon E3-12xx, 2nd gen i7, i5, 
 	 i3 2xxx,
 [0x2c] = Xeon 36xx  56xx, i7, i5 and i3,
-[0x2d] = Xeon E5 Sandy bridy family,
+[0x2d] = Xeon E5 Sandy Bridy family, 
+	 Core i7-39xx Extreme,
 [0x2e] = Xeon 75xx  65xx,
 [0x2f] = Xeon E7 family,
 [0x35] = Atom Family,
 [0x36] = Atom S1000,
 [0x37] = Atom C2000, E3000,
 [0x3a] = Xeon E3-1200v2 and 3rd gen core, 
-	 Ivy bridge,
+	 Ivy Bridge,
 [0x3c] = 4th gen Core, Xeon E3-12xx v3 
 	 (Haswell),
 [0x3d] = Next gen Core,
-[0x3e] = Next gen Xeon E5/E7, Ivy bridge,
+[0x3e] = Xeon E5/E7, Ivy Bridge-EP,
 [0x3f] = Future gen Xeon,
 [0x45] = 4th gen Core, Xeon E3-12xx v3 
 	 (Haswell),

CVS commit: src/usr.sbin/cpuctl/arch

2013-11-07 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Thu Nov  7 18:59:01 UTC 2013

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
Fix typo. From jnemeth.


To generate a diff of this commit:
cvs rdiff -u -r1.48 -r1.49 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.48 src/usr.sbin/cpuctl/arch/i386.c:1.49
--- src/usr.sbin/cpuctl/arch/i386.c:1.48	Thu Nov  7 18:18:59 2013
+++ src/usr.sbin/cpuctl/arch/i386.c	Thu Nov  7 18:59:01 2013
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.48 2013/11/07 18:18:59 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.49 2013/11/07 18:59:01 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.48 2013/11/07 18:18:59 msaitoh Exp $);
+__RCSID($NetBSD: i386.c,v 1.49 2013/11/07 18:59:01 msaitoh Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -342,7 +342,7 @@ const struct cpu_cpuid_nameclass i386_cp
 [0x2a] = Xeon E3-12xx, 2nd gen i7, i5, 
 	 i3 2xxx,
 [0x2c] = Xeon 36xx  56xx, i7, i5 and i3,
-[0x2d] = Xeon E5 Sandy Bridy family, 
+[0x2d] = Xeon E5 Sandy Bridge family, 
 	 Core i7-39xx Extreme,
 [0x2e] = Xeon 75xx  65xx,
 [0x2f] = Xeon E7 family,

CVS commit: src/usr.sbin/cpuctl/arch

2013-10-30 Thread matthew green

Module Name:src
Committed By:   mrg
Date:   Wed Oct 30 08:42:16 UTC 2013

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
avoid uninitialised variable use.


To generate a diff of this commit:
cvs rdiff -u -r1.46 -r1.47 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.46 src/usr.sbin/cpuctl/arch/i386.c:1.47
--- src/usr.sbin/cpuctl/arch/i386.c:1.46	Mon Oct 28 05:41:49 2013
+++ src/usr.sbin/cpuctl/arch/i386.c	Wed Oct 30 08:42:16 2013
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.46 2013/10/28 05:41:49 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.47 2013/10/30 08:42:16 mrg Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.46 2013/10/28 05:41:49 msaitoh Exp $);
+__RCSID($NetBSD: i386.c,v 1.47 2013/10/30 08:42:16 mrg Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -1986,7 +1986,7 @@ cache_info_lookup(const struct x86_cache
 static void
 x86_print_cacheinfo(struct cpu_info *ci)
 {
-	const char *sep;
+	const char *sep = NULL;
 
 	if (ci-ci_cinfo[CAI_ICACHE].cai_totalsize != 0 ||
 	ci-ci_cinfo[CAI_DCACHE].cai_totalsize != 0) {

CVS commit: src/usr.sbin/cpuctl/arch

2013-10-04 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Fri Oct  4 17:12:48 UTC 2013

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
Fix typo in comment (s/XRC0/XCR0/).


To generate a diff of this commit:
cvs rdiff -u -r1.42 -r1.43 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.42 src/usr.sbin/cpuctl/arch/i386.c:1.43
--- src/usr.sbin/cpuctl/arch/i386.c:1.42	Sat Sep 14 17:23:18 2013
+++ src/usr.sbin/cpuctl/arch/i386.c	Fri Oct  4 17:12:48 2013
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.42 2013/09/14 17:23:18 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.43 2013/10/04 17:12:48 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.42 2013/09/14 17:23:18 msaitoh Exp $);
+__RCSID($NetBSD: i386.c,v 1.43 2013/10/04 17:12:48 msaitoh Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -1038,7 +1038,7 @@ cpu_probe_base_features(struct cpu_info 
 	if (ci-ci_cpuid_level  0xd)
 		return;
 
-	/* Get support XRC0 bits */
+	/* Get support XCR0 bits */
 	x86_cpuid2(0xd, 0, descs);
 	ci-ci_feat_val[5] = descs[0];	/* Actually 64 bits */
 	ci-ci_cur_xsave = descs[1];

CVS commit: src/usr.sbin/cpuctl/arch

2013-09-14 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Sat Sep 14 17:23:18 UTC 2013

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
Add shared TLB.
KNF.


To generate a diff of this commit:
cvs rdiff -u -r1.41 -r1.42 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.41 src/usr.sbin/cpuctl/arch/i386.c:1.42
--- src/usr.sbin/cpuctl/arch/i386.c:1.41	Fri Sep 13 06:21:43 2013
+++ src/usr.sbin/cpuctl/arch/i386.c	Sat Sep 14 17:23:18 2013
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.41 2013/09/13 06:21:43 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.42 2013/09/14 17:23:18 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.41 2013/09/13 06:21:43 msaitoh Exp $);
+__RCSID($NetBSD: i386.c,v 1.42 2013/09/14 17:23:18 msaitoh Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -1961,23 +1961,33 @@ x86_print_cacheinfo(struct cpu_info *ci)
 		if (sep != NULL)
 			aprint_verbose(\n);
 	}
+	if (ci-ci_cinfo[CAI_L2_STLB].cai_totalsize != 0) {
+		sep = print_tlb_config(ci, CAI_L2_STLB, L2 STLB, NULL);
+		sep = print_tlb_config(ci, CAI_L2_STLB2, NULL, sep);
+		if (sep != NULL)
+			aprint_verbose(\n);
+	}
 	if (ci-ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) {
-		sep = print_tlb_config(ci, CAI_L1_1GBITLB, L1 1GB page ITLB, NULL);
+		sep = print_tlb_config(ci, CAI_L1_1GBITLB, L1 1GB page ITLB,
+		NULL);
 		if (sep != NULL)
 			aprint_verbose(\n);
 	}
 	if (ci-ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) {
-		sep = print_tlb_config(ci, CAI_L1_1GBDTLB, L1 1GB page DTLB, NULL);
+		sep = print_tlb_config(ci, CAI_L1_1GBDTLB, L1 1GB page DTLB,
+		NULL);
 		if (sep != NULL)
 			aprint_verbose(\n);
 	}
 	if (ci-ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) {
-		sep = print_tlb_config(ci, CAI_L2_1GBITLB, L2 1GB page ITLB, NULL);
+		sep = print_tlb_config(ci, CAI_L2_1GBITLB, L2 1GB page ITLB,
+		NULL);
 		if (sep != NULL)
 			aprint_verbose(\n);
 	}
 	if (ci-ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) {
-		sep = print_tlb_config(ci, CAI_L2_1GBDTLB, L2 1GB page DTLB, NULL);
+		sep = print_tlb_config(ci, CAI_L2_1GBDTLB, L2 1GB page DTLB,
+		NULL);
 		if (sep != NULL)
 			aprint_verbose(\n);
 	}

CVS commit: src/usr.sbin/cpuctl/arch

2013-09-13 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Fri Sep 13 06:21:43 UTC 2013

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
Update Intel processors' brand names and model names (e.g. Atom C2000 and
E3000) from the latest document.


To generate a diff of this commit:
cvs rdiff -u -r1.40 -r1.41 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.40 src/usr.sbin/cpuctl/arch/i386.c:1.41
--- src/usr.sbin/cpuctl/arch/i386.c:1.40	Tue Jul 16 09:54:30 2013
+++ src/usr.sbin/cpuctl/arch/i386.c	Fri Sep 13 06:21:43 2013
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.40 2013/07/16 09:54:30 msaitoh Exp $	*/
+/*	$NetBSD: i386.c,v 1.41 2013/09/13 06:21:43 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.40 2013/07/16 09:54:30 msaitoh Exp $);
+__RCSID($NetBSD: i386.c,v 1.41 2013/09/13 06:21:43 msaitoh Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -151,7 +151,9 @@ static const struct x86_cache_info intel
 
 /*
  * Map Brand ID from cpuid instruction to brand name.
- * Source: Intel Processor Identification and the CPUID Instruction, AP-485
+ * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32
+ * Processor Brand Strings, Chapter 3 in Intel (R) 64 and IA-32
+ * Architectures Software Developer's Manual, Volume 2A.
  */
 static const char * const i386_intel_brand[] = {
 	,		/* Unsupported */
@@ -159,7 +161,7 @@ static const char * const i386_intel_bra
 	Pentium III,  /* Intel (R) Pentium (R) III processor */
 	Pentium III Xeon, /* Intel (R) Pentium (R) III Xeon (TM) processor */
 	Pentium III,  /* Intel (R) Pentium (R) III processor */
-	,		/* Reserved */
+	,		/* 0x05: Reserved */
 	Mobile Pentium III, /* Mobile Intel (R) Pentium (R) III processor-M */
 	Mobile Celeron,   /* Mobile Intel (R) Celeron (R) processor */
 	Pentium 4,	/* Intel (R) Pentium (R) 4 processor */
@@ -167,9 +169,17 @@ static const char * const i386_intel_bra
 	Celeron,	/* Intel (R) Celeron (TM) processor */
 	Xeon,		/* Intel (R) Xeon (TM) processor */
 	Xeon MP,	/* Intel (R) Xeon (TM) processor MP */
-	,		/* Reserved */
+	,		/* 0x0d: Reserved */
 	Mobile Pentium 4, /* Mobile Intel (R) Pentium (R) 4 processor-M */
 	Mobile Celeron,   /* Mobile Intel (R) Celeron (R) processor */
+	,		/* 0x10: Reserved */
+	Mobile Genuine,   /* Moblie Genuine Intel (R) processor */
+	Celeron M,/* Intel (R) Celeron (R) M processor */
+	Mobile Celeron,   /* Mobile Intel (R) Celeron (R) processor */
+	Celeron,  /* Intel (R) Celeron (R) processor */
+	Mobile Genuine,   /* Moblie Genuine Intel (R) processor */
+	Pentium M,/* Intel (R) Pentium (R) M processor */
+	Mobile Celeron,   /* Mobile Intel (R) Celeron (R) processor */
 };
 
 /*
@@ -246,6 +256,11 @@ const char *modifiers[] = {
 
 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = {
 	{
+		/*
+		 * For Intel processors, check Chapter 35Model-specific
+		 * registers (MSRS), in Intel (R) 64 and IA-32 Architectures
+		 * Software Developer's Manual, Volume 3C.
+		 */
 		GenuineIntel,
 		CPUVENDOR_INTEL,
 		Intel,
@@ -281,7 +296,6 @@ const struct cpu_cpuid_nameclass i386_cp
 		{
 			CPUCLASS_686,
 			{
-/* Updated from intel_x86_325486.pdf Aug 2012 */
 [0x00] = Pentium Pro (A-step),
 [0x01] = Pentium Pro,
 [0x03] = Pentium II (Klamath),
@@ -320,17 +334,20 @@ const struct cpu_cpuid_nameclass i386_cp
 [0x2e] = Xeon 75xx  65xx,
 [0x2f] = Xeon E7 family,
 [0x35] = Atom Family,
-[0x36] = Atom S,
+[0x36] = Atom S1000,
+[0x37] = Atom C2000, E3000,
 [0x3a] = Xeon E3-1200v2 and 3rd gen core, 
 	 Ivy bridge,
 [0x3c] = 4th gen Core, Xeon E3-12xx v3 
 	 (Haswell),
+[0x3d] = Next gen Core,
 [0x3e] = Next gen Xeon E5/E7, Ivy bridge,
 [0x3f] = Future gen Xeon,
 [0x45] = 4th gen Core, Xeon E3-12xx v3 
 	 (Haswell),
 [0x46] = 4th gen Core, Xeon E3-12xx v3 
 	 (Haswell),
+[0x4d] = Atom C2000, E3000,
 			},
 			Pentium Pro, II or III,	/* Default */
 			NULL,

CVS commit: src/usr.sbin/cpuctl/arch

2013-07-16 Thread SAITOH Masanobu

Module Name:src
Committed By:   msaitoh
Date:   Tue Jul 16 09:54:30 UTC 2013

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
 Update Intel's Processor Family Names of family == 6 from the latest document.
Add 0x35(Atom), 0x36(Atom S), 0x3f(future Xeon), 0x46(Haswell) and update some
models.


To generate a diff of this commit:
cvs rdiff -u -r1.39 -r1.40 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.39 src/usr.sbin/cpuctl/arch/i386.c:1.40
--- src/usr.sbin/cpuctl/arch/i386.c:1.39	Wed Mar  6 11:52:53 2013
+++ src/usr.sbin/cpuctl/arch/i386.c	Tue Jul 16 09:54:30 2013
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.39 2013/03/06 11:52:53 yamt Exp $	*/
+/*	$NetBSD: i386.c,v 1.40 2013/07/16 09:54:30 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.39 2013/03/06 11:52:53 yamt Exp $);
+__RCSID($NetBSD: i386.c,v 1.40 2013/07/16 09:54:30 msaitoh Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -294,12 +294,18 @@ const struct cpu_cpuid_nameclass i386_cp
 [0x0a] = Pentium III Xeon (Cascades),
 [0x0b] = Pentium III (Tualatin),
 [0x0d] = Pentium M (Dothan), 
-[0x0e] = Pentium Core Duo, // M (Yonah),
-[0x0f] = Core 2,
+[0x0e] = Pentium Core Duo, Core solo,
+[0x0f] = Xeon 30xx, 32xx, 51xx, 53xx, 73xx, 
+	 Core 2 Quad 6xxx, 
+	 Core 2 Extreme 6xxx, 
+	 Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx 
+	 and Pentium DC,
 [0x15] = EP80579 Integrated Processor,
 [0x16] = Celeron (45nm),
-[0x17] = Core 2 Extreme,
-[0x1a] = Core i7 (Nehalem),
+[0x17] = Xeon 31xx, 33xx, 52xx, 54xx, 
+	 Core 2 Quad 8xxx and 9xxx,
+[0x1a] = Core i7, Xeon 34xx, 35xx and 55xx 
+	 (Nehalem),
 [0x1c] = Atom Family,
 [0x1d] = XeonMP 74xx (Nehalem),
 [0x1e] = Core i7 and i5,
@@ -307,15 +313,24 @@ const struct cpu_cpuid_nameclass i386_cp
 [0x25] = Xeon 36xx  56xx, i7, i5 and i3,
 [0x26] = Atom Family,
 [0x27] = Atom Family,
-[0x2a] = Xeon E3-12xx, 2nd gen i7, i5, i3 2xxx,
+[0x2a] = Xeon E3-12xx, 2nd gen i7, i5, 
+	 i3 2xxx,
 [0x2c] = Xeon 36xx  56xx, i7, i5 and i3,
-[0x2e] = Xeon 75xx  65xx,
 [0x2d] = Xeon E5 Sandy bridy family,
+[0x2e] = Xeon 75xx  65xx,
 [0x2f] = Xeon E7 family,
-[0x3a] = Xeon E3-1200v2 and 3rd gen core, Ivy bridge,
-[0x3c] = Next Intel Core,
-[0x3e] = Next gen Xeon E5, Ivy bridge,
-[0x45] = Next Intel Core,
+[0x35] = Atom Family,
+[0x36] = Atom S,
+[0x3a] = Xeon E3-1200v2 and 3rd gen core, 
+	 Ivy bridge,
+[0x3c] = 4th gen Core, Xeon E3-12xx v3 
+	 (Haswell),
+[0x3e] = Next gen Xeon E5/E7, Ivy bridge,
+[0x3f] = Future gen Xeon,
+[0x45] = 4th gen Core, Xeon E3-12xx v3 
+	 (Haswell),
+[0x46] = 4th gen Core, Xeon E3-12xx v3 
+	 (Haswell),
 			},
 			Pentium Pro, II or III,	/* Default */
 			NULL,

CVS commit: src/usr.sbin/cpuctl/arch

2013-03-06 Thread YAMAMOTO Takashi

Module Name:src
Committed By:   yamt
Date:   Wed Mar  6 11:52:54 UTC 2013

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
print some more bits


To generate a diff of this commit:
cvs rdiff -u -r1.38 -r1.39 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.38 src/usr.sbin/cpuctl/arch/i386.c:1.39
--- src/usr.sbin/cpuctl/arch/i386.c:1.38	Mon Jan  7 23:20:42 2013
+++ src/usr.sbin/cpuctl/arch/i386.c	Wed Mar  6 11:52:53 2013
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.38 2013/01/07 23:20:42 dsl Exp $	*/
+/*	$NetBSD: i386.c,v 1.39 2013/03/06 11:52:53 yamt Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.38 2013/01/07 23:20:42 dsl Exp $);
+__RCSID($NetBSD: i386.c,v 1.39 2013/03/06 11:52:53 yamt Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -658,6 +658,7 @@ identifycpu_cpuids(struct cpu_info *ci)
 	u_int core_max = 1;	/* core per package */
 	u_int smt_bits, core_bits;
 	uint32_t descs[4];
+	uint32_t highest_basic_info;
 
 	aprint_verbose(%s: Initial APIC ID %u\n, cpuname, ci-ci_initapicid);
 	ci-ci_packageid = ci-ci_initapicid;
@@ -676,7 +677,8 @@ identifycpu_cpuids(struct cpu_info *ci)
 		lp_max = (descs[1]  16)  0xff;
 	}
 	x86_cpuid(0, descs);
-	if (descs[0] = 4) {
+	highest_basic_info = descs[0];
+	if (highest_basic_info = 4) {
 		x86_cpuid2(4, 0, descs);
 		core_max = (descs[0]  26) + 1;
 	}
@@ -1427,6 +1429,44 @@ identifycpu(int fd, const char *cpuname)
 			print_bits(cpuname, SVM features, CPUID_AMD_SVM_FLAGS,
    data[3]);
 		}
+	} else if (cpu_vendor == CPUVENDOR_INTEL) {
+		uint32_t data[4];
+		uint32_t highest_basic_info;
+		uint32_t bi_index;
+
+		x86_cpuid(0x, data);
+		highest_basic_info = data[0];
+		aprint_verbose(%s: highest basic info %08x\n, cpuname,
+		highest_basic_info);
+		for (bi_index = 1; bi_index = highest_basic_info; bi_index++) {
+			x86_cpuid(bi_index, data);
+			switch (bi_index) {
+			case 6:
+print_bits(cpuname, DSPM-eax,
+CPUID_DSPM_FLAGS, data[0]);
+print_bits(cpuname, DSPM-ecx,
+CPUID_DSPM_FLAGS1, data[2]);
+break;
+			case 7:
+aprint_verbose(%s: SEF highest subleaf %08x\n,
+cpuname, data[0]);
+print_bits(cpuname, SEF-main, CPUID_SEF_FLAGS,
+data[1]);
+break;
+#if 0
+			default:
+aprint_verbose(%s: basic %08x-eax %08x\n,
+cpuname, bi_index, data[0]);
+aprint_verbose(%s: basic %08x-ebx %08x\n,
+cpuname, bi_index, data[1]);
+aprint_verbose(%s: basic %08x-ecx %08x\n,
+cpuname, bi_index, data[2]);
+aprint_verbose(%s: basic %08x-edx %08x\n,
+cpuname, bi_index, data[3]);
+break;
+#endif
+			}
+		}
 	}
 
 #ifdef INTEL_ONDEMAND_CLOCKMOD

CVS commit: src/usr.sbin/cpuctl/arch

2013-01-07 Thread David Laight

Module Name:src
Committed By:   dsl
Date:   Mon Jan  7 23:20:42 UTC 2013

Modified Files:
src/usr.sbin/cpuctl/arch: cpuctl_i386.h i386-asm.S i386.c x86_64-asm.S

Log Message:
Add support for the xsave related data from cpuid 8.n.
Reorder the output so that the 'brand' string - which actually identifies
  the cpu is output first.


To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/usr.sbin/cpuctl/arch/cpuctl_i386.h
cvs rdiff -u -r1.2 -r1.3 src/usr.sbin/cpuctl/arch/i386-asm.S
cvs rdiff -u -r1.37 -r1.38 src/usr.sbin/cpuctl/arch/i386.c
cvs rdiff -u -r1.3 -r1.4 src/usr.sbin/cpuctl/arch/x86_64-asm.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/cpuctl_i386.h
diff -u src/usr.sbin/cpuctl/arch/cpuctl_i386.h:1.1 src/usr.sbin/cpuctl/arch/cpuctl_i386.h:1.2
--- src/usr.sbin/cpuctl/arch/cpuctl_i386.h:1.1	Sat Jan  5 15:27:45 2013
+++ src/usr.sbin/cpuctl/arch/cpuctl_i386.h	Mon Jan  7 23:20:42 2013
@@ -1,4 +1,4 @@
-/*  $NetBSD: cpuctl_i386.h,v 1.1 2013/01/05 15:27:45 dsl Exp $  */
+/*  $NetBSD: cpuctl_i386.h,v 1.2 2013/01/07 23:20:42 dsl Exp $  */
 
 /* Interfaces to code in i386-asm.S */
 
@@ -6,3 +6,4 @@
 
 void x86_cpuid2(uint32_t, uint32_t, uint32_t *);
 uint32_t x86_identify(void);
+uint32_t x86_xgetbv(void);

Index: src/usr.sbin/cpuctl/arch/i386-asm.S
diff -u src/usr.sbin/cpuctl/arch/i386-asm.S:1.2 src/usr.sbin/cpuctl/arch/i386-asm.S:1.3
--- src/usr.sbin/cpuctl/arch/i386-asm.S:1.2	Sat Jan  5 15:27:45 2013
+++ src/usr.sbin/cpuctl/arch/i386-asm.S	Mon Jan  7 23:20:42 2013
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386-asm.S,v 1.2 2013/01/05 15:27:45 dsl Exp $	*/
+/*	$NetBSD: i386-asm.S,v 1.3 2013/01/07 23:20:42 dsl Exp $	*/
 
 /*-
  * Copyright (c) 1998, 2000, 2004, 2006, 2007 The NetBSD Foundation, Inc.
@@ -48,6 +48,11 @@ ENTRY(x86_cpuid2)
 	ret
 END(x86_cpuid2)
 
+ENTRY(x86_xgetbv)
+	xgetbv
+	ret
+END(x86_xgetbv)
+
 ENTRY(x86_identify)
 	/* Try to toggle alignment check flag; does not exist on 386. */
 	pushfl

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.37 src/usr.sbin/cpuctl/arch/i386.c:1.38
--- src/usr.sbin/cpuctl/arch/i386.c:1.37	Sun Jan  6 23:17:35 2013
+++ src/usr.sbin/cpuctl/arch/i386.c	Mon Jan  7 23:20:42 2013
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.37 2013/01/06 23:17:35 dsl Exp $	*/
+/*	$NetBSD: i386.c,v 1.38 2013/01/07 23:20:42 dsl Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.37 2013/01/06 23:17:35 dsl Exp $);
+__RCSID($NetBSD: i386.c,v 1.38 2013/01/07 23:20:42 dsl Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -97,12 +97,14 @@ struct cpu_info {
 	uint32_t	ci_signature;	 /* X86 cpuid type */
 	uint32_t	ci_family;	 /* from ci_signature */
 	uint32_t	ci_model;	 /* from ci_signature */
-	uint32_t	ci_feat_val[5];	 /* X86 CPUID feature bits
+	uint32_t	ci_feat_val[8];	 /* X86 CPUID feature bits
 	  *	[0] basic features %edx
 	  *	[1] basic features %ecx
 	  *	[2] extended features %edx
 	  *	[3] extended features %ecx
 	  *	[4] VIA padlock features
+	  *	[5] XCR0 bits (d:0 %eax)
+	  *	[6] xsave flags (d:1 %eax)
 	  */
 	uint32_t	ci_cpu_class;	 /* CPU class */
 	uint32_t	ci_brand_id;	 /* Intel brand id */
@@ -113,6 +115,10 @@ struct cpu_info {
 	uint8_t		ci_coreid;
 	uint8_t		ci_smtid;
 	uint32_t	ci_initapicid;
+
+	uint32_t	ci_cur_xsave;
+	uint32_t	ci_max_xsave;
+
 	struct x86_cache_info ci_cinfo[CAI_COUNT];
 	void		(*ci_info)(struct cpu_info *);
 };
@@ -204,11 +210,6 @@ static void amd_family5_setup(struct cpu
 static void powernow_probe(struct cpu_info *);
 
 /*
- * Info for CTL_HW
- */
-static char	cpu_model[120];
-
-/*
  * Note: these are just the ones that may not have a cpuid instruction.
  * We deal with the rest in a different way.
  */
@@ -999,6 +1000,19 @@ cpu_probe_base_features(struct cpu_info 
 		ci-ci_cpu_serial[2] = descs[2];
 		ci-ci_cpu_serial[1] = descs[3];
 	}
+
+	if (ci-ci_cpuid_level  0xd)
+		return;
+
+	/* Get support XRC0 bits */
+	x86_cpuid2(0xd, 0, descs);
+	ci-ci_feat_val[5] = descs[0];	/* Actually 64 bits */
+	ci-ci_cur_xsave = descs[1];
+	ci-ci_max_xsave = descs[2];
+
+	/* Additional flags (eg xsaveopt support) */
+	x86_cpuid2(0xd, 1, descs);
+	ci-ci_feat_val[6] = descs[0];   /* Actually 64 bits */
 }
 
 static void
@@ -1159,6 +1173,26 @@ transmeta_cpu_info(struct cpu_info *ci)
 	}
 }
 
+static void
+print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val)
+{
+	char buf[32 * 16];
+	char *bp;
+
+#define	MAX_LINE_LEN	79	/* get from command arg or 'stty cols' ? */
+
+	if (val == 0 || fmt == NULL)
+		return;
+
+	snprintb_m(buf, sizeof(buf), fmt, val,
+	MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1);
+	bp = buf;
+	while (*bp != '\0') {
+		aprint_verbose(%s: %s %s\n, cpuname, hdr, bp);
+		bp +=

CVS commit: src/usr.sbin/cpuctl/arch

2013-01-06 Thread David Laight

Module Name:src
Committed By:   dsl
Date:   Sun Jan  6 23:17:35 UTC 2013

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
Use full model number to index name strings - a lot of 256 element arrays
don't matter in usespace.
Update list of intel family 6 model names (all current cpus) to include
everything upto and including sandy bridge and ivy bridge.
My i7 is no longer reported as a random P II.


To generate a diff of this commit:
cvs rdiff -u -r1.36 -r1.37 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.36 src/usr.sbin/cpuctl/arch/i386.c:1.37
--- src/usr.sbin/cpuctl/arch/i386.c:1.36	Sat Jan  5 21:16:22 2013
+++ src/usr.sbin/cpuctl/arch/i386.c	Sun Jan  6 23:17:35 2013
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.36 2013/01/05 21:16:22 dsl Exp $	*/
+/*	$NetBSD: i386.c,v 1.37 2013/01/06 23:17:35 dsl Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.36 2013/01/05 21:16:22 dsl Exp $);
+__RCSID($NetBSD: i386.c,v 1.37 2013/01/06 23:17:35 dsl Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -127,22 +127,17 @@ struct cpu_nocpuid_nameclass {
 	void (*cpu_info)(struct cpu_info *);
 };
 
-struct cpu_extend_nameclass {
-	int ext_model;
-	const char *cpu_models[CPU_MAXMODEL+1];
-};
-
 struct cpu_cpuid_nameclass {
 	const char *cpu_id;
 	int cpu_vendor;
 	const char *cpu_vendorname;
 	struct cpu_cpuid_family {
 		int cpu_class;
-		const char *cpu_models[CPU_MAXMODEL+2];
+		const char *cpu_models[256];
+		const char *cpu_model_default;
 		void (*cpu_setup)(struct cpu_info *);
 		void (*cpu_probe)(struct cpu_info *);
 		void (*cpu_info)(struct cpu_info *);
-		struct cpu_extend_nameclass *cpu_extended_names;
 	} cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1];
 };
 
@@ -248,21 +243,6 @@ const char *modifiers[] = {
 	
 };
 
-struct cpu_extend_nameclass intel_family6_ext_models[] = {
-	{ /* Extended models 1x */
-	  0x01, { NULL,			NULL,
-		  NULL,			NULL,
-		  NULL,			EP80579 Integrated Processor,
-		  Celeron (45nm),	Core 2 Extreme,
-		  NULL,			NULL,
-		  Core i7 (Nehalem),	NULL,
-		  Atom,		XeonMP (Nehalem),
-		   NULL,		NULL} },
-	{ /* End of list */
-	  0x00, { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
-		  NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL} }
-};
-
 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = {
 	{
 		GenuineIntel,
@@ -275,9 +255,8 @@ const struct cpu_cpuid_nameclass i386_cp
 486DX, 486DX, 486SX, 486DX2, 486SL,
 486SX2, 0, 486DX2 W/B Enhanced,
 486DX4, 0, 0, 0, 0, 0, 0, 0,
-486		/* Default */
 			},
-			NULL,
+			486,		/* Default */
 			NULL,
 			NULL,
 			NULL,
@@ -291,9 +270,8 @@ const struct cpu_cpuid_nameclass i386_cp
 Pentium/MMX, Pentium, 0,
 Pentium (P54C), Pentium/MMX (Tillamook),
 0, 0, 0, 0, 0, 0, 0,
-Pentium	/* Default */
 			},
-			NULL,
+			Pentium,	/* Default */
 			NULL,
 			NULL,
 			NULL,
@@ -302,24 +280,46 @@ const struct cpu_cpuid_nameclass i386_cp
 		{
 			CPUCLASS_686,
 			{
-Pentium Pro (A-step), Pentium Pro, 0,
-Pentium II (Klamath), Pentium Pro,
-Pentium II/Celeron (Deschutes),
-Celeron (Mendocino),
-Pentium III (Katmai),
-Pentium III (Coppermine),
-Pentium M (Banias), 
-Pentium III Xeon (Cascades),
-Pentium III (Tualatin), 0,
-Pentium M (Dothan), 
-Pentium M (Yonah),
-Core 2,
-Pentium Pro, II or III	/* Default */
+/* Updated from intel_x86_325486.pdf Aug 2012 */
+[0x00] = Pentium Pro (A-step),
+[0x01] = Pentium Pro,
+[0x03] = Pentium II (Klamath),
+[0x04] = Pentium Pro,
+[0x05] = Pentium II/Celeron (Deschutes),
+[0x06] = Celeron (Mendocino),
+[0x07] = Pentium III (Katmai),
+[0x08] = Pentium III (Coppermine),
+[0x09] = Pentium M (Banias), 
+[0x0a] = Pentium III Xeon (Cascades),
+[0x0b] = Pentium III (Tualatin),
+[0x0d] = Pentium M (Dothan), 
+[0x0e] = Pentium Core Duo, // M (Yonah),
+[0x0f] = Core 2,
+[0x15] = EP80579 Integrated Processor,
+[0x16] = Celeron (45nm),
+[0x17] = Core 2 Extreme,
+[0x1a] = Core i7 (Nehalem),
+[0x1c] = Atom Family,
+[0x1d] = XeonMP 74xx (Nehalem),
+[0x1e] = Core i7 and i5,
+[0x1f] = Core i7 and i5,
+[0x25] = Xeon 36xx  56xx, i7, i5 and i3,
+[0x26] = Atom Family,
+[0x27] = Atom Family,
+[0x2a] = Xeon E3-12xx, 2nd gen i7, i5, i3 2xxx,
+[0x2c] = Xeon 36xx  56xx, i7, i5 and i3,
+[0x2e] = Xeon 75xx  65xx,
+[0x2d] = Xeon E5 Sandy bridy family,
+[0x2f] = Xeon E7 family,
+[0x3a] = Xeon E3-1200v2 and 3rd gen core, Ivy bridge,
+[0x3c] = Next Intel Core,
+[0x3e] = Next gen Xeon E5, Ivy bridge,
+[0x45] = Next Intel Core,
 			},
+			Pentium Pro, II or III,	/* Default */

CVS commit: src/usr.sbin/cpuctl/arch

2013-01-05 Thread David Laight

Module Name:src
Committed By:   dsl
Date:   Sat Jan  5 15:27:46 UTC 2013

Modified Files:
src/usr.sbin/cpuctl/arch: i386-asm.S i386.c
Added Files:
src/usr.sbin/cpuctl/arch: cpuctl_i386.h

Log Message:
Change the i386 asm x86_identify() so it returns a value instead of writing
into global data.
Fix a stack alignment fubar that would cause a crash on a cirix 486.
Refactor identify code to common setup for normal identify and ucode
identify - which was missing a memset().


To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1 src/usr.sbin/cpuctl/arch/cpuctl_i386.h
cvs rdiff -u -r1.1 -r1.2 src/usr.sbin/cpuctl/arch/i386-asm.S
cvs rdiff -u -r1.33 -r1.34 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386-asm.S
diff -u src/usr.sbin/cpuctl/arch/i386-asm.S:1.1 src/usr.sbin/cpuctl/arch/i386-asm.S:1.2
--- src/usr.sbin/cpuctl/arch/i386-asm.S:1.1	Mon May  5 17:54:14 2008
+++ src/usr.sbin/cpuctl/arch/i386-asm.S	Sat Jan  5 15:27:45 2013
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386-asm.S,v 1.1 2008/05/05 17:54:14 ad Exp $	*/
+/*	$NetBSD: i386-asm.S,v 1.2 2013/01/05 15:27:45 dsl Exp $	*/
 
 /*-
  * Copyright (c) 1998, 2000, 2004, 2006, 2007 The NetBSD Foundation, Inc.
@@ -30,15 +30,6 @@
 #include machine/cputypes.h
 #include machine/psl.h
 
-	.data
-
-_C_LABEL(cpu):
-	.long	0
-	.globl	_C_LABEL(cpu)
-_C_LABEL(cpu_info_level):
-	.long	-1
-	.globl	_C_LABEL(cpu_info_level)
-
 	.text
 
 ENTRY(x86_cpuid2)
@@ -58,7 +49,6 @@ ENTRY(x86_cpuid2)
 END(x86_cpuid2)
 
 ENTRY(x86_identify)
-	pushl	%ebx
 	/* Try to toggle alignment check flag; does not exist on 386. */
 	pushfl
 	popl	%eax
@@ -91,11 +81,11 @@ isnx586:
 	 * Don't try cpuid, as Nx586s reportedly don't support the
 	 * PSL_ID bit.
 	 */
-	movl	$CPU_NX586,_C_LABEL(cpu)
-	jmp	2f
+	movl	$CPU_NX586,%eax
+	ret
 is386:
-	movl	$CPU_386,_C_LABEL(cpu)
-	jmp	2f
+	movl	$CPU_386,%eax
+	ret
 
 try486:	/* Try to toggle identification flag; does not exist on early 486s. */
 	pushfl
@@ -112,8 +102,13 @@ try486:	/* Try to toggle identification 
 	popfl
 
 	testl	%eax,%eax
-	jnz	try586
-is486:	movl	$CPU_486,_C_LABEL(cpu)
+	jz	is486
+
+	/* Later cpu, caller will use cpuid instruction */
+	movl	$-1,%eax
+	ret
+
+is486:
 	/*
 	 * Check Cyrix CPU
 	 * Cyrix CPUs do not change the undefined flags following
@@ -129,9 +124,11 @@ is486:	movl	$CPU_486,_C_LABEL(cpu)
 	divl	%ecx
 	jnc	trycyrix486
 	popfl
-	jmp 2f
+	movl	$CPU_486,%eax
+	ret
+
 trycyrix486:
-	movl	$CPU_6x86,_C_LABEL(cpu)	# set CPU type
+	popfl
 	/*
 	 * Check for Cyrix 486 CPU by seeing if the flags change during a
 	 * divide. This is documented in the Cx486SLC/e SMM Programmer's
@@ -139,6 +136,7 @@ trycyrix486:
 	 */
 	xorl	%edx,%edx
 	cmpl	%edx,%edx		# set flags to known state
+	pushl	%ebx
 	pushfl
 	popl	%ecx			# store flags in ecx
 	movl	$-1,%eax
@@ -146,15 +144,13 @@ trycyrix486:
 	divl	%ebx			# do a long division
 	pushfl
 	popl	%eax
+	popl	%ebx
 	xorl	%ecx,%eax		# are the flags different?
 	testl	$0x8d5,%eax		# only check C|PF|AF|Z|N|V
-	jne	2f			# yes; must be Cyrix 6x86 CPU
-	movl	$CPU_486DLC,_C_LABEL(cpu)# set CPU type
-	jmp	2f
-try586:	/* Use the `cpuid' instruction. */
-	xorl	%eax,%eax
-	cpuid
-	movl	%eax,_C_LABEL(cpu_info_level)
-2:
-	popl	%ebx
+	je	is486dlc		# yes = must be Cyrix 6x86 CPU
+	movl	$CPU_6x86,%eax
+	ret
+
+is486dlc:
+	movl	$CPU_486DLC,%eax
 	ret

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.33 src/usr.sbin/cpuctl/arch/i386.c:1.34
--- src/usr.sbin/cpuctl/arch/i386.c:1.33	Wed Jan  2 19:24:30 2013
+++ src/usr.sbin/cpuctl/arch/i386.c	Sat Jan  5 15:27:45 2013
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.33 2013/01/02 19:24:30 dsl Exp $	*/
+/*	$NetBSD: i386.c,v 1.34 2013/01/05 15:27:45 dsl Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.33 2013/01/02 19:24:30 dsl Exp $);
+__RCSID($NetBSD: i386.c,v 1.34 2013/01/05 15:27:45 dsl Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -84,18 +84,15 @@ __RCSID($NetBSD: i386.c,v 1.33 2013/01/
 #include x86/cpu_ucode.h
 
 #include ../cpuctl.h
+#include cpuctl_i386.h
 
 /* Size of buffer for printing humanized numbers */
 #define HUMAN_BUFSIZE sizeof(999KB)
 
-#define   x86_cpuid(a,b)  x86_cpuid2((a),0,(b))
-
-void	x86_cpuid2(uint32_t, uint32_t, uint32_t *);
-void	x86_identify(void);
-
 struct cpu_info {
 	const char	*ci_dev;
-	int32_t		ci_cpuid_level;
+	int32_t		ci_cpu_type; /* for cpu's without cpuid */
+	int32_t		ci_cpuid_level;	 /* highest cpuid supported */
 	uint32_t	ci_signature;	 /* X86 cpuid type */
 	uint32_t	ci_feat_val[5];	 /* X86 CPUID feature bits
 	  *	[0] basic features %edx
@@ -985,7 +982,7 @@ amd_amd64_name(struct cpu_info *ci)
 }
 
 static void
-cpu_probe_base_features(struct cpu_info *ci)

CVS commit: src/usr.sbin/cpuctl/arch

2013-01-05 Thread David Laight

Module Name:src
Committed By:   dsl
Date:   Sat Jan  5 15:33:00 UTC 2013

Modified Files:
src/usr.sbin/cpuctl/arch: x86_64-asm.S

Log Message:
Fix x86_identify() for amd64


To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/usr.sbin/cpuctl/arch/x86_64-asm.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/x86_64-asm.S
diff -u src/usr.sbin/cpuctl/arch/x86_64-asm.S:1.2 src/usr.sbin/cpuctl/arch/x86_64-asm.S:1.3
--- src/usr.sbin/cpuctl/arch/x86_64-asm.S:1.2	Sun Oct 19 15:22:17 2008
+++ src/usr.sbin/cpuctl/arch/x86_64-asm.S	Sat Jan  5 15:33:00 2013
@@ -1,4 +1,4 @@
-/*	$NetBSD: x86_64-asm.S,v 1.2 2008/10/19 15:22:17 christos Exp $	*/
+/*	$NetBSD: x86_64-asm.S,v 1.3 2013/01/05 15:33:00 dsl Exp $	*/
 
 /*-
  * Copyright (c) 2007 The NetBSD Foundation, Inc.
@@ -28,15 +28,6 @@
 
 #include machine/asm.h
 
-	.data
-
-_C_LABEL(cpu):
-	.long	0
-	.globl	_C_LABEL(cpu)
-_C_LABEL(cpu_info_level):
-	.long	-1
-	.globl	_C_LABEL(cpu_info_level)
-
 	.text
 
 ENTRY(x86_cpuid2)
@@ -53,8 +44,5 @@ ENTRY(x86_cpuid2)
 	ret
 
 ENTRY(x86_identify)
-	pushq	%rbx
-	cpuid
-	movl	%eax, PIC_GOT(_C_LABEL(cpu_info_level))
-	popq	%rbx
+	movl	$-1,%eax
 	ret

CVS commit: src/usr.sbin/cpuctl/arch

2013-01-05 Thread David Laight

Module Name:src
Committed By:   dsl
Date:   Sat Jan  5 16:38:13 UTC 2013

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
If the IOC_CPU_UCODE_GET_VERSION fails with ENOTTY, try issuing the
request that the amd64 kernel understands.


To generate a diff of this commit:
cvs rdiff -u -r1.34 -r1.35 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.34 src/usr.sbin/cpuctl/arch/i386.c:1.35
--- src/usr.sbin/cpuctl/arch/i386.c:1.34	Sat Jan  5 15:27:45 2013
+++ src/usr.sbin/cpuctl/arch/i386.c	Sat Jan  5 16:38:12 2013
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.34 2013/01/05 15:27:45 dsl Exp $	*/
+/*	$NetBSD: i386.c,v 1.35 2013/01/05 16:38:12 dsl Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.34 2013/01/05 15:27:45 dsl Exp $);
+__RCSID($NetBSD: i386.c,v 1.35 2013/01/05 16:38:12 dsl Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -67,6 +67,7 @@ __RCSID($NetBSD: i386.c,v 1.34 2013/01/
 #include sys/ioctl.h
 #include sys/cpuio.h
 
+#include errno.h
 #include string.h
 #include stdio.h
 #include stdlib.h
@@ -1530,9 +1531,22 @@ identifycpu(int fd, const char *cpuname)
 		ucode.loader_version = CPU_UCODE_LOADER_INTEL1;
 	else
 		return;
+
 	ucode.data = ucvers;
-	if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, ucode)  0)
-		return;
+	if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, ucode)  0) {
+#ifdef __i386__
+		struct cpu_ucode_version_64 ucode_64;
+		if (errno != ENOTTY)
+			return;
+		/* Try the 64 bit ioctl */
+		memset(ucode_64, 0, sizeof ucode_64);
+		ucode_64.data = ucvers;
+		ucode_64.loader_version = ucode.loader_version;
+		if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, ucode_64)  0)
+			return;
+#endif
+	}
+
 	if (cpu_vendor == CPUVENDOR_AMD)
 		printf(%s: UCode version: 0x%PRIx64\n, cpuname, ucvers.amd.version);
 	else if (cpu_vendor == CPUVENDOR_INTEL)

CVS commit: src/usr.sbin/cpuctl/arch

2013-01-05 Thread David Laight

Module Name:src
Committed By:   dsl
Date:   Sat Jan  5 21:16:22 UTC 2013

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
The Intel and AMD docs (more or less) agree on how the cpuid 'extended
  family' and 'extended model' bits are used to create larger values
  than the original 16bit value allowed for.
Calculate and save these values 'up-front' and use them throughout.
Untangle the (backwards) nested switch statement for amd 'model 15' cpus.
Works as badly as ever on my i7.


To generate a diff of this commit:
cvs rdiff -u -r1.35 -r1.36 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.35 src/usr.sbin/cpuctl/arch/i386.c:1.36
--- src/usr.sbin/cpuctl/arch/i386.c:1.35	Sat Jan  5 16:38:12 2013
+++ src/usr.sbin/cpuctl/arch/i386.c	Sat Jan  5 21:16:22 2013
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.35 2013/01/05 16:38:12 dsl Exp $	*/
+/*	$NetBSD: i386.c,v 1.36 2013/01/05 21:16:22 dsl Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.35 2013/01/05 16:38:12 dsl Exp $);
+__RCSID($NetBSD: i386.c,v 1.36 2013/01/05 21:16:22 dsl Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -95,6 +95,8 @@ struct cpu_info {
 	int32_t		ci_cpu_type; /* for cpu's without cpuid */
 	int32_t		ci_cpuid_level;	 /* highest cpuid supported */
 	uint32_t	ci_signature;	 /* X86 cpuid type */
+	uint32_t	ci_family;	 /* from ci_signature */
+	uint32_t	ci_model;	 /* from ci_signature */
 	uint32_t	ci_feat_val[5];	 /* X86 CPUID feature bits
 	  *	[0] basic features %edx
 	  *	[1] basic features %ecx
@@ -660,7 +662,7 @@ cyrix6x86_cpu_setup(struct cpu_info *ci)
 void
 winchip_cpu_setup(struct cpu_info *ci)
 {
-	switch (CPUID2MODEL(ci-ci_signature)) { /* model */
+	switch (ci-ci_model) {
 	case 4:	/* WinChip C6 */
 		disable_tsc(ci);
 	}
@@ -725,7 +727,6 @@ identifycpu_cpuids(struct cpu_info *ci)
 static void
 via_cpu_probe(struct cpu_info *ci)
 {
-	u_int model = CPUID2MODEL(ci-ci_signature);
 	u_int stepping = CPUID2STEPPING(ci-ci_signature);
 	u_int descs[4];
 	u_int lfunc;
@@ -744,7 +745,7 @@ via_cpu_probe(struct cpu_info *ci)
 		ci-ci_feat_val[2] |= descs[3];
 	}
 
-	if (model  0x9 || (model == 0x9  stepping  3))
+	if (ci-ci_model  0x9 || (ci-ci_model == 0x9  stepping  3))
 		return;
 
 	/* Nehemiah or Esther */
@@ -761,11 +762,10 @@ via_cpu_probe(struct cpu_info *ci)
 static const char *
 intel_family6_name(struct cpu_info *ci)
 {
-	int model = CPUID2MODEL(ci-ci_signature);
 	const char *ret = NULL;
 	u_int l2cache = ci-ci_cinfo[CAI_L2CACHE].cai_totalsize;
 
-	if (model == 5) {
+	if (ci-ci_model == 5) {
 		switch (l2cache) {
 		case 0:
 		case 128 * 1024:
@@ -782,14 +782,14 @@ intel_family6_name(struct cpu_info *ci)
 			ret = Pentium II Xeon;
 			break;
 		}
-	} else if (model == 6) {
+	} else if (ci-ci_model == 6) {
 		switch (l2cache) {
 		case 256 * 1024:
 		case 512 * 1024:
 			ret = Mobile Pentium II;
 			break;
 		}
-	} else if (model == 7) {
+	} else if (ci-ci_model == 7) {
 		switch (l2cache) {
 		case 512 * 1024:
 			ret = Pentium III;
@@ -799,7 +799,7 @@ intel_family6_name(struct cpu_info *ci)
 			ret = Pentium III Xeon;
 			break;
 		}
-	} else if (model = 8) {
+	} else if (ci-ci_model = 8) {
 		if (ci-ci_brand_id  ci-ci_brand_id  0x10) {
 			switch (ci-ci_brand_id) {
 			case 0x3:
@@ -836,150 +836,87 @@ intel_family6_name(struct cpu_info *ci)
  * Revision Guide for AMD NPT Family 0Fh Processors
  * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
  * and other miscellaneous reports.
+ *
+ * This is all rather pointless, these are cross 'brand' since the raw
+ * silicon is shared.
  */
 static const char *
 amd_amd64_name(struct cpu_info *ci)
 {
-	int extfamily, extmodel, model;
-	const char *ret = NULL;
+	static char family_str[32];
 
-	model = CPUID2MODEL(ci-ci_signature);
-	extfamily = CPUID2EXTFAMILY(ci-ci_signature);
-	extmodel  = CPUID2EXTMODEL(ci-ci_signature);
-
-	switch (extfamily) {
-	case 0x00:
-		switch (model) {
-		case 0x1:
-			switch (extmodel) {
-			case 0x2:	/* rev JH-E1/E6 */
-			case 0x4:	/* rev JH-F2 */
-ret = Dual-Core Opteron;
-break;
-			}
-			break;
-		case 0x3:
-			switch (extmodel) {
-			case 0x2:	/* rev JH-E6 (Toledo) */
-ret = Dual-Core Opteron or Athlon 64 X2;
-break;
-			case 0x4:	/* rev JH-F2 (Windsor) */
-ret = Athlon 64 FX or Athlon 64 X2;
-break;
-			}
-			break;
-		case 0x4:
-			switch (extmodel) {
-			case 0x0:	/* rev SH-B0/C0/CG (ClawHammer) */
-			case 0x1:	/* rev SH-D0 */
-ret = Athlon 64;
-break;
-			case 0x2:	/* rev SH-E5 (Lancaster?) */
-ret = Mobile Athlon 64 or Turion 64;
-break;
-			}
-			break;
-		case 0x5:
-			switch (extmodel) {
-			case 0x0:	/*

CVS commit: src/usr.sbin/cpuctl/arch

2013-01-02 Thread David Laight

Module Name:src
Committed By:   dsl
Date:   Wed Jan  2 19:24:31 UTC 2013

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
#include sys/ioctl.h


To generate a diff of this commit:
cvs rdiff -u -r1.32 -r1.33 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.32 src/usr.sbin/cpuctl/arch/i386.c:1.33
--- src/usr.sbin/cpuctl/arch/i386.c:1.32	Wed Aug 29 17:13:23 2012
+++ src/usr.sbin/cpuctl/arch/i386.c	Wed Jan  2 19:24:30 2013
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.32 2012/08/29 17:13:23 drochner Exp $	*/
+/*	$NetBSD: i386.c,v 1.33 2013/01/02 19:24:30 dsl Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,13 +57,14 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.32 2012/08/29 17:13:23 drochner Exp $);
+__RCSID($NetBSD: i386.c,v 1.33 2013/01/02 19:24:30 dsl Exp $);
 #endif /* not lint */
 
 #include sys/types.h
 #include sys/param.h
 #include sys/bitops.h
 #include sys/sysctl.h
+#include sys/ioctl.h
 #include sys/cpuio.h
 
 #include string.h

CVS commit: src/usr.sbin/cpuctl/arch

2012-10-17 Thread Matthias Drochner

Module Name:src
Committed By:   drochner
Date:   Wed Oct 17 20:22:16 UTC 2012

Modified Files:
src/usr.sbin/cpuctl/arch: noarch.c

Log Message:
avoid dummy structure definition, include a system header instead,
looks just cleaner


To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/usr.sbin/cpuctl/arch/noarch.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/noarch.c
diff -u src/usr.sbin/cpuctl/arch/noarch.c:1.4 src/usr.sbin/cpuctl/arch/noarch.c:1.5
--- src/usr.sbin/cpuctl/arch/noarch.c:1.4	Fri Aug 31 07:27:27 2012
+++ src/usr.sbin/cpuctl/arch/noarch.c	Wed Oct 17 20:22:15 2012
@@ -1,4 +1,4 @@
-/*	$NetBSD: noarch.c,v 1.4 2012/08/31 07:27:27 drochner Exp $	*/
+/*	$NetBSD: noarch.c,v 1.5 2012/10/17 20:22:15 drochner Exp $	*/
 
 /*-
  * Copyright (c) 2008 The NetBSD Foundation, Inc.
@@ -27,18 +27,15 @@
  */
 
 #include sys/cdefs.h
-#include sys/types.h
 
 #ifndef lint
-__RCSID($NetBSD: noarch.c,v 1.4 2012/08/31 07:27:27 drochner Exp $);
+__RCSID($NetBSD: noarch.c,v 1.5 2012/10/17 20:22:15 drochner Exp $);
 #endif /* not lint */
 
+#include sys/types.h
+#include sys/cpuio.h
 #include stdio.h
 
-struct cpu_ucode {
-	int dummy;
-};
-
 #include ../cpuctl.h
 
 void

CVS commit: src/usr.sbin/cpuctl/arch

2012-04-17 Thread Christoph Egger

Module Name:src
Committed By:   cegger
Date:   Tue Apr 17 13:00:10 UTC 2012

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
print cpu family for AMD CPU families 0x12 - 0x15


To generate a diff of this commit:
cvs rdiff -u -r1.30 -r1.31 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.30 src/usr.sbin/cpuctl/arch/i386.c:1.31
--- src/usr.sbin/cpuctl/arch/i386.c:1.30	Thu Apr  5 11:05:53 2012
+++ src/usr.sbin/cpuctl/arch/i386.c	Tue Apr 17 13:00:09 2012
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.30 2012/04/05 11:05:53 cegger Exp $	*/
+/*	$NetBSD: i386.c,v 1.31 2012/04/17 13:00:09 cegger Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.30 2012/04/05 11:05:53 cegger Exp $);
+__RCSID($NetBSD: i386.c,v 1.31 2012/04/17 13:00:09 cegger Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -959,24 +959,22 @@ amd_amd64_name(struct cpu_info *ci)
 		}
 		break;
 	case 0x01:
-		switch (model) {
-			case 0x02:
-ret = Family 10h;
-break;
-			default:
-ret = Unknown AMD64 CPU;
-break;
-		}
+		ret = Family 10h;
 		break;
 	case 0x02:
-		switch (model) {
-			case 0x03:
-ret = Family 11h;
-break;
-			default:
-ret = Unknown AMD64 CPU;
-break;
-		}
+		ret = Family 11h;
+		break;
+	case 0x03:
+		ret = Family 12h;
+		break;
+	case 0x05:
+		ret = Family 14h;
+		break;
+	case 0x06:
+		ret = Family 15h;
+		break;
+	default:
+		ret = Unknown AMD64 CPU;
 		break;
 	}

CVS commit: src/usr.sbin/cpuctl/arch

2012-04-05 Thread Christoph Egger

Module Name:src
Committed By:   cegger
Date:   Thu Apr  5 11:05:54 UTC 2012

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
report l3 cache information on AMD Family 10h and newer processors


To generate a diff of this commit:
cvs rdiff -u -r1.29 -r1.30 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.29 src/usr.sbin/cpuctl/arch/i386.c:1.30
--- src/usr.sbin/cpuctl/arch/i386.c:1.29	Fri Mar  2 16:29:31 2012
+++ src/usr.sbin/cpuctl/arch/i386.c	Thu Apr  5 11:05:53 2012
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.29 2012/03/02 16:29:31 sborrill Exp $	*/
+/*	$NetBSD: i386.c,v 1.30 2012/04/05 11:05:53 cegger Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.29 2012/03/02 16:29:31 sborrill Exp $);
+__RCSID($NetBSD: i386.c,v 1.30 2012/04/05 11:05:53 cegger Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -1769,9 +1769,9 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
 		cai-cai_associativity = 0;	/* XXX Unknown/reserved */
 
 	/*
-	 * Determine L3 cache info on AMD Family 10h processors
+	 * Determine L3 cache info on AMD Family 10h and newer processors
 	 */
-	if (family == 0x10) {
+	if (family = 0x10) {
 		cai = ci-ci_cinfo[CAI_L3CACHE];
 		cai-cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]);
 		cai-cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]);

CVS commit: src/usr.sbin/cpuctl/arch

2012-03-02 Thread Stephen Borrill

Module Name:src
Committed By:   sborrill
Date:   Fri Mar  2 16:29:31 UTC 2012

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
Print CPU stepping level


To generate a diff of this commit:
cvs rdiff -u -r1.28 -r1.29 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.28 src/usr.sbin/cpuctl/arch/i386.c:1.29
--- src/usr.sbin/cpuctl/arch/i386.c:1.28	Wed Feb 29 23:34:01 2012
+++ src/usr.sbin/cpuctl/arch/i386.c	Fri Mar  2 16:29:31 2012
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.28 2012/02/29 23:34:01 joerg Exp $	*/
+/*	$NetBSD: i386.c,v 1.29 2012/03/02 16:29:31 sborrill Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.28 2012/02/29 23:34:01 joerg Exp $);
+__RCSID($NetBSD: i386.c,v 1.29 2012/03/02 16:29:31 sborrill Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -1517,9 +1517,10 @@ identifycpu(const char *cpuname)
 #endif
 
 	aprint_normal_dev(ci-ci_dev, family %02x model %02x 
-	extfamily %02x extmodel %02x\n, CPUID2FAMILY(ci-ci_signature),
-	CPUID2MODEL(ci-ci_signature), CPUID2EXTFAMILY(ci-ci_signature),
-	CPUID2EXTMODEL(ci-ci_signature));
+	extfamily %02x extmodel %02x stepping %02x\n,
+	CPUID2FAMILY(ci-ci_signature), CPUID2MODEL(ci-ci_signature),
+	CPUID2EXTFAMILY(ci-ci_signature), CPUID2EXTMODEL(ci-ci_signature),
+	CPUID2STEPPING(ci-ci_signature));
 }
 
 static const char *

CVS commit: src/usr.sbin/cpuctl/arch

2012-02-29 Thread Joerg Sonnenberger

Module Name:src
Committed By:   joerg
Date:   Wed Feb 29 23:34:02 UTC 2012

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
Use uintmax_t for freqency computations to avoid differences between
platforms.


To generate a diff of this commit:
cvs rdiff -u -r1.27 -r1.28 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.27 src/usr.sbin/cpuctl/arch/i386.c:1.28
--- src/usr.sbin/cpuctl/arch/i386.c:1.27	Fri Feb  3 05:07:17 2012
+++ src/usr.sbin/cpuctl/arch/i386.c	Wed Feb 29 23:34:01 2012
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.27 2012/02/03 05:07:17 yamt Exp $	*/
+/*	$NetBSD: i386.c,v 1.28 2012/02/29 23:34:01 joerg Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.27 2012/02/03 05:07:17 yamt Exp $);
+__RCSID($NetBSD: i386.c,v 1.28 2012/02/29 23:34:01 joerg Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -1394,9 +1394,9 @@ identifycpu(const char *cpuname)
 	aprint_normal(%s: %s, cpuname, cpu_model);
 
 	if (ci-ci_tsc_freq != 0)
-		aprint_normal(, %qd.%02qd MHz,
-		(ci-ci_tsc_freq + 4999) / 100,
-		((ci-ci_tsc_freq + 4999) / 1) % 100);
+		aprint_normal(, %ju.%02ju MHz,
+		((uintmax_t)ci-ci_tsc_freq + 4999) / 100,
+		(((uintmax_t)ci-ci_tsc_freq + 4999) / 1) % 100);
 	if (ci-ci_signature != 0)
 		aprint_normal(, id 0x%x, ci-ci_signature);
 	aprint_normal(\n);

CVS commit: src/usr.sbin/cpuctl/arch

2012-02-02 Thread YAMAMOTO Takashi

Module Name:src
Committed By:   yamt
Date:   Fri Feb  3 05:07:17 UTC 2012

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
use a correct macro.
releng@ ok


To generate a diff of this commit:
cvs rdiff -u -r1.26 -r1.27 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.26 src/usr.sbin/cpuctl/arch/i386.c:1.27
--- src/usr.sbin/cpuctl/arch/i386.c:1.26	Sun Dec  4 17:00:10 2011
+++ src/usr.sbin/cpuctl/arch/i386.c	Fri Feb  3 05:07:17 2012
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.26 2011/12/04 17:00:10 chs Exp $	*/
+/*	$NetBSD: i386.c,v 1.27 2012/02/03 05:07:17 yamt Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.26 2011/12/04 17:00:10 chs Exp $);
+__RCSID($NetBSD: i386.c,v 1.27 2012/02/03 05:07:17 yamt Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -1694,7 +1694,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
 	cai = ci-ci_cinfo[CAI_DCACHE];
 	cai-cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]);
 	cai-cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]);
-	cai-cai_linesize = AMD_L1_EDX_IC_LS(descs[2]);
+	cai-cai_linesize = AMD_L1_ECX_DC_LS(descs[2]);
 
 	cai = ci-ci_cinfo[CAI_ICACHE];
 	cai-cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]);

CVS commit: src/usr.sbin/cpuctl/arch

2011-05-03 Thread Jukka Ruohonen

Module Name:src
Committed By:   jruoho
Date:   Tue May  3 09:06:22 UTC 2011

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
Identify AMD Family 11h. From PR bin/41188 by FUKAUMI Naoki.


To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.24 src/usr.sbin/cpuctl/arch/i386.c:1.25
--- src/usr.sbin/cpuctl/arch/i386.c:1.24	Sat Feb 19 13:34:38 2011
+++ src/usr.sbin/cpuctl/arch/i386.c	Tue May  3 09:06:22 2011
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.24 2011/02/19 13:34:38 jmcneill Exp $	*/
+/*	$NetBSD: i386.c,v 1.25 2011/05/03 09:06:22 jruoho Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.24 2011/02/19 13:34:38 jmcneill Exp $);
+__RCSID($NetBSD: i386.c,v 1.25 2011/05/03 09:06:22 jruoho Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -967,6 +967,16 @@
 break;
 		}
 		break;
+	case 0x02:
+		switch (model) {
+			case 0x03:
+ret = Family 11h;
+break;
+			default:
+ret = Unknown AMD64 CPU;
+break;
+		}
+		break;
 	}
 
 	return ret;

CVS commit: src/usr.sbin/cpuctl/arch

2011-02-19 Thread Jared D. McNeill

Module Name:src
Committed By:   jmcneill
Date:   Sat Feb 19 13:34:38 UTC 2011

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
fix printing of padlock features


To generate a diff of this commit:
cvs rdiff -u -r1.23 -r1.24 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.23 src/usr.sbin/cpuctl/arch/i386.c:1.24
--- src/usr.sbin/cpuctl/arch/i386.c:1.23	Wed Dec 15 17:09:07 2010
+++ src/usr.sbin/cpuctl/arch/i386.c	Sat Feb 19 13:34:38 2011
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.23 2010/12/15 17:09:07 cegger Exp $	*/
+/*	$NetBSD: i386.c,v 1.24 2011/02/19 13:34:38 jmcneill Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.23 2010/12/15 17:09:07 cegger Exp $);
+__RCSID($NetBSD: i386.c,v 1.24 2011/02/19 13:34:38 jmcneill Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -742,7 +742,7 @@
 		ci-ci_feat_val[2] |= descs[3];
 	}
 
-	if (model  0x9)
+	if (model  0x9 || (model == 0x9  stepping  3))
 		return;
 
 	/* Nehemiah or Esther */
@@ -753,11 +753,7 @@
 
 	x86_cpuid(0xc001, descs);
 	lfunc = descs[3];
-	if (model  0x9 || stepping = 8) {	/* ACE */
-		if (lfunc  CPUID_VIA_HAS_ACE) {
-			ci-ci_feat_val[4] = lfunc;
-		}
-	}
+	ci-ci_feat_val[4] = lfunc;
 }
 
 static const char *
@@ -1414,9 +1410,9 @@
 		feature_str[2] = CPUID_INTEL_EXT_FLAGS;
 		feature_str[3] = CPUID_INTEL_FLAGS4;
 		break;
-	case CPUVENDOR_CYRIX:
+	case CPUVENDOR_IDT:
 		feature_str[4] = CPUID_FLAGS_PADLOCK;
-		/* FALLTHRU */
+		break;
 	default:
 		break;
 	}

CVS commit: src/usr.sbin/cpuctl/arch

2010-12-15 Thread Christoph Egger

Module Name:src
Committed By:   cegger
Date:   Wed Dec 15 17:09:07 UTC 2010

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
beautify printing of SVM features across multiple lines


To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.22 src/usr.sbin/cpuctl/arch/i386.c:1.23
--- src/usr.sbin/cpuctl/arch/i386.c:1.22	Tue Feb 23 08:46:33 2010
+++ src/usr.sbin/cpuctl/arch/i386.c	Wed Dec 15 17:09:07 2010
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.22 2010/02/23 08:46:33 cegger Exp $	*/
+/*	$NetBSD: i386.c,v 1.23 2010/12/15 17:09:07 cegger Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.22 2010/02/23 08:46:33 cegger Exp $);
+__RCSID($NetBSD: i386.c,v 1.23 2010/12/15 17:09:07 cegger Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -1491,9 +1491,14 @@
 			aprint_verbose(%s: SVM Rev. %d\n, cpuname,
 			data[0]  0xf);
 			aprint_verbose(%s: SVM NASID %d\n, cpuname, data[1]);
-			snprintb(buf, sizeof(buf), CPUID_AMD_SVM_FLAGS,
-			data[3]);
-			aprint_verbose(%s: SVM features %s\n, cpuname, buf);
+			snprintb_m(buf, sizeof(buf), CPUID_AMD_SVM_FLAGS,
+   data[3], MAX_FEATURE_LEN);
+			bp = buf;
+			while (*bp != '\0') {
+aprint_verbose(%s: SVM features %s\n,
+cpuname, bp);
+bp += strlen(bp) + 1;
+			}
 		}
 	}

CVS commit: src/usr.sbin/cpuctl/arch

2010-02-23 Thread Christoph Egger

Module Name:src
Committed By:   cegger
Date:   Tue Feb 23 08:46:33 UTC 2010

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
check for svm feature flags if cpuid function 0x800a is available.


To generate a diff of this commit:
cvs rdiff -u -r1.21 -r1.22 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.21 src/usr.sbin/cpuctl/arch/i386.c:1.22
--- src/usr.sbin/cpuctl/arch/i386.c:1.21	Tue Feb 16 00:13:14 2010
+++ src/usr.sbin/cpuctl/arch/i386.c	Tue Feb 23 08:46:33 2010
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.21 2010/02/16 00:13:14 mrg Exp $	*/
+/*	$NetBSD: i386.c,v 1.22 2010/02/23 08:46:33 cegger Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.21 2010/02/16 00:13:14 mrg Exp $);
+__RCSID($NetBSD: i386.c,v 1.22 2010/02/23 08:46:33 cegger Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -1478,10 +1478,14 @@
 #endif
 
 	if (cpu_vendor == CPUVENDOR_AMD) {
-		powernow_probe(ci);
+		uint32_t data[4];
 
-		if ((ci-ci_feat_val[3]  CPUID_SVM) != 0) {
-			uint32_t data[4];
+		x86_cpuid(0x8000, data);
+		if (data[0] = 0x8007)
+			powernow_probe(ci);
+
+		if ((data[0] = 0x800a)
+		(ci-ci_feat_val[3]  CPUID_SVM) != 0) {
 
 			x86_cpuid(0x800a, data);
 			aprint_verbose(%s: SVM Rev. %d\n, cpuname,
@@ -1842,11 +1846,6 @@
 	uint32_t regs[4];
 	char buf[256];
 
-	x86_cpuid(0x8000, regs);
-
-	/* We need CPUID(0x8007) */
-	if (regs[0]  0x8007)
-		return;
 	x86_cpuid(0x8007, regs);
 
 	snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]);

CVS commit: src/usr.sbin/cpuctl/arch

2010-02-15 Thread matthew green

Module Name:src
Committed By:   mrg
Date:   Tue Feb 16 00:13:14 UTC 2010

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
don't call most/all Core2's (Merom).


To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.20 src/usr.sbin/cpuctl/arch/i386.c:1.21
--- src/usr.sbin/cpuctl/arch/i386.c:1.20	Fri Oct  2 13:54:01 2009
+++ src/usr.sbin/cpuctl/arch/i386.c	Tue Feb 16 00:13:14 2010
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.20 2009/10/02 13:54:01 jmcneill Exp $	*/
+/*	$NetBSD: i386.c,v 1.21 2010/02/16 00:13:14 mrg Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.20 2009/10/02 13:54:01 jmcneill Exp $);
+__RCSID($NetBSD: i386.c,v 1.21 2010/02/16 00:13:14 mrg Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -309,7 +309,7 @@
 Pentium III (Tualatin), 0,
 Pentium M (Dothan), 
 Pentium M (Yonah),
-Core 2 (Merom),
+Core 2,
 Pentium Pro, II or III	/* Default */
 			},
 			NULL,

CVS commit: src/usr.sbin/cpuctl/arch

2009-05-14 Thread Paul Goyette

Module Name:src
Committed By:   pgoyette
Date:   Thu May 14 20:16:10 UTC 2009

Modified Files:
src/usr.sbin/cpuctl/arch: i386.c

Log Message:
Add a few more processor extended models for Intel Family 6


To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.18 src/usr.sbin/cpuctl/arch/i386.c:1.19
--- src/usr.sbin/cpuctl/arch/i386.c:1.18	Wed May 13 22:25:51 2009
+++ src/usr.sbin/cpuctl/arch/i386.c	Thu May 14 20:16:10 2009
@@ -1,4 +1,4 @@
-/*	$NetBSD: i386.c,v 1.18 2009/05/13 22:25:51 pgoyette Exp $	*/
+/*	$NetBSD: i386.c,v 1.19 2009/05/14 20:16:10 pgoyette Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include sys/cdefs.h
 #ifndef lint
-__RCSID($NetBSD: i386.c,v 1.18 2009/05/13 22:25:51 pgoyette Exp $);
+__RCSID($NetBSD: i386.c,v 1.19 2009/05/14 20:16:10 pgoyette Exp $);
 #endif /* not lint */
 
 #include sys/types.h
@@ -248,8 +248,8 @@
 	{ /* Extended models 1x */
 	  0x01, { NULL,			NULL,
 		  NULL,			NULL,
-		  NULL,			NULL,
-		  NULL,			NULL,
+		  NULL,			EP80579 Integrated Processor,
+		  Celeron (45nm),	Core 2 Extreme,
 		  NULL,			NULL,
 		  Core i7 (Nehalem),	NULL,
 		  Atom,		XeonMP (Nehalem),

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