CVS commit: src/sys/arch/x86/include

2021-07-10 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Sat Jul 10 17:08:37 UTC 2021

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
Add some definitions from Intel SDM:

 - CPUID leaf 7:0 %ecx bit 13 TME_EN (Total Memory Encryption)
 - CPUID leaf 7:0 %edx bit 18 PCONFIG (Platform CONFIGuration)


To generate a diff of this commit:
cvs rdiff -u -r1.176 -r1.177 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2021-04-30 Thread Christos Zoulas
Module Name:src
Committed By:   christos
Date:   Fri Apr 30 15:37:06 UTC 2021

Added Files:
src/sys/arch/x86/include: gdt.h

Log Message:
merge the i386 and amd64 gdt.h files.


To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1 src/sys/arch/x86/include/gdt.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2021-03-17 Thread NONAKA Kimihiro
Module Name:src
Committed By:   nonaka
Date:   Thu Mar 18 01:50:12 UTC 2021

Modified Files:
src/sys/arch/x86/include: intrdefs.h

Log Message:
LIR_HV priority should be lower than softint.


To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/x86/include/intrdefs.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2021-01-21 Thread Robert Elz
Module Name:src
Committed By:   kre
Date:   Thu Jan 21 09:50:37 UTC 2021

Modified Files:
src/sys/arch/x86/include: bus_defs.h

Log Message:
PRIx (etc) definitions should not include the %

Will fix anything this ends up breaking later.


To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/x86/include/bus_defs.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2020-11-23 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Tue Nov 24 00:46:28 UTC 2020

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
Add some definitions from the latest Intel SDM:

 - Add CPUID leaf 7 %edx bit 23 "KL" (Key Locker).
 - Add CPUID leaf 7 subleaf 1 %eax bit 5 "AVX512_BF16".


To generate a diff of this commit:
cvs rdiff -u -r1.175 -r1.176 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2020-11-15 Thread Manuel Bouyer
Module Name:src
Committed By:   bouyer
Date:   Sun Nov 15 13:59:42 UTC 2020

Modified Files:
src/sys/arch/x86/include: machdep.h

Log Message:
remove unused x86_cpu_initclock_func()


To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/x86/include/machdep.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2020-09-07 Thread Jonathan A. Kollasch
Module Name:src
Committed By:   jakllsch
Date:   Mon Sep  7 13:19:20 UTC 2020

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
Fix printb string for LA57


To generate a diff of this commit:
cvs rdiff -u -r1.174 -r1.175 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2020-09-06 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Mon Sep  7 03:03:09 UTC 2020

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Add CPUID(EAX=07H, ECX=0) ECX bit 16 LA57 from maxv.


To generate a diff of this commit:
cvs rdiff -u -r1.173 -r1.174 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2020-09-04 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Fri Sep  4 17:05:09 UTC 2020

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
Add a few more CPUID flags.


To generate a diff of this commit:
cvs rdiff -u -r1.171 -r1.172 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2020-08-05 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Wed Aug  5 15:40:46 UTC 2020

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
Add new fields here and there.


To generate a diff of this commit:
cvs rdiff -u -r1.170 -r1.171 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2020-07-19 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Mon Jul 20 05:50:56 UTC 2020

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
Revert previous, to unbreak the build (NVMM declares the macro too).

There are hundreds of MSRs, we're not going to list them all, especially
when the majority are unused.


To generate a diff of this commit:
cvs rdiff -u -r1.169 -r1.170 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2020-07-19 Thread Jaromir Dolecek
Module Name:src
Committed By:   jdolecek
Date:   Sun Jul 19 16:17:00 UTC 2020

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
add definition for MSR_IA32_FEATURE_CONTROL, just for information


To generate a diff of this commit:
cvs rdiff -u -r1.168 -r1.169 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2020-06-18 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Thu Jun 18 16:27:24 UTC 2020

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
style and fix typo


To generate a diff of this commit:
cvs rdiff -u -r1.167 -r1.168 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2020-06-09 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Wed Jun 10 03:39:03 UTC 2020

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Add SRBDS_CTRL bit.


To generate a diff of this commit:
cvs rdiff -u -r1.166 -r1.167 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2020-06-01 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Mon Jun  1 08:32:39 UTC 2020

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
Add some definitions from the latest Intel SDM plus small fix:

 - Add CPUID leaf 6 %eax bit 19 for HW_FEEDBACK* and IA32_PACKAGE_TERM* MSRs.
 - Add CPUID leaf 7 %ecx bit 31 for Protection Keys.
 - Add definition of Load only TLB and Store only TLB.
 - Add IF_PSCHANGE_MC_NO bit of IA32_ARCH_CAPABILITIES
 - Fix HWP_IGNIDL.


To generate a diff of this commit:
cvs rdiff -u -r1.165 -r1.166 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2020-05-28 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Thu May 28 07:59:38 UTC 2020

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
Add AMD MSR_DE_CFG's bit 1 as DE_CFG_LFENCE_SERIALIZE.
This bit makes lfence instruction serializing.


To generate a diff of this commit:
cvs rdiff -u -r1.164 -r1.165 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2020-04-30 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Fri May  1 04:07:24 UTC 2020

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
- Add AMD INVLPGB/TLBSYNC hypervisor enable in VMCB and TLBSYNC intercept bit.
- Modify comment.


To generate a diff of this commit:
cvs rdiff -u -r1.163 -r1.164 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2020-04-27 Thread Manuel Bouyer
Module Name:src
Committed By:   bouyer
Date:   Mon Apr 27 16:29:17 UTC 2020

Modified Files:
src/sys/arch/x86/include: cpu.h

Log Message:
Move ci_vcpu under the #ifdef XEN section at the end of the struct cpu_info.
Hopefully will fix the nvmm module.


To generate a diff of this commit:
cvs rdiff -u -r1.122 -r1.123 src/sys/arch/x86/include/cpu.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2020-04-24 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Fri Apr 24 09:49:05 UTC 2020

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
- AMD CPUID Fn8000_000a %edx bit 20 is "SPEC_CTRL".
- Add some bit definitions of AMD's CPUID Fn8000_001f Encrypted Memory
  features.


To generate a diff of this commit:
cvs rdiff -u -r1.161 -r1.162 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2020-04-05 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Mon Apr  6 02:36:49 UTC 2020

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 CPUID Fn0001 %edx bit 8 is printed as "TSC", so rename CPUID Fn8000_0007
%edx bit 8 from "TSC" to "ITSC" (Invariant TSC) to avoid confusion.


To generate a diff of this commit:
cvs rdiff -u -r1.159 -r1.160 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2020-03-13 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Sat Mar 14 04:55:15 UTC 2020

Modified Files:
src/sys/arch/x86/include: pte.h trap.h

Log Message:
style


To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/x86/include/pte.h
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/x86/include/trap.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2019-03-12 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Wed Mar 13 05:22:07 UTC 2019

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
Add TSX_FORCE_ABORT related definitions.


To generate a diff of this commit:
cvs rdiff -u -r1.142 -r1.143 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2019-02-12 Thread Cherry G. Mathew
Module Name:src
Committed By:   cherry
Date:   Wed Feb 13 05:28:50 UTC 2019

Modified Files:
src/sys/arch/x86/include: intr.h

Log Message:
Missed the crucial header file in previous commit.

struct intrstub; is now uniform across native and XEN

This should fix the XEN builds.


To generate a diff of this commit:
cvs rdiff -u -r1.58 -r1.59 src/sys/arch/x86/include/intr.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2019-02-07 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Fri Feb  8 04:06:00 UTC 2019

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Fix bitstring format of Intel CPUID Architectural Performance Monitoring
Fn000a %ebx.


To generate a diff of this commit:
cvs rdiff -u -r1.138 -r1.139 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2019-02-05 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Tue Feb  5 08:07:19 UTC 2019

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Add new CPUID flags WAITPKG, CLDEMOTE, MOVDIRI, MOVDIR64B and
IA32_CORE_CAPABILITIES from the latest Intel SDM.


To generate a diff of this commit:
cvs rdiff -u -r1.137 -r1.138 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2019-01-13 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Sun Jan 13 12:19:09 UTC 2019

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
Forgot to commit file along with identcpu.c::rev1.86.


To generate a diff of this commit:
cvs rdiff -u -r1.136 -r1.137 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-12-13 Thread Cherry G. Mathew
Module Name:src
Committed By:   cherry
Date:   Thu Dec 13 16:16:51 UTC 2018

Modified Files:
src/sys/arch/x86/include: intr.h

Log Message:
Allow x86 builds to have the opportunity to not have pre-emption
enabled by default. This can be effected by having a:

"optionsNO_PREEMPTION"

line in the kernel configuration file.

While it was tempting to tie __HAVE_PREEMPTION to MULTIPROCESSOR,
as is currently assumed in sys/kern/kern_stub.c ,

having MULTIPROCESSOR without __HAVE_PREEMPTION
and not having either are valid configuration options which users
could have choice of. We thus err on the side of configurability.


To generate a diff of this commit:
cvs rdiff -u -r1.56 -r1.57 src/sys/arch/x86/include/intr.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-12-06 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Thu Dec  6 17:26:18 UTC 2018

Modified Files:
src/sys/arch/x86/include: pmap.h

Log Message:
Fix inconsistency, these are indexes and not types, no real functional
change.


To generate a diff of this commit:
cvs rdiff -u -r1.91 -r1.92 src/sys/arch/x86/include/pmap.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-11-25 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Mon Nov 26 04:43:37 UTC 2018

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Add Intel CPUID Architectural Performance Monitoring leaf Fn000a.


To generate a diff of this commit:
cvs rdiff -u -r1.135 -r1.136 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-11-21 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Thu Nov 22 06:14:35 UTC 2018

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Add Intel/AMD MONITOR/MWAIT leaf.


To generate a diff of this commit:
cvs rdiff -u -r1.134 -r1.135 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-11-21 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Wed Nov 21 12:18:53 UTC 2018

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Add Intel CPUID Extended Topology Enumeration Fn000b definitions.


To generate a diff of this commit:
cvs rdiff -u -r1.133 -r1.134 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-11-20 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Wed Nov 21 06:09:49 UTC 2018

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
Modify comment. No functional change:
- AMD also has CPUID 0x06 and 0x0d.
- PCOMMIT was obsoleted.


To generate a diff of this commit:
cvs rdiff -u -r1.132 -r1.133 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-11-14 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Thu Nov 15 03:50:22 UTC 2018

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Add MAWAU (for BND{LD,ST}X instruction) from the latest Intel SDM.


To generate a diff of this commit:
cvs rdiff -u -r1.131 -r1.132 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-07-16 Thread Paul Goyette
Module Name:src
Committed By:   pgoyette
Date:   Mon Jul 16 07:07:30 UTC 2018

Modified Files:
src/sys/arch/x86/include: cpu.h

Log Message:
More rearrangement of struct cpu_info to keep all the un-conditional
members at fixed locations.

Should address my PR kern/52919

OK maxv@

XXX kernel version bump coming momentarily.


To generate a diff of this commit:
cvs rdiff -u -r1.95 -r1.96 src/sys/arch/x86/include/cpu.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-07-15 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Sun Jul 15 08:47:43 UTC 2018

Modified Files:
src/sys/arch/x86/include: cpu.h

Log Message:
Hum. Move the __HAVE_DIRECT_MAP block a little below, otherwise dynamically
loaded kernel modules use a wrong offset for some ci_* fields. Found when
modloading tprof_amd on an AMD 10h, the read of ci_signature was at a
wrong address, and the cpu family was not detected correctly.


To generate a diff of this commit:
cvs rdiff -u -r1.94 -r1.95 src/sys/arch/x86/include/cpu.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-05-30 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Thu May 31 03:29:01 UTC 2018

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Fix the bit location of SSBD in the macro for snprintb.


To generate a diff of this commit:
cvs rdiff -u -r1.125 -r1.126 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-05-23 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Wed May 23 07:24:38 UTC 2018

Modified Files:
src/sys/arch/x86/include: cpu_extended_state.h specialreg.h

Log Message:
Clean up the FPU headers.


To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/x86/include/cpu_extended_state.h
cvs rdiff -u -r1.124 -r1.125 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-05-22 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Tue May 22 07:24:08 UTC 2018

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
Add RSBA. When set, it indicates that the CPU is vulnerable to SpectreV2
via the RSB.


To generate a diff of this commit:
cvs rdiff -u -r1.121 -r1.122 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-05-19 Thread Jonathan A. Kollasch
Module Name:src
Committed By:   jakllsch
Date:   Sat May 19 16:55:59 UTC 2018

Modified Files:
src/sys/arch/x86/include: pmap.h

Log Message:
remove some remaining uvm_emap(9)-related function prototypes


To generate a diff of this commit:
cvs rdiff -u -r1.78 -r1.79 src/sys/arch/x86/include/pmap.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-04-13 Thread NONAKA Kimihiro
Module Name:src
Committed By:   nonaka
Date:   Fri Apr 13 11:24:34 UTC 2018

Modified Files:
src/sys/arch/x86/include: bootinfo.h

Log Message:
x86: Increase BOOTINFO_MAXSIZE to 8Kib.

Proposed on port-i386 and port-amd64 with no objections:
http://mail-index.netbsd.org/port-i386/2018/04/11/msg003692.html
http://mail-index.netbsd.org/port-amd64/2018/04/11/msg002697.html


To generate a diff of this commit:
cvs rdiff -u -r1.28 -r1.29 src/sys/arch/x86/include/bootinfo.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-03-30 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Fri Mar 30 19:49:49 UTC 2018

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
Add RDCL_NO and IBRS_ALL.


To generate a diff of this commit:
cvs rdiff -u -r1.119 -r1.120 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-03-30 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Fri Mar 30 09:30:57 UTC 2018

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
Add Some bit definitions of AMD Fn8001 %edx:
 - MMX
 - FXSR


To generate a diff of this commit:
cvs rdiff -u -r1.118 -r1.119 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-03-30 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Fri Mar 30 09:28:37 UTC 2018

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
>From the latest Intel SDM:
- Add Intel Fn_0006 %eax new bit 14-20 (HWP stuff).
- Intel Fn_0007 %ecx bit 22 is for both RDPID and IA32_TSC_AUX.


To generate a diff of this commit:
cvs rdiff -u -r1.117 -r1.118 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-03-14 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Wed Mar 14 15:03:16 UTC 2018

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
... and also add IBPB ...


To generate a diff of this commit:
cvs rdiff -u -r1.116 -r1.117 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-03-14 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Wed Mar 14 14:44:25 UTC 2018

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
Add the IBRS and STIBP MSRs.


To generate a diff of this commit:
cvs rdiff -u -r1.115 -r1.116 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-03-14 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Wed Mar 14 14:15:02 UTC 2018

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
Add IC_CFG.DIS_IND: "Disable Indirect Branch Predictor". Available (at
least) on AMD Families 10h, 12h and 16h.


To generate a diff of this commit:
cvs rdiff -u -r1.114 -r1.115 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-03-12 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Mon Mar 12 07:35:45 UTC 2018

Modified Files:
src/sys/arch/x86/include: cacheinfo.h

Log Message:
 AMD L3 cache association bitfield is not 8bit but 4bit like others association
bitfields.


To generate a diff of this commit:
cvs rdiff -u -r1.25 -r1.26 src/sys/arch/x86/include/cacheinfo.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-03-11 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Mon Mar 12 06:20:33 UTC 2018

Modified Files:
src/sys/arch/x86/include: cacheinfo.h

Log Message:
 Add 3way and 6way of L2 cache or TLB on AMD CPU.


To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/x86/include/cacheinfo.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-03-07 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Thu Mar  8 04:15:11 UTC 2018

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Sort entries. No functional change.


To generate a diff of this commit:
cvs rdiff -u -r1.112 -r1.113 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-03-04 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Mon Mar  5 05:44:07 UTC 2018

Modified Files:
src/sys/arch/x86/include: cacheinfo.h specialreg.h

Log Message:
Add Intel Deterministic Address Translation Parameter Leaf(0x18) definitions.


To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/x86/include/cacheinfo.h
cvs rdiff -u -r1.111 -r1.112 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-02-17 Thread Kamil Rytarowski
Module Name:src
Committed By:   kamil
Date:   Sat Feb 17 13:01:23 UTC 2018

Modified Files:
src/sys/arch/x86/include: Makefile

Log Message:
Stop installing dbregs.h

This is now kernel-only header. The behavior is well specified by the CPU
documents and we don't introduce changes to it.

Noted by 


To generate a diff of this commit:
cvs rdiff -u -r1.21 -r1.22 src/sys/arch/x86/include/Makefile

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-01-15 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Mon Jan 15 08:17:20 UTC 2018

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Add IA32_SPEC_CTRL MSR and IA32_PRED_CMD MSR.


To generate a diff of this commit:
cvs rdiff -u -r1.110 -r1.111 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-01-14 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Mon Jan 15 07:19:00 UTC 2018

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Add MSR_IA32_ARCH_CAPABILITIES definition.


To generate a diff of this commit:
cvs rdiff -u -r1.109 -r1.110 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-01-14 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Mon Jan 15 06:08:41 UTC 2018

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
- Add Intel cpuid 7 %edx bit 29 IA32_ARCH_CAPABILITIES supported bit.
- Add comment.


To generate a diff of this commit:
cvs rdiff -u -r1.108 -r1.109 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-01-13 Thread Jaromir Dolecek
Module Name:src
Committed By:   jdolecek
Date:   Sat Jan 13 17:55:57 UTC 2018

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
fix swapped comments for EFER LME and LMA


To generate a diff of this commit:
cvs rdiff -u -r1.107 -r1.108 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-01-09 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Wed Jan 10 07:04:54 UTC 2018

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Add Intel cpuid 7 %edx IBRS(IBPB Speculation Control) and
STIBP(STIBP Speculation Control) from OpenBSD.


To generate a diff of this commit:
cvs rdiff -u -r1.106 -r1.107 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2018-01-09 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Wed Jan 10 04:45:24 UTC 2018

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Add comment.


To generate a diff of this commit:
cvs rdiff -u -r1.105 -r1.106 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-12-28 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Thu Dec 28 08:30:36 UTC 2017

Modified Files:
src/sys/arch/x86/include: cpu.h

Log Message:
typos


To generate a diff of this commit:
cvs rdiff -u -r1.83 -r1.84 src/sys/arch/x86/include/cpu.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-12-02 Thread Christos Zoulas
Module Name:src
Committed By:   christos
Date:   Sat Dec  2 21:04:59 UTC 2017

Modified Files:
src/sys/arch/x86/include: cpu.h

Log Message:
Add padding to make the 32/64 bit structs the same.


To generate a diff of this commit:
cvs rdiff -u -r1.82 -r1.83 src/sys/arch/x86/include/cpu.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-11-27 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Mon Nov 27 09:10:12 UTC 2017

Modified Files:
src/sys/arch/x86/include: cpu.h

Log Message:
Remove unused fields, there is no alignment we need to enforce.


To generate a diff of this commit:
cvs rdiff -u -r1.81 -r1.82 src/sys/arch/x86/include/cpu.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-11-08 Thread Christos Zoulas
Module Name:src
Committed By:   christos
Date:   Thu Nov  9 01:01:33 UTC 2017

Modified Files:
src/sys/arch/x86/include: bootinfo.h

Log Message:
add "prekern" to the string list.


To generate a diff of this commit:
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/x86/include/bootinfo.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-11-08 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Wed Nov  8 17:55:54 UTC 2017

Modified Files:
src/sys/arch/x86/include: cpu_extended_state.h

Log Message:
remove vestige


To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/x86/include/cpu_extended_state.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-10-31 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Tue Oct 31 18:30:36 UTC 2017

Modified Files:
src/sys/arch/x86/include: cpu_extended_state.h

Log Message:
Remove outdated comment.


To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/x86/include/cpu_extended_state.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-10-31 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Tue Oct 31 10:39:13 UTC 2017

Modified Files:
src/sys/arch/x86/include: cpu_extended_state.h

Log Message:
Add xsh_xcomp_bv and fx_zero, and use uint8_t instead.


To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/x86/include/cpu_extended_state.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-10-18 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Thu Oct 19 06:29:16 UTC 2017

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Add the following bits in AMD Fn800a %edx features (SVM features):
PFThreshold (PAUSE filter threshold)
AVIC (AMD virtual interrupt controller)
V_VMSAVE_VMLOAD (virtualized VMSAVE and VMLOAD)
vGIF (virtualized GIF)


To generate a diff of this commit:
cvs rdiff -u -r1.104 -r1.105 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-10-17 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Wed Oct 18 03:38:32 UTC 2017

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Add Turbo Boost Max Technology 3.0 bit.


To generate a diff of this commit:
cvs rdiff -u -r1.103 -r1.104 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-10-13 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Fri Oct 13 13:53:54 UTC 2017

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Add the following instruction bits in Structured Extended Flags Enumeration
Leaf from "Intel Architecture Instruction Set Extensions and Future Features
Programming Reference" (319433-030):
AVX512_IFMA
AVX512_VBMI
AVX512_VBMI2
GFNI
VAES
VPCLMULQDQ
AVX512_VNNI
AVX512_BITALG
AVX512_VPOPCNTDQ
AVX512_4VNNIW
AVX512_4FMAPS


To generate a diff of this commit:
cvs rdiff -u -r1.102 -r1.103 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-09-28 Thread Ryota Ozaki
Module Name:src
Committed By:   ozaki-r
Date:   Fri Sep 29 03:17:18 UTC 2017

Modified Files:
src/sys/arch/x86/include: pmap.h

Log Message:
Fix build

sys/arch/x86/x86/cpu.c:920:20: error: 'pmap_largepages' undeclared (first use 
in this function)
  smp_data.large = (pmap_largepages != 0);
^


To generate a diff of this commit:
cvs rdiff -u -r1.67 -r1.68 src/sys/arch/x86/include/pmap.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-09-16 Thread Christos Zoulas
Module Name:src
Committed By:   christos
Date:   Sat Sep 16 23:55:45 UTC 2017

Modified Files:
src/sys/arch/x86/include: lock.h

Log Message:
more const


To generate a diff of this commit:
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/x86/include/lock.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-08-12 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Sat Aug 12 12:33:31 UTC 2017

Modified Files:
src/sys/arch/x86/include: psl.h

Log Message:
Don't include opt_vm86.h.


To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/x86/include/psl.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-08-10 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Fri Aug 11 06:27:12 UTC 2017

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
Add a comment about APICBASE_PHYSADDR. Has to do with PR/42597.


To generate a diff of this commit:
cvs rdiff -u -r1.100 -r1.101 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-08-10 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Thu Aug 10 12:46:31 UTC 2017

Modified Files:
src/sys/arch/x86/include: cpu_extended_state.h

Log Message:
Remove the svr4/ibcs2 fpu flags.


To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/x86/include/cpu_extended_state.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-07-11 Thread Andreas Gustafsson
Module Name:src
Committed By:   gson
Date:   Tue Jul 11 14:00:16 UTC 2017

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
Fix typo in comment


To generate a diff of this commit:
cvs rdiff -u -r1.99 -r1.100 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-06-17 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Sat Jun 17 08:07:03 UTC 2017

Modified Files:
src/sys/arch/x86/include: pmap.h

Log Message:
Actually, use slot 456 instead, so that it fits a cache line.


To generate a diff of this commit:
cvs rdiff -u -r1.66 -r1.67 src/sys/arch/x86/include/pmap.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-06-14 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Wed Jun 14 12:49:37 UTC 2017

Modified Files:
src/sys/arch/x86/include: pmap.h

Log Message:
Move the direct map from slot 509 to slot 460. We will increase its size
dynamically.


To generate a diff of this commit:
cvs rdiff -u -r1.64 -r1.65 src/sys/arch/x86/include/pmap.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-06-14 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Wed Jun 14 08:45:42 UTC 2017

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
Add EFER_TCE. This would be an interesting feature to have, since it
reduces the indirect cost of invlpg; but I'm not convinced the way we
flush upper-levels is correct for this yet.


To generate a diff of this commit:
cvs rdiff -u -r1.98 -r1.99 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-05-14 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Mon May 15 04:02:52 UTC 2017

Modified Files:
src/sys/arch/x86/include: cpu.h specialreg.h

Log Message:
 CPUID_CFLUSH bit is not for CFLUSH insn but CLFLUSH insn, so modify comments
and snprintb() sring.


To generate a diff of this commit:
cvs rdiff -u -r1.69 -r1.70 src/sys/arch/x86/include/cpu.h
cvs rdiff -u -r1.97 -r1.98 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-04-27 Thread NONAKA Kimihiro
Module Name:src
Committed By:   nonaka
Date:   Fri Apr 28 01:23:58 UTC 2017

Modified Files:
src/sys/arch/x86/include: i82489reg.h

Log Message:
Added AMD extended APIC register space present definition.


To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/x86/include/i82489reg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-04-21 Thread NONAKA Kimihiro
Module Name:src
Committed By:   nonaka
Date:   Sat Apr 22 04:25:09 UTC 2017

Modified Files:
src/sys/arch/x86/include: i82093reg.h

Log Message:
Added I/O APIC EOI register definition.


To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/x86/include/i82093reg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-04-21 Thread NONAKA Kimihiro
Module Name:src
Committed By:   nonaka
Date:   Sat Apr 22 04:23:17 UTC 2017

Modified Files:
src/sys/arch/x86/include: i82489reg.h specialreg.h

Log Message:
Add x2APIC register definitions.


To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/x86/include/i82489reg.h
cvs rdiff -u -r1.95 -r1.96 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-04-18 Thread NONAKA Kimihiro
Module Name:src
Committed By:   nonaka
Date:   Wed Apr 19 06:43:05 UTC 2017

Modified Files:
src/sys/arch/x86/include: cpuvar.h i82489var.h

Log Message:
remove prototypes of nonexistent function.


To generate a diff of this commit:
cvs rdiff -u -r1.48 -r1.49 src/sys/arch/x86/include/cpuvar.h
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/x86/include/i82489var.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-03-05 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Sun Mar  5 09:08:18 UTC 2017

Modified Files:
src/sys/arch/x86/include: pmap.h

Log Message:
Remove PG_u from the kernel pages on Xen. Otherwise there is no privilege
separation between the kernel and userland.

On Xen-amd64, the kernel runs in ring3 just like userland, and the
separation is guaranteed by the hypervisor - each syscall/trap is
intercepted by Xen and sent manually to the kernel. Before that, the
hypervisor modifies the page tables so that the kernel becomes accessible.
Later, when returning to userland, the hypervisor removes the kernel pages
and flushes the TLB.

However, TLB flushes are costly, and in order to reduce the number of pages
flushed Xen marks the userland pages as global, while keeping the kernel
ones as local. This way, when returning to userland, only the kernel pages
get flushed - which makes sense since they are the only ones that got
removed from the mapping.

Xen differentiates the userland pages by looking at their PG_u bit in the
PTE; if a page has this bit then Xen tags it as global, otherwise Xen
manually adds the bit but keeps the page as local. The thing is, since we
set PG_u in the kernel pages, Xen believes our kernel pages are in fact
userland pages, so it marks them as global. Therefore, when returning to
userland, the kernel pages indeed get removed from the page tree, but are
not flushed from the TLB. Which means that they are still accessible.

With this - and depending on the DTLB size - userland has a small window
where it can read/write to the last kernel pages accessed, which is enough
to completely escalate privileges: the sysent structure systematically gets
read when performing a syscall, and chances are that it will still be
cached in the TLB. Userland can then use this to patch a chosen syscall,
make it point to a userland function, retrieve %gs and compute the address
of its credentials, and finally grant itself root privileges.


To generate a diff of this commit:
cvs rdiff -u -r1.62 -r1.63 src/sys/arch/x86/include/pmap.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-02-18 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Sat Feb 18 16:15:51 UTC 2017

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
Add the AMD 10h family PMC values. Some values depend on the CPU revision,
they are commented out. Several other values are common with K7, we could
merge them later.

This family of CPUs has a 12bit event selector, contrary to K7 (8bit). The
thing is, i386's PMC interface takes as argument a uint8_t from userland,
so these counters are not accessible (yet).


To generate a diff of this commit:
cvs rdiff -u -r1.93 -r1.94 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-02-14 Thread NONAKA Kimihiro
Module Name:src
Committed By:   nonaka
Date:   Tue Feb 14 13:25:22 UTC 2017

Modified Files:
src/sys/arch/x86/include: bootinfo.h

Log Message:
x86: add e820 memory type.


To generate a diff of this commit:
cvs rdiff -u -r1.25 -r1.26 src/sys/arch/x86/include/bootinfo.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-02-11 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Sat Feb 11 15:11:45 UTC 2017

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
Fix a few (unused) MSR values, and add some others that I believe are
relevant.

>From Murray Armfield (PR/42861).


To generate a diff of this commit:
cvs rdiff -u -r1.92 -r1.93 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-02-01 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Thu Feb  2 05:43:48 UTC 2017

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Modify comment. Use long form.


To generate a diff of this commit:
cvs rdiff -u -r1.91 -r1.92 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2017-01-12 Thread Christos Zoulas
Module Name:src
Committed By:   christos
Date:   Fri Jan 13 05:26:42 UTC 2017

Modified Files:
src/sys/arch/x86/include: cpuvar.h

Log Message:
Add missing forward decl.


To generate a diff of this commit:
cvs rdiff -u -r1.47 -r1.48 src/sys/arch/x86/include/cpuvar.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2016-12-07 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Thu Dec  8 06:11:03 UTC 2016

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
Add CLWB bit.


To generate a diff of this commit:
cvs rdiff -u -r1.90 -r1.91 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2016-12-04 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Mon Dec  5 03:59:47 UTC 2016

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
Fix CPUID_SEF_FLAGS. Octal value has no 8.


To generate a diff of this commit:
cvs rdiff -u -r1.89 -r1.90 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2016-08-19 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Fri Aug 19 18:53:29 UTC 2016

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
KNF so NXR likes it, and some typos


To generate a diff of this commit:
cvs rdiff -u -r1.88 -r1.89 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2016-08-18 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Thu Aug 18 13:00:54 UTC 2016

Modified Files:
src/sys/arch/x86/include: cpu_extended_state.h

Log Message:
KNF and simplify.


To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/x86/include/cpu_extended_state.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2016-07-16 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Sat Jul 16 13:47:01 UTC 2016

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
Add the cr4 flags for PKE and UMIP.


To generate a diff of this commit:
cvs rdiff -u -r1.87 -r1.88 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2016-04-27 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Wed Apr 27 08:51:32 UTC 2016

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
Add some bit definitions mainly taken from the latest Intel SDM:
 - Add SGX, UMIP, RDPID and SGXLC.
 - Add avx512dq, avx512bw and avx512vl.
Fix the bit location of CLFLUSHOPT.


To generate a diff of this commit:
cvs rdiff -u -r1.86 -r1.87 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2016-04-27 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Wed Apr 27 08:47:03 UTC 2016

Modified Files:
src/sys/arch/x86/include: cacheinfo.h

Log Message:
Add new desc 0x64 and 0xc4.


To generate a diff of this commit:
cvs rdiff -u -r1.21 -r1.22 src/sys/arch/x86/include/cacheinfo.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2016-01-12 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Wed Jan 13 07:19:29 UTC 2016

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Add some AMD's bit definitions from "BIOS and Kernel Developer(BKDG) for AMD
Family 15h Models 60h-6Fh Processors".


To generate a diff of this commit:
cvs rdiff -u -r1.85 -r1.86 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2016-01-07 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Fri Jan  8 03:26:35 UTC 2016

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Add CLFLUSHOPT bit.


To generate a diff of this commit:
cvs rdiff -u -r1.84 -r1.85 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2016-01-07 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Fri Jan  8 02:27:08 UTC 2016

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Add x86 FPU Data Pointer Updated Only bit from Intel SDM.


To generate a diff of this commit:
cvs rdiff -u -r1.83 -r1.84 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2016-01-07 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Fri Jan  8 02:25:15 UTC 2016

Modified Files:
src/sys/arch/x86/include: cacheinfo.h

Log Message:
 Index 0x6c is not 126 entries but 128 entries. The old value was from
previous SDM.


To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/x86/include/cacheinfo.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2015-10-18 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Mon Oct 19 02:45:26 UTC 2015

Modified Files:
src/sys/arch/x86/include: cacheinfo.h

Log Message:
 Add some TLB entries from the latest Intel SDM. This change might incorrect
because the document itself is very strange.


To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/x86/include/cacheinfo.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2015-08-13 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Fri Aug 14 06:54:22 UTC 2015

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 - Add Hardware-Controlled Performance States (HWP) bits.
 - Use __BIT()


To generate a diff of this commit:
cvs rdiff -u -r1.82 -r1.83 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



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