On Fri, Apr 14, 2023 at 10:26:14AM +0800, Kevin Lo wrote:
> On Thu, Apr 13, 2023 at 01:30:36PM -0500, Brian Conway wrote:
> > Reviving this thread, apologies for discontinuity in mail readers:
> > https://marc.info/?t=16564219358
> >
> > After rebasing on 7.3, my results have mirrored
On Thu, Apr 13, 2023 at 01:30:36PM -0500, Brian Conway wrote:
>
> Reviving this thread, apologies for discontinuity in mail readers:
> https://marc.info/?t=16564219358
>
> After rebasing on 7.3, my results have mirrored Hrvoje's testing at the end
> of that thread. No issues with
On 2023/04/13 16:45, Sonic wrote:
> Is this multiqueue support in 7.3 or does it require patching?
> According to Intel the i211 should have 2 queues but I see no msi-x
> support in dmesg:
> em0 at pci1 dev 0 function 0 "Intel I211" rev 0x03: msi, address
It is not committed, there's a diff.
Is this multiqueue support in 7.3 or does it require patching?
According to Intel the i211 should have 2 queues but I see no msi-x
support in dmesg:
em0 at pci1 dev 0 function 0 "Intel I211" rev 0x03: msi, address
Thanks.
Chris
On Thu, Apr 13, 2023, at 2:45 PM, Stuart Henderson wrote:
> On 2023/04/13 13:30, Brian Conway wrote:
>> Reviving this thread, apologies for discontinuity in mail readers:
>> https://marc.info/?t=16564219358
>>
>> After rebasing on 7.3, my results have mirrored Hrvoje's testing at the end
>>
On 2023/04/13 13:30, Brian Conway wrote:
> Reviving this thread, apologies for discontinuity in mail readers:
> https://marc.info/?t=16564219358
>
> After rebasing on 7.3, my results have mirrored Hrvoje's testing at the end
> of that thread. No issues with throughput, unusual latency, or
Reviving this thread, apologies for discontinuity in mail readers:
https://marc.info/?t=16564219358
After rebasing on 7.3, my results have mirrored Hrvoje's testing at the end of
that thread. No issues with throughput, unusual latency, or reliability.
`vmstat -i` shows some level of
On 15.8.2022. 20:51, Hrvoje Popovski wrote:
> On 12.8.2022. 22:15, Hrvoje Popovski wrote:
>> Hi,
>>
>> I'm testing forwarding over
>>
>> em0 at pci7 dev 0 function 0 "Intel 82576" rev 0x01, msix, 4 queues,
>> em1 at pci7 dev 0 function 1 "Intel 82576" rev 0x01, msix, 4 queues,
>> em2 at pci8 dev 0
On 12.8.2022. 22:15, Hrvoje Popovski wrote:
> Hi,
>
> I'm testing forwarding over
>
> em0 at pci7 dev 0 function 0 "Intel 82576" rev 0x01, msix, 4 queues,
> em1 at pci7 dev 0 function 1 "Intel 82576" rev 0x01, msix, 4 queues,
> em2 at pci8 dev 0 function 0 "Intel I210" rev 0x03, msix, 4 queues,
On 28.6.2022. 15:11, Jonathan Matthew wrote:
> This adds the (not quite) final bits to em(4) to enable multiple rx/tx queues.
> Note that desktop/laptop models (I218, I219 etc.) do not support multiple
> queues,
> so this only really applies to servers and network appliances (including
> APU2).
> On 2 Jul 2022, at 08:44, Hrvoje Popovski wrote:
>
> On 28.6.2022. 15:11, Jonathan Matthew wrote:
>> This adds the (not quite) final bits to em(4) to enable multiple rx/tx
>> queues.
>> Note that desktop/laptop models (I218, I219 etc.) do not support multiple
>> queues,
>> so this only
On 28.6.2022. 15:11, Jonathan Matthew wrote:
> This adds the (not quite) final bits to em(4) to enable multiple rx/tx queues.
> Note that desktop/laptop models (I218, I219 etc.) do not support multiple
> queues,
> so this only really applies to servers and network appliances (including
> APU2).
On 2022/06/29 13:19, Stuart Henderson wrote:
> On 2022/06/28 23:11, Jonathan Matthew wrote:
> > This adds the (not quite) final bits to em(4) to enable multiple rx/tx
> > queues.
> > Note that desktop/laptop models (I218, I219 etc.) do not support multiple
> > queues,
> > so this only really
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