Re: cpu.4: VIA C7 CPUs support Enhanced SpeedStep (i386)
On Tue, Jun 05, 2018 at 10:04:52PM +1000, Jonathan Gray wrote:
> > VIA C7 CPUs support Enhanced SpeedStep, so reflect that in cpu.4.
> >
> > On the VIA C7 1.5Ghz:
> >
> > cpu0: VIA Esther processor 1500MHz ("CentaurHauls" 686-class) 1.51 GHz
> > cpu0:
> > FPU,V86,DE,PSE,TSC,MSR,PAE,MCE,APIC,SEP,MTRR,PGE,CMOV,PAT,CFLUSH,ACPI,MMX,FXSR,SSE,SSE2,TM,PBE,NXE,SSE3,EST,TM2
> > cpu0: Enhanced SpeedStep 1501 MHz: speeds: 1500, 800 MHz
>
> If you just have the faked high/low table does it really support it
> besides setting the cpuid bit? No PSS in ACPI? There is a table
> for a 1.5GHz C7 in i386
>
> /* 1.50GHz Centaur C7-M 400 MHz FSB */
> static struct est_op C7M_754[] = {
> ID16(1500, 1004, BUS100),
> ID16(1400, 988, BUS100),
> ID16(1000, 940, BUS100),
> ID16( 800, 844, BUS100),
> ID16( 600, 844, BUS100),
> ID16( 400, 844, BUS100),
> };
Sorry for the delay, I wanted to try booting an old VIA C7 motherboard
I have (the dmesg bits from previous mail came from our dmesg archive)
before answering.
I finally was able to find it and do so, and indeed it seems there are
some issues as well:
cpu0: VIA C7 Processor 1000MHz ("CentaurHauls" 686-class) 1 GHz
cpu0:
FPU,V86,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,CMOV,PAT,CFLUSH,ACPI,MMX,FXSR,SSE,SSE2,TM,PBE,NXE,SSE3,EST,TM2,xTPR
cpu0: unknown Enhanced SpeedStep CPU, msr 0x08100a1308000a13
cpu0: using only highest and lowest power states
cpu0: Enhanced SpeedStep 998 MHz: speeds: 1333, 1067 MHz
I'm not sure it makes sense to spend any time on this, let's forget it.
Re: cpu.4: VIA C7 CPUs support Enhanced SpeedStep (i386)
On Tue, Jun 05, 2018 at 11:11:21AM +0200, Frederic Cambus wrote:
> Hi tech@,
>
> VIA C7 CPUs support Enhanced SpeedStep, so reflect that in cpu.4.
>
> On the VIA C7 1.5Ghz:
>
> cpu0: VIA Esther processor 1500MHz ("CentaurHauls" 686-class) 1.51 GHz
> cpu0:
> FPU,V86,DE,PSE,TSC,MSR,PAE,MCE,APIC,SEP,MTRR,PGE,CMOV,PAT,CFLUSH,ACPI,MMX,FXSR,SSE,SSE2,TM,PBE,NXE,SSE3,EST,TM2
> cpu0: Enhanced SpeedStep 1501 MHz: speeds: 1500, 800 MHz
>
> Comments? OK?
If you just have the faked high/low table does it really support it
besides setting the cpuid bit? No PSS in ACPI? There is a table
for a 1.5GHz C7 in i386
/* 1.50GHz Centaur C7-M 400 MHz FSB */
static struct est_op C7M_754[] = {
ID16(1500, 1004, BUS100),
ID16(1400, 988, BUS100),
ID16(1000, 940, BUS100),
ID16( 800, 844, BUS100),
ID16( 600, 844, BUS100),
ID16( 400, 844, BUS100),
};
VIA seems to refer to changing the frequency on C7 as 'Enhanced PowerSaver'.
>
> Index: share/man/man4/man4.i386/cpu.4
> ===
> RCS file: /cvs/src/share/man/man4/man4.i386/cpu.4,v
> retrieving revision 1.18
> diff -u -p -r1.18 cpu.4
> --- share/man/man4/man4.i386/cpu.412 Jan 2018 04:36:44 - 1.18
> +++ share/man/man4/man4.i386/cpu.45 Jun 2018 08:39:38 -
> @@ -53,8 +53,8 @@ positions.
> The processor dynamically adjusts frequency in response to load; the setperf
> value is interpreted as the maximum.
> .It EST
> -Enhanced SpeedStep found on Intel Pentium M processors,
> -offering frequency scaling with numerous positions.
> +Enhanced SpeedStep found on Intel Pentium M and newer processors, as well as
> +on VIA C7 processors, offering frequency scaling with numerous positions.
> .It SpeedStep
> Found on some Intel Pentium 3 and newer mobile chips,
> it is capable of adjusting frequency between a low and high value.
>
Re: cpu.4: VIA C7 CPUs support Enhanced SpeedStep (i386)
On Tue, Jun 05, 2018 at 11:11:21AM +0200, Frederic Cambus wrote:
> Hi tech@,
>
> VIA C7 CPUs support Enhanced SpeedStep, so reflect that in cpu.4.
>
> On the VIA C7 1.5Ghz:
>
> cpu0: VIA Esther processor 1500MHz ("CentaurHauls" 686-class) 1.51 GHz
> cpu0:
> FPU,V86,DE,PSE,TSC,MSR,PAE,MCE,APIC,SEP,MTRR,PGE,CMOV,PAT,CFLUSH,ACPI,MMX,FXSR,SSE,SSE2,TM,PBE,NXE,SSE3,EST,TM2
> cpu0: Enhanced SpeedStep 1501 MHz: speeds: 1500, 800 MHz
>
> Comments? OK?
>
> Index: share/man/man4/man4.i386/cpu.4
> ===
> RCS file: /cvs/src/share/man/man4/man4.i386/cpu.4,v
> retrieving revision 1.18
> diff -u -p -r1.18 cpu.4
> --- share/man/man4/man4.i386/cpu.412 Jan 2018 04:36:44 - 1.18
> +++ share/man/man4/man4.i386/cpu.45 Jun 2018 08:39:38 -
> @@ -53,8 +53,8 @@ positions.
> The processor dynamically adjusts frequency in response to load; the setperf
> value is interpreted as the maximum.
> .It EST
> -Enhanced SpeedStep found on Intel Pentium M processors,
> -offering frequency scaling with numerous positions.
> +Enhanced SpeedStep found on Intel Pentium M and newer processors, as well as
> +on VIA C7 processors, offering frequency scaling with numerous positions.
> .It SpeedStep
> Found on some Intel Pentium 3 and newer mobile chips,
> it is capable of adjusting frequency between a low and high value.
>
morning.
the same page on amd64 documents EST thus:
EST Enhanced SpeedStep found on Intel and VIA
processors, offering frequency scaling with
numerous positions.
that neatly sidesteps the playing catchup issue of trying to list all
supported models. can we do it that way?
jmc
cpu.4: VIA C7 CPUs support Enhanced SpeedStep (i386)
Hi tech@,
VIA C7 CPUs support Enhanced SpeedStep, so reflect that in cpu.4.
On the VIA C7 1.5Ghz:
cpu0: VIA Esther processor 1500MHz ("CentaurHauls" 686-class) 1.51 GHz
cpu0:
FPU,V86,DE,PSE,TSC,MSR,PAE,MCE,APIC,SEP,MTRR,PGE,CMOV,PAT,CFLUSH,ACPI,MMX,FXSR,SSE,SSE2,TM,PBE,NXE,SSE3,EST,TM2
cpu0: Enhanced SpeedStep 1501 MHz: speeds: 1500, 800 MHz
Comments? OK?
Index: share/man/man4/man4.i386/cpu.4
===
RCS file: /cvs/src/share/man/man4/man4.i386/cpu.4,v
retrieving revision 1.18
diff -u -p -r1.18 cpu.4
--- share/man/man4/man4.i386/cpu.4 12 Jan 2018 04:36:44 - 1.18
+++ share/man/man4/man4.i386/cpu.4 5 Jun 2018 08:39:38 -
@@ -53,8 +53,8 @@ positions.
The processor dynamically adjusts frequency in response to load; the setperf
value is interpreted as the maximum.
.It EST
-Enhanced SpeedStep found on Intel Pentium M processors,
-offering frequency scaling with numerous positions.
+Enhanced SpeedStep found on Intel Pentium M and newer processors, as well as
+on VIA C7 processors, offering frequency scaling with numerous positions.
.It SpeedStep
Found on some Intel Pentium 3 and newer mobile chips,
it is capable of adjusting frequency between a low and high value.
