Re: Access to DMA memory while DMA in progress?

On Fri, Oct 27, 2017 at 11:15:34AM -0400, Mouse wrote: > Heh. Well, reading the x86 bus_dma implementation (amd64 doesn't seem > to have a separate bus_dma implementation of its own) leads me to think > it has no such issues; all POSTREAD does there is copy from the bounce > buffer (if the

Re: Access to DMA memory while DMA in progress?

On Fri, 27 Oct 2017, Mouse wrote: > >> But I'm not sure what sort of sync calls I need to make. [...] > > You want to do a bus_dmamap_sync(BUS_DMASYNC_POSTREAD) [...] > > In the NIC example above, you map the ring buffer with > > BUS_DMA_COHERENT, fill it up and do a > >

Re: Access to DMA memory while DMA in progress?

>>> [...access to DMA buffer while DMA in progress...ordering...] >> Hm! On such hardware, then, you can't count on any particular >> portion of a DMA transfer being visible until the whole transfer is >> finished? > Yes. I'm assuming here that the driver would do a data cache > invalidate (for

Re: Access to DMA memory while DMA in progress?

> On Oct 27, 2017, at 10:36 AM, Mouse wrote: > >>> I would like to read the DMA buffer while DMA is still going on. >>> [...] I'm fine if the CPU's view lags the hardware's view slightly, >>> but I do care about the CPU's view of the DMA write order matching >>> the

Re: Access to DMA memory while DMA in progress?

>> I would like to read the DMA buffer while DMA is still going on. >> [...] I'm fine if the CPU's view lags the hardware's view slightly, >> but I do care about the CPU's view of the DMA write order matching >> the hardware's: that is, if the CPU sees the value written by a >> given DMA cycle,

Re: Access to DMA memory while DMA in progress?

> On Oct 27, 2017, at 9:38 AM, Mouse wrote: > > ... > I would like to read the DMA buffer while DMA is still going on. That > is, I have a buffer of (say) 64K and the hardware is busily writing > into it; I want to read the buffer and see what the hardware has >