Hi Rick,
On Sat, 9 Jan 2016 14:45:43 -0800
"Richard (Rick) Karlquist" wrote:
> This circuit is very similar to one that was championed by Tom
> Faulker of HP/Agilent at the now closed Spokane site. Tom
> measured the circuit at about -171 dBc/Hz. He was very
Moin Bruce,
On Sat, 9 Jan 2016 21:36:35 + (UTC)
Bruce Griffiths wrote:
> Splitting the resistor in 2 and ac coupling the emitters together
> reduces the effects of Vbe and/or base biasing mismatch allowing a more
> symmetric output and/or operation at lower input
No, it was just word of mouth within the company.
Somewhere I have a piece of notebook paper
on which Tom drew the circuit. We did have
internal forums where papers where presented,
but this was never even published internally.
As with all forums, a lot of stuff happens
outside the official
Anything like the pnp + diode circuit shown in HP application note 301-1?
Bruce
On Monday, 11 January 2016 8:00 AM, Richard (Rick) Karlquist
wrote:
No, it was just word of mouth within the company.
Somewhere I have a piece of notebook paper
on which Tom drew the
Moin John,
Yes, I know I am comming back to an "old" discussion, but I have questions
that need to be answered! :-)
On Wed, 06 May 2015 08:56:10 -0400
John Ackermann N8UR wrote:
> Wenzel has published the schematic of an excellent squaring circuit. I
> don't have the URL for
Splitting the resistor in 2 and ac coupling the emitters together reduces the
effects of Vbe and/or base biasing mismatch allowing a more symmetric output
and/or operation at lower input signal levels.The inductor reduces the high
frequency variations in the total emitter current. It also
On 1/9/2016 12:44 PM, Attila Kinali wrote:
The purpose of the input circuit is to convert the RF input signal
into a low-jitter square wave that can drive the PIC clock input.
The circuit is closely based on the one published by Wenzel at
http://www.wenzel.com/documents/waveform.html, with
Bob wrote:
The simple answer is that a biased fast CMOS gate will do a better job
ADEV wise than your signal sources will.
Maybe or maybe not, at tau ~1 second. Trouble is, as tau gets
larger, the gate performs *worse*. The switching threshold of all
MOSFET logic devices varies all over
Hi
On May 23, 2015, at 12:37 AM, Charles Steinmetz csteinm...@yandex.com wrote:
Bob wrote:
The simple answer is that a biased fast CMOS gate will do a better job
ADEV wise than your signal sources will.
Maybe or maybe not, at tau ~1 second. Trouble is, as tau gets larger, the
gate
...@n1k.org
Date: Fri, 22 May 2015 17:31:47 -0400
To: time-nuts@febo.com
Subject: Re: [time-nuts] Divider circuit for Rubidium Standard
Hi
What is your objective? Put another way:
1) How clean is your sine wave source?
2) What frequency (or range) are you trying to convert?
3) What level
After reading the posts on this subject I have a question.
First, in my experience I used a rather simple circuit made from
diodes used as limiters and a transistor feeding
a logic inverter. No AGC.
So here is my question. What is the proper circuit to use?
I'd like to do a PSPICE and check
Hi
What is your objective? Put another way:
1) How clean is your sine wave source?
2) What frequency (or range) are you trying to convert?
3) What level range are you trying to work with?
4) What is it going into (how clean is the next stage)?
If you have an optical fountain that is good to
On Friday, May 22, 2015 10:48:16 AM Gerhard Hoffmann wrote:
Am 21.05.2015 um 23:32 schrieb Magnus Danielson:
On 05/21/2015 12:15 AM, Richard (Rick) Karlquist wrote:
The counter front ends seem to be modeled after scope front ends
and scope triggering circuits, where you can adjust the
Hi
The simple answer is that a biased fast CMOS gate will do a better job
ADEV wise than your signal sources will. If you want that to also hold
for phase noise, run the gate on 5.5V and get the input signal as close to that
(5.5V p-p) as you can.
Bob
On May 22, 2015, at 6:29 PM, xaos
Bob,
This are all great questions.
1. Let's assume that it varies from a HP Signal generator
to a home built device. However, If I was to build it I
would expect to pay more and get better specs.
I have a few HP 3325B's and a few 8660C.
I would probably use those as inputs but not always.
2.
Hi
To answer the next part of the question - simulation:
Noise wise, Spice is fundamentally a linear analysis program. Logic gates
mostly operate in a non-linear fashion (full on / full off). The noise
models that are commonly used (when you can even find them)
apply to fairly limited “active
Am 21.05.2015 um 23:32 schrieb Magnus Danielson:
On 05/21/2015 12:15 AM, Richard (Rick) Karlquist wrote:
The counter front ends seem to be modeled after scope front ends
and scope triggering circuits, where you can adjust the triggering
level. Any jitter in the triggering would normally
Hi
On May 22, 2015, at 4:48 AM, Gerhard Hoffmann dk...@arcor.de wrote:
Am 21.05.2015 um 23:32 schrieb Magnus Danielson:
On 05/21/2015 12:15 AM, Richard (Rick) Karlquist wrote:
The counter front ends seem to be modeled after scope front ends
and scope triggering circuits, where you
Hi
On May 20, 2015, at 11:27 PM, Alex Pummer a...@pcscons.com wrote:
once upon the time at Gigatronics we compared logic devices noise and found
that TTL were the quietest
73
KJ6UHN Alex
Before the 74AC stuff came along, some flavor of TTL was the best bet. With TTL
you needed to be a
On 05/21/2015 12:15 AM, Richard (Rick) Karlquist wrote:
On 5/20/2015 11:22 AM, Magnus Danielson wrote:
The older HP counter manuals explained it very nicely too, as they
illustrated the slew-rate amplitude noise to time-noise conversion.
What do amazes me is the fact that I've yet to
Hi
On May 19, 2015, at 7:10 PM, Richard (Rick) Karlquist rich...@karlquist.com
wrote:
On 5/8/2015 2:19 PM, Bob Camp wrote:
On May 7, 2015, at 11:09 AM, Attila Kinali att...@kinali.ch wrote:
On Wed, 06 May 2015 18:09:03 -0700
Richard (Rick) Karlquist rich...@karlquist.com wrote:
Rick,
On 05/20/2015 01:10 AM, Richard (Rick) Karlquist wrote:
On 5/8/2015 2:19 PM, Bob Camp wrote:
On May 7, 2015, at 11:09 AM, Attila Kinali att...@kinali.ch wrote:
On Wed, 06 May 2015 18:09:03 -0700
Richard (Rick) Karlquist rich...@karlquist.com wrote:
A standard input on a frequency
The only gates that seem to do very well are high speed (as in 74AC or faster)
silicon CMOS. You need to run them with a fairly clean supply and feed them
with a p-p input that matches the supply voltage. Other than that, not a lot
of magic. Are they ideal - surely not. Will they hit 2x10^-13
On 5/20/2015 11:22 AM, Magnus Danielson wrote:
The older HP counter manuals explained it very nicely too, as they
illustrated the slew-rate amplitude noise to time-noise conversion.
What do amazes me is the fact that I've yet to see a counter input
channel which takes care to square up the
HI
On May 20, 2015, at 11:55 AM, Richard (Rick) Karlquist
rich...@karlquist.com wrote:
The only gates that seem to do very well are high speed (as in 74AC or
faster)
silicon CMOS. You need to run them with a fairly clean supply and feed them
with a p-p input that matches the supply
once upon the time at Gigatronics we compared logic devices noise and
found that TTL were the quietest
73
KJ6UHN Alex
On 5/20/2015 3:15 PM, Richard (Rick) Karlquist wrote:
On 5/20/2015 11:22 AM, Magnus Danielson wrote:
The older HP counter manuals explained it very nicely too, as they
On 5/8/2015 2:19 PM, Bob Camp wrote:
On May 7, 2015, at 11:09 AM, Attila Kinali att...@kinali.ch wrote:
On Wed, 06 May 2015 18:09:03 -0700
Richard (Rick) Karlquist rich...@karlquist.com wrote:
A standard input on a frequency counter is not a very demanding thing in the
hierarchy of
the existing circuitry. I would assume this would offer a
greater improvement in phase noise?
Cheers
-=Bryan=-
From: kb...@n1k.org
Date: Fri, 8 May 2015 17:19:59 -0400
To: time-nuts@febo.com
Subject: Re: [time-nuts] Divider circuit for Rubidium Standard
Hi
I guess the simple answer
would assume this would
offer a greater improvement in phase noise?
Cheers
-=Bryan=-
From: kb...@n1k.org
Date: Fri, 8 May 2015 17:19:59 -0400
To: time-nuts@febo.com
Subject: Re: [time-nuts] Divider circuit for Rubidium Standard
Hi
I guess the simple answer is “when you measure
On Wed, 06 May 2015 18:09:03 -0700
Richard (Rick) Karlquist rich...@karlquist.com wrote:
A standard input on a frequency counter is not a very demanding thing in
the hierarchy of
TimeNut signals. You can drive any of them with some pretty simple logic
gate based
circuits. No need to
Hi
I guess the simple answer is “when you measure them that’s the result”.
The slightly more complex answer is “fast silicon CMOS is indeed good, other
types may require further analysis”. In general the faster stuff is better
than
the slower CMOS.
Deeper into it you get to the fact that
On 5/6/2015 3:24 PM, Bob Camp wrote:
Hi
A standard input on a frequency counter is not a very demanding thing in the
hierarchy of
TimeNut signals. You can drive any of them with some pretty simple logic gate
based
circuits. No need to spend a lot of money.
Bob
Logic gate, yes.
Hi Rick:
Any suggestions for a circuit with better performance. Purpose will be a
external standard for a frequency counter.
-=Bryan=-
Date: Mon, 4 May 2015 21:09:51 -0700
From: rich...@karlquist.com
To: time-nuts@febo.com
Subject: Re: [time-nuts] Divider circuit for Rubidium Standard
measurement
Subject: Re: [time-nuts] Divider circuit for Rubidium Standard
This is a comparator based circuit. This will give you worse performance than
just about anything else, but it may be good enough anyway.
Rick Karlquist N6RK
___
time-nuts mailing list
The Phase noise floor (~-143dBc/Hz @ 1kHz) of the 10MHz output of that divider
is about 17dBc/Hz higher than either the LTC6957-4 (demo board) or the
Holzworth HX2410 (both ~ -160dBc/Hz @ 1kHz).All measured with a 10MHz +14dBm
input signal.For offsets below a few Hz shielding of the circuitry
: Mon, 4 May 2015 21:09:51 -0700
From: rich...@karlquist.com
To: time-nuts@febo.com
Subject: Re: [time-nuts] Divider circuit for Rubidium Standard
On 4/26/2015 3:51 AM, Bryan _ wrote:
All:
P
I was looking at the project from David partridges web site
http://www.perdrix.co.uk/FrequencyDivider
Rick:
Any suggestions for a circuit with better performance. Purpose will be a
external standard for a frequency counter.
-=Bryan=-
Date: Mon, 4 May 2015 21:09:51 -0700
From: rich...@karlquist.com
To: time-nuts@febo.com
Subject: Re: [time-nuts] Divider circuit for Rubidium Standard
On 4/26/2015 3:51 AM, Bryan _ wrote:
All:
P
I was looking at the project from David partridges web site
http://www.perdrix.co.uk/FrequencyDivider/index.html
-=Bryan=-
___
This is a comparator based
as I don't need all the
dividers, but it has the circuitry for the amplifiers and buffers as well wave
shaping the input.
Cheers
-=Bryan=-
From: kb...@n1k.org
Date: Sun, 26 Apr 2015 09:56:17 -0400
To: time-nuts@febo.com
Subject: Re: [time-nuts] Divider circuit for Rubidium Standard
Hi
=-
From: kb...@n1k.org
Date: Sun, 26 Apr 2015 09:56:17 -0400
To: time-nuts@febo.com
Subject: Re: [time-nuts] Divider circuit for Rubidium Standard
Hi
I would *assume* that either the 20 or 60 MHz is already a square wave. If
they both are, use the 20, if not use
which ever one
Hi
I would *assume* that either the 20 or 60 MHz is already a square wave. If they
both are, use the 20, if not use
which ever one is a square wave already.
Past that it is just a divide by 2 or a divide by 3 followed by a divide by 2.
You want the last stage to be divide
by 2 so the output
All:
Picked up a FE 5680B from Ebay awhile back. Appears to work fine, but is
limited to a 1pps output. However there is a point on the PCB that's documented
that has a 20Mhz output. There is actually a clean 60Mhz output as well.
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