Re: [time-nuts] Digital Phasae Lock Loops

[Bill Reed]

I also knew Dr. Gardner in that time frame. I had the responsibility
for the specification and procurement of the Saturn V com system.
It included a phase locked turn around offset transponder for Doppler
tracking.
Also forward command and return telemetry. To gain some knowledge
of phase locked systems I contracted Dr. Gardner to conduct a course
on phase locked techniques at MSFC. This course became the basis
for his book. He gave me a signed copy.

Bill Reed

-Original Message- 
From: Alexander Pummer

Sent: Friday, October 16, 2015 7:05 PM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Digital Phasae Lock Loops

yes as I wrote Dr. Gardner is the pope of the phase locked loops, his
book is a heavy weight, not for beginner
73
Alex
10/16/2015 4:16 PM, Dave Daniel wrote:

Wasn't Dr. Gardner the author of "the other" PLL book? Or am I confusing
his name with another Gardner?

DaveD

On 10/16/2015 4:33 PM, Alexander Pummer wrote:
actually my old friend Dr. Floyd Gardner -- 
who is the pope of the

phase locked loops -- told me some thirty years ego , that the Best
book os a very good introduction
73
Alex

On 10/16/2015 1:42 PM, Dave Daniel wrote:
Roland Best's text is the best (no pun intended) 
one I have seen on

PLLs. I didn't know it was up to a sixth edition.

On 10/16/2015 11:18 AM, Alexander Pummer wrote:
Hi Steve,
I will tell you a big secret; a digital PLL is not a low phase noise
system and a very good introduction to PLLs and the digital PLL
could be found in Roland Bests:


Phase Locked Loops 6/e: Design, Simulation, and Applications

73
KJ6UHN
Alex


On 10/16/2015 7:45 AM, Martyn Smith wrote:
Hello,

I want to design a digital phase lock loop.

I intend to lock a 10 MHz ultra low noise oscillator that we make
to an external frequency standard.

I need a digital PLL as I’m trying to get a loop bandwidth  0.1 
Hz.


Has anyone had any experience of Digital PLL’s or can point me to
any documents published?

Regards

Steve
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Re: [time-nuts] Digital Phasae Lock Loops

[Tom Van Baak]

Martyn Smith wrote:
> All we want to do is lock a 10 MHz ULN OXCO to a rubidium.
> So basically a clean up loop.
> Then we can provide an ULN output from the ULN OXCO and long term stability 
> from the rubidium.
> The 10 MHz ULN OXCO has phase noise of –115 to -120 dBc/Hz @ 1 Hz with a –174 
> dBc noise floor.
> The rubidium’s phase noise at 1 Hz is about –105 dBc.
> So for the PLL to remove the poor rubidium phase noise I need a loop BW of 
> less than 0.2 Hz.
> I have tried digital PLL’s from other companies.  One you can specify the 
> bandwidth down to 1 mHz.
> But they are very unreliable, subject to flicking out of lock now and then.
> At the moment we use an analog PLL with a loop bandwidth around 0.2 Hz.
> That works well for my ULN OXCO’s that make about –113 dBc@1 Hz.
> But now we are getting even lower phase noise at 1 Hz (-115 dBc and below), I 
> need
>a smaller loop BW, and we aren’t able to get that with an analog PLL.

Ok, thanks for the clarification. I'll leave it up to those with more 
experience to recommend a solution. I'd be surprised if using a digital PLL 
helps here. Are you sure you've reached the limit of what you can do with 
analog?

BTW, if your existing clean up oscillator is "very unreliable" consider that it 
may be your oscillator and not the PLL. For this you do not want to use ADEV or 
L(f) statistics. A one-time phase jump can cause loss of lock and averaging 
statistics will not tell you this. Instead you may want to look at the raw 
phase data and quantify the jumps. Occasional large jumps may not show up at 
all in an ADEV plot but can cause trouble for a PLL. Magnus, would MTIE be 
appropriate here?

/tvb

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Re: [time-nuts] Digital Phasae Lock Loops

[Alex Pummer]

actually, that is a ketch 22, if the loop bandwidth is to low, you will 
have low noise , but it may will not lock at all, an other way to try to 
filter out the noise, also you may make the loop filter digital, but 
leave the the PLL analog, that could have  the possibility to have the 
advantage to be able to change the loop bandwidth  increase for locking, 
and reduce after the detected locking

73
Alex


On 10/17/2015 4:57 AM, Tom Van Baak wrote:

Martyn Smith wrote:

All we want to do is lock a 10 MHz ULN OXCO to a rubidium.
So basically a clean up loop.
Then we can provide an ULN output from the ULN OXCO and long term stability 
from the rubidium.
The 10 MHz ULN OXCO has phase noise of –115 to -120 dBc/Hz @ 1 Hz with a –174 
dBc noise floor.
The rubidium’s phase noise at 1 Hz is about –105 dBc.
So for the PLL to remove the poor rubidium phase noise I need a loop BW of less 
than 0.2 Hz.
I have tried digital PLL’s from other companies.  One you can specify the 
bandwidth down to 1 mHz.
But they are very unreliable, subject to flicking out of lock now and then.
At the moment we use an analog PLL with a loop bandwidth around 0.2 Hz.
That works well for my ULN OXCO’s that make about –113 dBc@1 Hz.
But now we are getting even lower phase noise at 1 Hz (-115 dBc and below), I 
need
a smaller loop BW, and we aren’t able to get that with an analog PLL.

Ok, thanks for the clarification. I'll leave it up to those with more 
experience to recommend a solution. I'd be surprised if using a digital PLL 
helps here. Are you sure you've reached the limit of what you can do with 
analog?

BTW, if your existing clean up oscillator is "very unreliable" consider that it 
may be your oscillator and not the PLL. For this you do not want to use ADEV or L(f) 
statistics. A one-time phase jump can cause loss of lock and averaging statistics will 
not tell you this. Instead you may want to look at the raw phase data and quantify the 
jumps. Occasional large jumps may not show up at all in an ADEV plot but can cause 
trouble for a PLL. Magnus, would MTIE be appropriate here?

/tvb

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Re: [time-nuts] Digital Phasae Lock Loops

[Jim Lux]

On 10/17/15 6:17 AM, Alex Pummer wrote:


actually, that is a ketch 22, if the loop bandwidth is to low, you will
have low noise , but it may will not lock at all, an other way to try to
filter out the noise, also you may make the loop filter digital, but
leave the the PLL analog, that could have  the possibility to have the
advantage to be able to change the loop bandwidth  increase for locking,
and reduce after the detected locking


changing  loop bandwidth between acquisition and tracking, or, 
similarly, (effective) loop bandwidth that changes with SNR are pretty 
common strategies.


In the deep space transponder world (where you are acquiring and 
tracking a very narrow carrier at -155 or -160 dBm against noise of 
-170dBm/Hz) you also want to know what order filter you should be using 
in the tracking loop.  If there's an expectation that the frequency 
being tracked is changing (e.g. Doppler), then a low order loop may not 
be the best choice.




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Re: [time-nuts] Digital Phasae Lock Loops

[Ole Petter Ronningen]

Quartzlock makes a couple of interesting digital PLL-modules, marketed
specifically as ultra low noise cleanup loops. The datasheets contain a lot
of interesting and useful information about the software architecture - not
enough that *I* can recreate it, but perhaps someone more skilled than me
can.

Very interesting stuff:
http://quartzlock.com/product/timing-modules/digital-phase-lock-loop

Does anyone know of a reference where more information about this approach
can be found? I am impressed they can do all that in a PIC 16F689..

On Sat, Oct 17, 2015 at 4:48 PM, Jim Lux  wrote:

> On 10/17/15 6:17 AM, Alex Pummer wrote:
>
>>
>> actually, that is a ketch 22, if the loop bandwidth is to low, you will
>> have low noise , but it may will not lock at all, an other way to try to
>> filter out the noise, also you may make the loop filter digital, but
>> leave the the PLL analog, that could have  the possibility to have the
>> advantage to be able to change the loop bandwidth  increase for locking,
>> and reduce after the detected locking
>>
>
> changing  loop bandwidth between acquisition and tracking, or, similarly,
> (effective) loop bandwidth that changes with SNR are pretty common
> strategies.
>
> In the deep space transponder world (where you are acquiring and tracking
> a very narrow carrier at -155 or -160 dBm against noise of -170dBm/Hz) you
> also want to know what order filter you should be using in the tracking
> loop.  If there's an expectation that the frequency being tracked is
> changing (e.g. Doppler), then a low order loop may not be the best choice.
>
>
>
>
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Re: [time-nuts] Digital Phasae Lock Loops

[Magnus Danielson]

Hi,

On 10/17/2015 01:57 PM, Tom Van Baak wrote:

Martyn Smith wrote:

All we want to do is lock a 10 MHz ULN OXCO to a rubidium.
So basically a clean up loop.
Then we can provide an ULN output from the ULN OXCO and long term stability 
from the rubidium.
The 10 MHz ULN OXCO has phase noise of –115 to -120 dBc/Hz @ 1 Hz with a –174 
dBc noise floor.
The rubidium’s phase noise at 1 Hz is about –105 dBc.
So for the PLL to remove the poor rubidium phase noise I need a loop BW of less 
than 0.2 Hz.
I have tried digital PLL’s from other companies.  One you can specify the 
bandwidth down to 1 mHz.
But they are very unreliable, subject to flicking out of lock now and then.
At the moment we use an analog PLL with a loop bandwidth around 0.2 Hz.
That works well for my ULN OXCO’s that make about –113 dBc@1 Hz.
But now we are getting even lower phase noise at 1 Hz (-115 dBc and below), I 
need
a smaller loop BW, and we aren’t able to get that with an analog PLL.


Ok, thanks for the clarification. I'll leave it up to those with more 
experience to recommend a solution. I'd be surprised if using a digital PLL 
helps here. Are you sure you've reached the limit of what you can do with 
analog?


First of all, digital PLLs is an overloaded term. I consider many of the 
PLLs I do digital, but they are DSP based with software, but essentially 
just normal PI-loops. The benefit of doing a PI-loop in digital is that 
the integrator does not have loss in the same way that the analog 
integrator does, which helps with bandwidths below 1 Hz.
What is fairly critical is to maintain fairly high resolution on the 
input and output, but definitively in the integrator. However, in the 
DSP-side, maintaining many bits in the integrator is so cheap, that it 
stupid not to do it.



BTW, if your existing clean up oscillator is "very unreliable" consider that it 
may be your oscillator and not the PLL. For this you do not want to use ADEV or L(f) 
statistics. A one-time phase jump can cause loss of lock and averaging statistics will 
not tell you this. Instead you may want to look at the raw phase data and quantify the 
jumps. Occasional large jumps may not show up at all in an ADEV plot but can cause 
trouble for a PLL. Magnus, would MTIE be appropriate here?


Great question.

MTIE could indeed be useful, but it one has to understand what MTIE 
means, so it can be a bit confusing initially. MTIE is however the 
telecom sync guys way of expressing long term systematic noise and is a 
mirror-version of the sine-jitter tolerance test which is so helpful.


I often look at phase and frequency raw-data. MTIE is a process-variant 
of the phase-data to illustrate the maxiumum difference between min and 
max value of a sweeping window of size tau. MTIE and sine 
jitter-tolerance curves are very handy as they illustrate the 
peak-to-peak systematics for different frequencies/time which then 
convert to buffer sizes and PLL bandwidths.


Cycle-slipping is a good search-term. When cycle slipping occurs, you 
usually get a high spike in the frequency plane, so they are usually 
easy to spot there, and then go for the phase plane to see how the 
transition looked. TimeLab is hell of a good tool to fool around with 
such things.


Cheers,
Magnus
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Re: [time-nuts] Digital Phasae Lock Loops

[Jim Lux]

On 10/16/15 7:45 AM, Martyn Smith wrote:

Hello,

I want to design a digital phase lock loop.

I intend to lock a 10 MHz ultra low noise oscillator that we make to an 
external frequency standard.

I need a digital PLL as I’m trying to get a loop bandwidth < 0.1 Hz.



are you locking the oscillator via a voltage to the oscillator?
How would you derive the error signal between your 10 MHz and the 
external standard?   Some sort of phase/frequency detector?
I would think that any of the GPS disciplined oscillator schemes that 
have been discussed on the list would be a good start.


You could also use your oscillator as the clock for an ADC that 
digitizes the external standard (or vice versa), which basically makes 
the ADC the "mixer".


Once you've got an error signal, it's a matter of an appropriate loop 
filter driving a DAC.






Has anyone had any experience of Digital PLL’s or can point me to any documents 
published?

Regards

Steve
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Re: [time-nuts] Digital Phasae Lock Loops

[Alexander Pummer]

Hi Steve,
I will tell you a big secret; a digital PLL is not a low phase noise 
system and a very good introduction to PLLs and the digital PLL could be 
found in Roland Bests:



 Phase Locked Loops 6/e: Design, Simulation, and Applications

73
KJ6UHN
Alex


On 10/16/2015 7:45 AM, Martyn Smith wrote:

Hello,

I want to design a digital phase lock loop.

I intend to lock a 10 MHz ultra low noise oscillator that we make to an 
external frequency standard.

I need a digital PLL as I’m trying to get a loop bandwidth < 0.1 Hz.

Has anyone had any experience of Digital PLL’s or can point me to any documents 
published?

Regards

Steve
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Re: [time-nuts] Digital Phasae Lock Loops

[Dave Daniel]

Roland Best's text is the best (no pun intended) one I have seen on 
PLLs. I didn't know it was up to a sixth edition.


On 10/16/2015 11:18 AM, Alexander Pummer wrote:

Hi Steve,
I will tell you a big secret; a digital PLL is not a low phase noise 
system and a very good introduction to PLLs and the digital PLL could 
be found in Roland Bests:



 Phase Locked Loops 6/e: Design, Simulation, and Applications

73
KJ6UHN
Alex


On 10/16/2015 7:45 AM, Martyn Smith wrote:

Hello,

I want to design a digital phase lock loop.

I intend to lock a 10 MHz ultra low noise oscillator that we make to 
an external frequency standard.


I need a digital PLL as I’m trying to get a loop bandwidth < 0.1 Hz.

Has anyone had any experience of Digital PLL’s or can point me to any 
documents published?


Regards

Steve
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Re: [time-nuts] Digital Phasae Lock Loops

[Mike Feher]

Hi Alex -

Someplace I have a copy of Floyd's pre-published manuscript for his first book. 
I use to used it a lot in the late 60's and early 70's till I actually got his 
published version. 73 - Mike 

Mike B. Feher, EOZ Inc.
89 Arnold Blvd.
Howell, NJ, 07731
732-886-5960 office
908-902-3831 cell

-Original Message-
From: time-nuts [mailto:time-nuts-boun...@febo.com] On Behalf Of Alexander 
Pummer
Sent: Friday, October 16, 2015 6:33 PM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Digital Phasae Lock Loops

actually my old friend Dr. Floyd Gardner -- who is the pope of the phase locked 
loops -- told me some thirty years ego , that the Best book os a very good 
introduction
73
Alex

On 10/16/2015 1:42 PM, Dave Daniel wrote:
> Roland Best's text is the best (no pun intended) one I have seen on 
> PLLs. I didn't know it was up to a sixth edition.
>
> On 10/16/2015 11:18 AM, Alexander Pummer wrote:
>> Hi Steve,
>> I will tell you a big secret; a digital PLL is not a low phase noise 
>> system and a very good introduction to PLLs and the digital PLL could 
>> be found in Roland Bests:
>>
>>
>>  Phase Locked Loops 6/e: Design, Simulation, and Applications
>>
>> 73
>> KJ6UHN
>> Alex
>>
>>
>> On 10/16/2015 7:45 AM, Martyn Smith wrote:
>>> Hello,
>>>
>>> I want to design a digital phase lock loop.
>>>
>>> I intend to lock a 10 MHz ultra low noise oscillator that we make to 
>>> an external frequency standard.
>>>
>>> I need a digital PLL as I’m trying to get a loop bandwidth < 0.1 Hz.
>>>
>>> Has anyone had any experience of Digital PLL’s or can point me to 
>>> any documents published?
>>>
>>> Regards
>>>
>>> Steve
>>> ___
>>> time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to 
>>> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
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>>
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Re: [time-nuts] Digital Phasae Lock Loops

[Dave Daniel]

Wasn't Dr. Gardner the author of "the other" PLL book? Or am I confusing 
his name with another Gardner?


DaveD

On 10/16/2015 4:33 PM, Alexander Pummer wrote:
actually my old friend Dr. Floyd Gardner -- who is the pope of the 
phase locked loops -- told me some thirty years ego , that the Best 
book os a very good introduction

73
Alex

On 10/16/2015 1:42 PM, Dave Daniel wrote:
Roland Best's text is the best (no pun intended) one I have seen on 
PLLs. I didn't know it was up to a sixth edition.


On 10/16/2015 11:18 AM, Alexander Pummer wrote:

Hi Steve,
I will tell you a big secret; a digital PLL is not a low phase noise 
system and a very good introduction to PLLs and the digital PLL 
could be found in Roland Bests:



 Phase Locked Loops 6/e: Design, Simulation, and Applications

73
KJ6UHN
Alex


On 10/16/2015 7:45 AM, Martyn Smith wrote:

Hello,

I want to design a digital phase lock loop.

I intend to lock a 10 MHz ultra low noise oscillator that we make 
to an external frequency standard.


I need a digital PLL as I’m trying to get a loop bandwidth < 0.1 Hz.

Has anyone had any experience of Digital PLL’s or can point me to 
any documents published?


Regards

Steve
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Re: [time-nuts] Digital Phasae Lock Loops

[Magnus Danielson]

Meanwhile I like his book better, but the Best book isn't too bad for 
some people. Wolaver is another good book. They excell in different aspects.


Cheers,
Magnus

On 10/17/2015 12:33 AM, Alexander Pummer wrote:

actually my old friend Dr. Floyd Gardner -- who is the pope of the phase
locked loops -- told me some thirty years ego , that the Best book os a
very good introduction
73
Alex

On 10/16/2015 1:42 PM, Dave Daniel wrote:

Roland Best's text is the best (no pun intended) one I have seen on
PLLs. I didn't know it was up to a sixth edition.

On 10/16/2015 11:18 AM, Alexander Pummer wrote:

Hi Steve,
I will tell you a big secret; a digital PLL is not a low phase noise
system and a very good introduction to PLLs and the digital PLL could
be found in Roland Bests:


 Phase Locked Loops 6/e: Design, Simulation, and Applications

73
KJ6UHN
Alex


On 10/16/2015 7:45 AM, Martyn Smith wrote:

Hello,

I want to design a digital phase lock loop.

I intend to lock a 10 MHz ultra low noise oscillator that we make to
an external frequency standard.

I need a digital PLL as I’m trying to get a loop bandwidth < 0.1 Hz.

Has anyone had any experience of Digital PLL’s or can point me to
any documents published?

Regards

Steve
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Re: [time-nuts] Digital Phasae Lock Loops

[Alexander Pummer]

actually my old friend Dr. Floyd Gardner -- who is the pope of the phase 
locked loops -- told me some thirty years ego , that the Best book os a 
very good introduction

73
Alex

On 10/16/2015 1:42 PM, Dave Daniel wrote:
Roland Best's text is the best (no pun intended) one I have seen on 
PLLs. I didn't know it was up to a sixth edition.


On 10/16/2015 11:18 AM, Alexander Pummer wrote:

Hi Steve,
I will tell you a big secret; a digital PLL is not a low phase noise 
system and a very good introduction to PLLs and the digital PLL could 
be found in Roland Bests:



 Phase Locked Loops 6/e: Design, Simulation, and Applications

73
KJ6UHN
Alex


On 10/16/2015 7:45 AM, Martyn Smith wrote:

Hello,

I want to design a digital phase lock loop.

I intend to lock a 10 MHz ultra low noise oscillator that we make to 
an external frequency standard.


I need a digital PLL as I’m trying to get a loop bandwidth < 0.1 Hz.

Has anyone had any experience of Digital PLL’s or can point me to 
any documents published?


Regards

Steve
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Re: [time-nuts] Digital Phasae Lock Loops

[Alexander Pummer]

yes as I wrote Dr. Gardner is the pope of the phase locked loops, his 
book is a heavy weight, not for beginner

73
Alex
10/16/2015 4:16 PM, Dave Daniel wrote:

Wasn't Dr. Gardner the author of "the other" PLL book? Or am I confusing
his name with another Gardner?

DaveD

On 10/16/2015 4:33 PM, Alexander Pummer wrote:
actually my old friend Dr. Floyd Gardner -- 
who is the pope of the

phase locked loops -- told me some thirty years ego , that the Best
book os a very good introduction
73
Alex

On 10/16/2015 1:42 PM, Dave Daniel wrote:
Roland Best's text is the best (no pun 
intended) one I have seen on

PLLs. I didn't know it was up to a sixth edition.

On 10/16/2015 11:18 AM, Alexander Pummer wrote:
Hi Steve,
I will tell you a big secret; a digital PLL is not a low phase noise
system and a very good introduction to PLLs and the digital PLL
could be found in Roland Bests:


Phase Locked Loops 6/e: Design, Simulation, and Applications

73
KJ6UHN
Alex


On 10/16/2015 7:45 AM, Martyn Smith wrote:
Hello,

I want to design a digital phase lock loop.

I intend to lock a 10 MHz ultra low noise oscillator that we make
to an external frequency standard.

I need a digital PLL as I’m trying to get a loop bandwidth  
0.1 Hz.


Has anyone had any experience of Digital PLL’s or can point me to
any documents published?

Regards

Steve
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