On 10/16/15 7:45 AM, Martyn Smith wrote:
Hello,
I want to design a digital phase lock loop.
I intend to lock a 10 MHz ultra low noise oscillator that we make to an
external frequency standard.
I need a digital PLL as I’m trying to get a loop bandwidth < 0.1 Hz.
are you locking the oscillator via a voltage to the oscillator?
How would you derive the error signal between your 10 MHz and the
external standard? Some sort of phase/frequency detector?
I would think that any of the GPS disciplined oscillator schemes that
have been discussed on the list would be a good start.
You could also use your oscillator as the clock for an ADC that
digitizes the external standard (or vice versa), which basically makes
the ADC the "mixer".
Once you've got an error signal, it's a matter of an appropriate loop
filter driving a DAC.
Has anyone had any experience of Digital PLL’s or can point me to any documents
published?
Regards
Steve
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