On Tue, 03 Jan 2012 07:01:13 +0100, ehydra wrote:
>David schrieb:
>> I could analyze it on SPICE but I suspect the real world construction
>> parasitics will be what limits the performance. I just sketched it
>> out in my notebook but I will see if I can post it somewhere. Is
>> there a quick a
On Thu, 29 Dec 2011 21:14:30 -0800, John Beale
wrote:
In case it's useful... there are many ways to get a square wave out from
a sine wave in, but one straightforward way is with a comparator. [...]
FWIW, I decided on a more straightforward way to get a square wave output
from my FE-5680A:
David schrieb:
I could analyze it on SPICE but I suspect the real world construction
parasitics will be what limits the performance. I just sketched it
out in my notebook but I will see if I can post it somewhere. Is
there a quick and dirty online schematic capture site?
Scan it. I will mak
precise time and frequency measurement
Reply-To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] FE-5680A clock shaping (sine -> square wave)
I could analyze it on SPICE but I suspect the real world construction
parasitics will be what limits the performa
I could analyze it on SPICE but I suspect the real world construction
parasitics will be what limits the performance. I just sketched it
out in my notebook but I will see if I can post it somewhere. Is
there a quick and dirty online schematic capture site?
It is not that complicated being a diff
The output level and impedance is why I ended up with the circuit I
did. The complementary transconductance output allows a near 5 volt
rail to rail swing from a 5 volt supply while driving a 50 ohm
transmission line and 50 ohm shunt termination to 5 volts on the
driver side.
It would be a power
Hi
In most cases it's a T section (two coils, one cap) low pass filter tacked on
to the output of a logic gate (or FPGA output). Net result is a reasonable sine
wave *if* you terminate it correctly. Based on the observations posted on the
list, the filter in the FE-5680 seems to be set up for a
Is it possible to sketch the circuit? I can SPICE it.
Symmetry limiting is the holy grail and it is questionable if a discrete
design is way better than one of the chips.
Here is another limiter circuit (by Chris Trask):
http://ehydra.dyndns.info/NG/LTspice/Negative%20Impedance%20LO%20Driver.
Heck- for a really good risetime, all you need is a mercury-wetted relay
:-)
Don
David
> What kind of performance would you expect in this application? Low
> jitter? 50 ohm output? TTL or better signal levels? Fast rise and
> fall times? Duty cycle correction?
>
> After reading your post I wa
The spec is over the entire temp range, and it may not be linear to temp. It
could be more sensitive at some temps than others.. Especially if the temp is
digitally compensated inside the unit.
Sent From iPhone
On Dec 29, 2011, at 23:55, Chris Albertson wrote:
> On Thu, Dec 29, 2011 at 9:14 P
What kind of performance would you expect in this application? Low
jitter? 50 ohm output? TTL or better signal levels? Fast rise and
fall times? Duty cycle correction?
After reading your post I was thinking about how to go about it and
ended up with an 8 transistor discrete design using a dif
On Thu, Dec 29, 2011 at 9:14 PM, John Beale wrote:
> ...and by the way, my FE-5680A shows a consistent -7E-12 per degree C
> temperature sensitivity (measured at case temp 42 and 52 C).
The spec says 3E-10 from -5C to 50C
So (3E-10)/55 = 5.5E-12 and you got 7E-12 I'd say it close to
what's ad
In case it's useful... there are many ways to get a square wave out from a
sine wave in, but one straightforward way is with a comparator. Some work
better than others. The slow ones won't work at all at 10 MHz, and the very
fast comparators (MAX999, ADCMP600, LT1116 etc.) are more expensive, an
13 matches
Mail list logo
