Re: [time-nuts] Zero-Crossing Detector Design?
Am 16.09.2012 21:46, schrieb Richard (Rick) Karlquist: Again, a really high speed comparator necessarily has a really broad bandwidth, meaning its noise bandwidth is large. This means more noise and more jitter than a lower speed comparator. The comparator cited is much faster than necessary for 30 MHz, by orders of magnitude. I did not suggest it for this 30 MHz system. And having orders of magnitude more noise bandwidth goes along with orders of magnitude less time where it contributes noise at all. Setting rise time / 3dB corners with NP0/PP caps, stable resistors and close to zero contributions of semiconductors ( in absolute ps) is much more desirable than leaving it to the mood of a LM139. Precise fitting of the BW vs. the required slope, in multiple steps, is the essence of O. Collins' paper. 73, Gerhard ps in the usenet group sci.electronics.design is a discussion about ovens with Phil Hobbs. I did inject a pointer to your paper. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
Am 20.07.2012 00:57, schrieb Richard (Rick) Karlquist: A fast comparator seems like a good idea, and it is simple, however it is actually the last thing you want to use. High thermal sensitivity and high jitter. Rick On 7/19/2012 1:35 PM, Dan Kemppainen wrote: Or use a fast comparator such as an ADCMP600 series. Much lower delays, and faster rising/falling edges. FYI, I've had good luck with this at 30Mhz. You could transformer couple this one, or simply couple it through a cap. The ADCMP580 could be an excellent choice for the output stage of a Collins type device. Running quite cool and showing only 180 ps _total_ delay is a good start. Good rise/fall times on home-etched 0.5 mm FR4 (and some semi-rigid): http://www.imagesup.de/bild-_Mgif-119362.htm regards, Gerhard, dk4xp ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
On 9/16/2012 12:03 PM, Gerhard Hoffmann wrote: Am 20.07.2012 00:57, schrieb Richard (Rick) Karlquist: A fast comparator seems like a good idea, and it is simple, however it is actually the last thing you want to use. High thermal sensitivity and high jitter. Rick On 7/19/2012 1:35 PM, Dan Kemppainen wrote: Or use a fast comparator such as an ADCMP600 series. Much lower delays, and faster rising/falling edges. FYI, I've had good luck with this at 30Mhz. You could transformer couple this one, or simply couple it through a cap. The ADCMP580 could be an excellent choice for the output stage of a Collins type device. Running quite cool and showing only 180 ps _total_ delay is a good start. Good rise/fall times on home-etched 0.5 mm FR4 (and some semi-rigid): http://www.imagesup.de/bild-_Mgif-119362.htm regards, Gerhard, dk4xp Again, a really high speed comparator necessarily has a really broad bandwidth, meaning its noise bandwidth is large. This means more noise and more jitter than a lower speed comparator. The comparator cited is much faster than necessary for 30 MHz, by orders of magnitude. Rick N6RK ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
For the specific application of driving an FPGA clock pin (that has an enormous input bandwidth) many things can go wrong. All fine about the advantages and disadvantages of the gate with resistor feedback, all I can say is that over here I it was not the best solution we found over many FPGA board versions with external clock. The latest design and the one we keep using standard now, uses a differential pair of PNP transistors (BFT91), this will have a moderate gain of x10 or so and the resistors set for making a limited wave of 0 to 3.0V (simple change of resistors can make it 0-2.0V or else required). we use a 100MHz narrow band limited bandwidth sin signal so no filter added, but we could add if we need one. The output signal into the FPGA looks very clean and has a few ns rise and fall times (not super steep, but the fpga input does the rest. It does depend also on the resistor values and current used in the transistor pair). This was the way we could get the very minimum clock jitter in the FPGA and a simple circuit quite tolerant to input levels and make a very clean and well defined signal into the FPGA. Way better than 74F or 74LV gates etc. The only inconvenience is that it needs +5V for the circuit to work (the VCCIO of +3.3V is not enough). My 2 euro cents ;-) Luis Cupido ct1dmk. On 7/22/2012 9:32 PM, Bill Fuqua wrote: Wow, I have not checked this list for some time. But there is a lot said about zero crossing detectors. Lots and lots of replies, so many that I have not looked at all of them. 1. Do not use CMOS inverters. Even though so much has been published on using these in linear mode by adding a feedback resistor, they can be a nightmare. The fast ones (74HC, 74AC, etc) have so much high frequency gain they are likely to take off into oscillation on their own. 2. The first thing you can do to get a good clean zero crossing is to reduce the noise. This means to pass it thru a narrow band pass filter such as a crystal filter. The narrower this filter is the closer to a pure sinewave it becomes and the less noise you have. 3. In research when we want a precise trigger we use what is called a constant fraction discriminator. This may not be needed if you have a very clean signal and its amplitude does not vary and you are wanting to trigger exactly at zero. But a constant fraction discriminator triggers on a point that is a constant fraction of the amplitude of the signal. They require a delay so that a fraction of the peak of the cycle can be compared with the rising edge of that cycle. This is mostly used with triggering on pulses of varying heights and when subnanosecond timing is required. My suggestion is to clean up your signal as much as possible and reduce noise bandwidth using a bandpass filter and then use a low noise amplifier for the front end of your zero-crossing detector. 73 Bill wa4lav ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
Hi Did you try running it at 3.3V and going into an LVDS input on the FPGA? Bob -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On Behalf Of ct1dmk Sent: Monday, July 23, 2012 7:26 AM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] Zero-Crossing Detector Design? For the specific application of driving an FPGA clock pin (that has an enormous input bandwidth) many things can go wrong. All fine about the advantages and disadvantages of the gate with resistor feedback, all I can say is that over here I it was not the best solution we found over many FPGA board versions with external clock. The latest design and the one we keep using standard now, uses a differential pair of PNP transistors (BFT91), this will have a moderate gain of x10 or so and the resistors set for making a limited wave of 0 to 3.0V (simple change of resistors can make it 0-2.0V or else required). we use a 100MHz narrow band limited bandwidth sin signal so no filter added, but we could add if we need one. The output signal into the FPGA looks very clean and has a few ns rise and fall times (not super steep, but the fpga input does the rest. It does depend also on the resistor values and current used in the transistor pair). This was the way we could get the very minimum clock jitter in the FPGA and a simple circuit quite tolerant to input levels and make a very clean and well defined signal into the FPGA. Way better than 74F or 74LV gates etc. The only inconvenience is that it needs +5V for the circuit to work (the VCCIO of +3.3V is not enough). My 2 euro cents ;-) Luis Cupido ct1dmk. On 7/22/2012 9:32 PM, Bill Fuqua wrote: Wow, I have not checked this list for some time. But there is a lot said about zero crossing detectors. Lots and lots of replies, so many that I have not looked at all of them. 1. Do not use CMOS inverters. Even though so much has been published on using these in linear mode by adding a feedback resistor, they can be a nightmare. The fast ones (74HC, 74AC, etc) have so much high frequency gain they are likely to take off into oscillation on their own. 2. The first thing you can do to get a good clean zero crossing is to reduce the noise. This means to pass it thru a narrow band pass filter such as a crystal filter. The narrower this filter is the closer to a pure sinewave it becomes and the less noise you have. 3. In research when we want a precise trigger we use what is called a constant fraction discriminator. This may not be needed if you have a very clean signal and its amplitude does not vary and you are wanting to trigger exactly at zero. But a constant fraction discriminator triggers on a point that is a constant fraction of the amplitude of the signal. They require a delay so that a fraction of the peak of the cycle can be compared with the rising edge of that cycle. This is mostly used with triggering on pulses of varying heights and when subnanosecond timing is required. My suggestion is to clean up your signal as much as possible and reduce noise bandwidth using a bandpass filter and then use a low noise amplifier for the front end of your zero-crossing detector. 73 Bill wa4lav ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
Hi Bob, No, never tried but it looks a good idea. Our boards all have 5v so there was never any pressure... ... for a 0.5v in the tail resistor to vcc and 0.7v of vbe I could easily allow collectors to swing some 300mv around 1.2V... a couple of resistors more than my single ended solution... but it should work fine from 3v3. Must try that. tks, lc ct1dmk, On 7/23/2012 12:35 PM, Bob Camp wrote: Hi Did you try running it at 3.3V and going into an LVDS input on the FPGA? Bob -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On Behalf Of ct1dmk Sent: Monday, July 23, 2012 7:26 AM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] Zero-Crossing Detector Design? For the specific application of driving an FPGA clock pin (that has an enormous input bandwidth) many things can go wrong. All fine about the advantages and disadvantages of the gate with resistor feedback, all I can say is that over here I it was not the best solution we found over many FPGA board versions with external clock. The latest design and the one we keep using standard now, uses a differential pair of PNP transistors (BFT91), this will have a moderate gain of x10 or so and the resistors set for making a limited wave of 0 to 3.0V (simple change of resistors can make it 0-2.0V or else required). we use a 100MHz narrow band limited bandwidth sin signal so no filter added, but we could add if we need one. The output signal into the FPGA looks very clean and has a few ns rise and fall times (not super steep, but the fpga input does the rest. It does depend also on the resistor values and current used in the transistor pair). This was the way we could get the very minimum clock jitter in the FPGA and a simple circuit quite tolerant to input levels and make a very clean and well defined signal into the FPGA. Way better than 74F or 74LV gates etc. The only inconvenience is that it needs +5V for the circuit to work (the VCCIO of +3.3V is not enough). My 2 euro cents ;-) Luis Cupido ct1dmk. On 7/22/2012 9:32 PM, Bill Fuqua wrote: Wow, I have not checked this list for some time. But there is a lot said about zero crossing detectors. Lots and lots of replies, so many that I have not looked at all of them. 1. Do not use CMOS inverters. Even though so much has been published on using these in linear mode by adding a feedback resistor, they can be a nightmare. The fast ones (74HC, 74AC, etc) have so much high frequency gain they are likely to take off into oscillation on their own. 2. The first thing you can do to get a good clean zero crossing is to reduce the noise. This means to pass it thru a narrow band pass filter such as a crystal filter. The narrower this filter is the closer to a pure sinewave it becomes and the less noise you have. 3. In research when we want a precise trigger we use what is called a constant fraction discriminator. This may not be needed if you have a very clean signal and its amplitude does not vary and you are wanting to trigger exactly at zero. But a constant fraction discriminator triggers on a point that is a constant fraction of the amplitude of the signal. They require a delay so that a fraction of the peak of the cycle can be compared with the rising edge of that cycle. This is mostly used with triggering on pulses of varying heights and when subnanosecond timing is required. My suggestion is to clean up your signal as much as possible and reduce noise bandwidth using a bandpass filter and then use a low noise amplifier for the front end of your zero-crossing detector. 73 Bill wa4lav ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
Hi The nice thing about going into the LVDS inputs is that you are differential right at the FPGA. Often that's where a *lot* of junk is running around. Bob -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On Behalf Of ct1dmk Sent: Monday, July 23, 2012 8:37 AM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] Zero-Crossing Detector Design? Hi Bob, No, never tried but it looks a good idea. Our boards all have 5v so there was never any pressure... ... for a 0.5v in the tail resistor to vcc and 0.7v of vbe I could easily allow collectors to swing some 300mv around 1.2V... a couple of resistors more than my single ended solution... but it should work fine from 3v3. Must try that. tks, lc ct1dmk, On 7/23/2012 12:35 PM, Bob Camp wrote: Hi Did you try running it at 3.3V and going into an LVDS input on the FPGA? Bob -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On Behalf Of ct1dmk Sent: Monday, July 23, 2012 7:26 AM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] Zero-Crossing Detector Design? For the specific application of driving an FPGA clock pin (that has an enormous input bandwidth) many things can go wrong. All fine about the advantages and disadvantages of the gate with resistor feedback, all I can say is that over here I it was not the best solution we found over many FPGA board versions with external clock. The latest design and the one we keep using standard now, uses a differential pair of PNP transistors (BFT91), this will have a moderate gain of x10 or so and the resistors set for making a limited wave of 0 to 3.0V (simple change of resistors can make it 0-2.0V or else required). we use a 100MHz narrow band limited bandwidth sin signal so no filter added, but we could add if we need one. The output signal into the FPGA looks very clean and has a few ns rise and fall times (not super steep, but the fpga input does the rest. It does depend also on the resistor values and current used in the transistor pair). This was the way we could get the very minimum clock jitter in the FPGA and a simple circuit quite tolerant to input levels and make a very clean and well defined signal into the FPGA. Way better than 74F or 74LV gates etc. The only inconvenience is that it needs +5V for the circuit to work (the VCCIO of +3.3V is not enough). My 2 euro cents ;-) Luis Cupido ct1dmk. On 7/22/2012 9:32 PM, Bill Fuqua wrote: Wow, I have not checked this list for some time. But there is a lot said about zero crossing detectors. Lots and lots of replies, so many that I have not looked at all of them. 1. Do not use CMOS inverters. Even though so much has been published on using these in linear mode by adding a feedback resistor, they can be a nightmare. The fast ones (74HC, 74AC, etc) have so much high frequency gain they are likely to take off into oscillation on their own. 2. The first thing you can do to get a good clean zero crossing is to reduce the noise. This means to pass it thru a narrow band pass filter such as a crystal filter. The narrower this filter is the closer to a pure sinewave it becomes and the less noise you have. 3. In research when we want a precise trigger we use what is called a constant fraction discriminator. This may not be needed if you have a very clean signal and its amplitude does not vary and you are wanting to trigger exactly at zero. But a constant fraction discriminator triggers on a point that is a constant fraction of the amplitude of the signal. They require a delay so that a fraction of the peak of the cycle can be compared with the rising edge of that cycle. This is mostly used with triggering on pulses of varying heights and when subnanosecond timing is required. My suggestion is to clean up your signal as much as possible and reduce noise bandwidth using a bandpass filter and then use a low noise amplifier for the front end of your zero-crossing detector. 73 Bill wa4lav ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions
Re: [time-nuts] Zero-Crossing Detector Design?
On 07/22/2012 01:39 AM, Bob Camp wrote: HI The Collins paper that Bruce referred to is the standard work on limiters / jitter / bandwidth. It can't and doesn't address all the possible issues in a full blown design. The math for the basic approach is all there though. Indeed. It's a good and recommended read. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
Maybe, it is on my list for the university IEEE download for months. And this is the only reference? I have seen some similar issues in a few BPSK receiver papers. Not for time-nuting but for S/N. - Henry Magnus Danielson schrieb: On 07/22/2012 01:39 AM, Bob Camp wrote: HI The Collins paper that Bruce referred to is the standard work on limiters / jitter / bandwidth. It can't and doesn't address all the possible issues in a full blown design. The math for the basic approach is all there though. Indeed. It's a good and recommended read. -- ehydra.dyndns.info ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
Hi There are papers on limiters in radio IF's going back at least into the 1930's. That's a long... list. Bob On Jul 22, 2012, at 3:36 PM, ehydra wrote: Maybe, it is on my list for the university IEEE download for months. And this is the only reference? I have seen some similar issues in a few BPSK receiver papers. Not for time-nuting but for S/N. - Henry Magnus Danielson schrieb: On 07/22/2012 01:39 AM, Bob Camp wrote: HI The Collins paper that Bruce referred to is the standard work on limiters / jitter / bandwidth. It can't and doesn't address all the possible issues in a full blown design. The math for the basic approach is all there though. Indeed. It's a good and recommended read. -- ehydra.dyndns.info ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
Wow, I have not checked this list for some time. But there is a lot said about zero crossing detectors. Lots and lots of replies, so many that I have not looked at all of them. 1. Do not use CMOS inverters. Even though so much has been published on using these in linear mode by adding a feedback resistor, they can be a nightmare. The fast ones (74HC, 74AC, etc) have so much high frequency gain they are likely to take off into oscillation on their own. 2. The first thing you can do to get a good clean zero crossing is to reduce the noise. This means to pass it thru a narrow band pass filter such as a crystal filter. The narrower this filter is the closer to a pure sinewave it becomes and the less noise you have. 3. In research when we want a precise trigger we use what is called a constant fraction discriminator. This may not be needed if you have a very clean signal and its amplitude does not vary and you are wanting to trigger exactly at zero. But a constant fraction discriminator triggers on a point that is a constant fraction of the amplitude of the signal. They require a delay so that a fraction of the peak of the cycle can be compared with the rising edge of that cycle. This is mostly used with triggering on pulses of varying heights and when subnanosecond timing is required. My suggestion is to clean up your signal as much as possible and reduce noise bandwidth using a bandpass filter and then use a low noise amplifier for the front end of your zero-crossing detector. 73 Bill wa4lav ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
Hi The feedback inverter is indeed a problem with fast logic, just bias it to mid point off the supply instead. Narrow filters can be both a good and a bad thing at the same time. They clean up the signal, but the also have delay. If they are narrow enough they have lots of delay. That would be ok, except it drifts with temperature. It also changes with input frequency. You can do a delay correction stage to help with the frequency variation part, but the delay correction adds more delay that's also temperature dependent. No easy solutions …. Bob On Jul 22, 2012, at 4:32 PM, Bill Fuqua wrote: Wow, I have not checked this list for some time. But there is a lot said about zero crossing detectors. Lots and lots of replies, so many that I have not looked at all of them. 1. Do not use CMOS inverters. Even though so much has been published on using these in linear mode by adding a feedback resistor, they can be a nightmare. The fast ones (74HC, 74AC, etc) have so much high frequency gain they are likely to take off into oscillation on their own. 2. The first thing you can do to get a good clean zero crossing is to reduce the noise. This means to pass it thru a narrow band pass filter such as a crystal filter. The narrower this filter is the closer to a pure sinewave it becomes and the less noise you have. 3. In research when we want a precise trigger we use what is called a constant fraction discriminator. This may not be needed if you have a very clean signal and its amplitude does not vary and you are wanting to trigger exactly at zero. But a constant fraction discriminator triggers on a point that is a constant fraction of the amplitude of the signal. They require a delay so that a fraction of the peak of the cycle can be compared with the rising edge of that cycle. This is mostly used with triggering on pulses of varying heights and when subnanosecond timing is required. My suggestion is to clean up your signal as much as possible and reduce noise bandwidth using a bandpass filter and then use a low noise amplifier for the front end of your zero-crossing detector. 73 Bill wa4lav ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
Narrow filters have high tempco on their group delay, so that's no good either. Didier KO4BB Bill Fuqua wlfuq...@uky.edu wrote: Wow, I have not checked this list for some time. But there is a lot said about zero crossing detectors. Lots and lots of replies, so many that I have not looked at all of them. 1. Do not use CMOS inverters. Even though so much has been published on using these in linear mode by adding a feedback resistor, they can be a nightmare. The fast ones (74HC, 74AC, etc) have so much high frequency gain they are likely to take off into oscillation on their own. 2. The first thing you can do to get a good clean zero crossing is to reduce the noise. This means to pass it thru a narrow band pass filter such as a crystal filter. The narrower this filter is the closer to a pure sinewave it becomes and the less noise you have. 3. In research when we want a precise trigger we use what is called a constant fraction discriminator. This may not be needed if you have a very clean signal and its amplitude does not vary and you are wanting to trigger exactly at zero. But a constant fraction discriminator triggers on a point that is a constant fraction of the amplitude of the signal. They require a delay so that a fraction of the peak of the cycle can be compared with the rising edge of that cycle. This is mostly used with triggering on pulses of varying heights and when subnanosecond timing is required. My suggestion is to clean up your signal as much as possible and reduce noise bandwidth using a bandpass filter and then use a low noise amplifier for the front end of your zero-crossing detector. 73 Bill wa4lav ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. -- Sent from my Motorola Droid Razr phone with K-9 Mail. Please excuse my brevity. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
On 7/22/2012 2:41 PM, Bob Camp wrote: Hi The feedback inverter is indeed a problem with fast logic, just bias it to mid point off the supply instead. 1. Do not use CMOS inverters. Even though so much has been published on using these in linear mode by adding a feedback resistor, they can be a nightmare. The fast ones (74HC, 74AC, etc) have so much high frequency gain they are likely to take off into oscillation on their own. YMMV, but in the 5071A cesium standard I designed in a 74AC00 biased at half the supply voltage to make an 80 MHz clock from a sine wave. We never observed oscillations. The feedback resistor method may be optimum for getting the gate at the exact center of its range which might encourage oscillation. We did not have a requirement that the gate is stable with no input, like it might need to be if it were a front panel input on an instrument. Rick ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
Good, I've learned also that bandwidth can matter and that a ZCD test can done by comparison: feed the counter or TSC or TimePod or 'scope with your source signal and 2 cables, then insert the ZCD and see the difference. Actually I'm interested in a ZCD to feed the FPGA from the OCXO, I'm using a 74HC04 with feedback followed by a regular 74HC04. On Sat, Jul 21, 2012 at 4:15 AM, John Miles jmi...@pop.net wrote: I see that from one way or the other, we always end up in a TimePod. OK, then the TimePod has no comparator, no trigger but has A to D conversions. Is the A/D conversion process supposed to be threshold-free? Hey, everybody needs at least one or two TimePods. :) You can use a TimePod or TSC 512xA to measure additive jitter, or for that matter a mixer and a delay line. But these instruments will all do the job by making a phase noise measurement, then integrating the plot to find the equivalent RMS time jitter. This means that you'll have to decide what limits of integration you want to use. A counter, on the other hand, will give you the total jitter seen across its entire front-end bandwidth, so there is less thinking involved. The trouble is, any good shaper or ZCD will have very low jitter, perhaps too low for even a Wavecrest-class TIC to measure. This is what Wenzel's quick-and-dirty differential amp with a pair of 2N3906s looks like, when the splitter test mentioned by Bob is performed with a TimePod, TSC or other phase noise analyzer: http://www.wenzel.com/documents/waveform.html http://www.ke5fx.com/wenzel_shaper_resid_jitter.png That's about 100 fs of additive jitter, measured between 0.1 Hz and 100 kHz. Because the broadband floor is relatively high, a great deal of the total jitter comes from the higher decades. (The circuit's jitter contribution between 0.1 Hz and 100 Hz is only about 10 fs.) A counter will not be limited by the 100 kHz or 1 MHz integration range of a TimePod or TSC 5120, so you might see enough jitter to be noticeable on a Wavecrest in the 1 to 10-ps neighborhood. But maybe you only care about jitter at lower offsets... in which case the counter will make your shaper look a lot worse than it really is. For instance, if the reason you're investigating ZCDs is because you want to build a DMTD, then you may be more interested in a residual ADEV plot instead. The pair of bipolars contributes white and flicker PM noise, so its residual ADEV at t=1s isn't too different from the residual jitter in the ADEV measurement bandwidth, which was 500 Hz in this case: http://www.ke5fx.com/wenzel_shaper_resid_ADEV.png It's worth noting that I made these measurements on a TSC 5120A. The phase noise measurement could have been made on a TimePod, but the residual ADEV plot could not, as it's below the TimePod's ADEV floor. To me, this says that there are better ways to spend one's time than designing a fancy multistage ZCD. The important thing is to consider how much bandwidth is really required in your application, and whether/how it should be limited. -- john, KE5FX Miles Design LLC ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
Only for the Nuts, ZCD have been discussed at great length this time and before, and bandwidth can be a major issue, but still much is being left out. With a little care, one can easily get to 1ns type accuracy, with the various suggestions, but that only gives 1e-9 / sec of accuracy, not even close to what is needed so as not to degrade the short term accuracy of a basic OCXO like a HP10811. For that it takes sub-picosecond type phase / time stability and repeatability, and to get to that level, it takes a whole lot more considerations. If you want to see how bad things really are, try and check out the sub-picosecond drift that even a very small temperature change or signal amplitude change can have on any of the Schmitt triggers or the suggested multi-stage band-limited ZCD designs. ws *** Good, I've learned also that bandwidth can matter and that a ZCD test can done by comparison: feed the counter or TSC or TimePod or 'scope with your source signal and 2 cables, then insert the ZCD and see the difference. Actually I'm interested in a ZCD to feed the FPGA from the OCXO, I'm using a 74HC04 with feedback followed by a regular 74HC04. On Sat, Jul 21, 2012 at 4:15 AM, John Miles jmiles at pop.net wrote: I see that from one way or the other, we always end up in a TimePod. OK, then the TimePod has no comparator, no trigger but has A to D conversions. Is the A/D conversion process supposed to be threshold-free? Hey, everybody needs at least one or two TimePods. :) You can use a TimePod or TSC 512xA to measure additive jitter, or for that matter a mixer and a delay line. But these instruments will all do the job by making a phase noise measurement, then integrating the plot to find the equivalent RMS time jitter. This means that you'll have to decide what limits of integration you want to use. A counter, on the other hand, will give you the total jitter seen across its entire front-end bandwidth, so there is less thinking involved. The trouble is, any good shaper or ZCD will have very low jitter, perhaps too low for even a Wavecrest-class TIC to measure. This is what Wenzel's quick-and-dirty differential amp with a pair of 2N3906s looks like, when the splitter test mentioned by Bob is performed with a TimePod, TSC or other phase noise analyzer: http://www.wenzel.com/documents/waveform.html http://www.ke5fx.com/wenzel_shaper_resid_jitter.png That's about 100 fs of additive jitter, measured between 0.1 Hz and 100 kHz. Because the broadband floor is relatively high, a great deal of the total jitter comes from the higher decades. (The circuit's jitter contribution between 0.1 Hz and 100 Hz is only about 10 fs.) A counter will not be limited by the 100 kHz or 1 MHz integration range of a TimePod or TSC 5120, so you might see enough jitter to be noticeable on a Wavecrest in the 1 to 10-ps neighborhood. But maybe you only care about jitter at lower offsets... in which case the counter will make your shaper look a lot worse than it really is. For instance, if the reason you're investigating ZCDs is because you want to build a DMTD, then you may be more interested in a residual ADEV plot instead. The pair of bipolars contributes white and flicker PM noise, so its residual ADEV at t=1s isn't too different from the residual jitter in the ADEV measurement bandwidth, which was 500 Hz in this case: http://www.ke5fx.com/wenzel_shaper_resid_ADEV.png It's worth noting that I made these measurements on a TSC 5120A. The phase noise measurement could have been made on a TimePod, but the residual ADEV plot could not, as it's below the TimePod's ADEV floor. To me, this says that there are better ways to spend one's time than designing a fancy multistage ZCD. The important thing is to consider how much bandwidth is really required in your application, and whether/how it should be limited. -- john, KE5FX Miles Design LLC ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
Interesting discussion but I must say I had several times a brain-problem here ;-) Am I right that for that this is in general not fully understood? Are there interesting papers? I'm interested here for two points: 1. What is the right threshold for a comparator and on what it depends? Looks like bandwidth of input signal, slew-rate of the comparator, noise in the input signal. Maybe more. Surely most of all people here know how to set the trigger right practical. But what is the academic answer to this problem in the view of maximum S/N behind the comparator? 2. What if this is a if-strip amp with interstage filters. Maybe in the look of a BPSK receiver. So we can connect to time-nuts GPS interests back ;-) Recall that the jitter of a trigger point is noise divided by slew-rate. Is it possible to expand here the explanation? Any reference? Thanks! - Henry Magnus Danielson schrieb: You can view the schmitt trigger detector as having a state, and when in proximity of the trigger point, you let the noise control when the trigger point occurs. Schmitt trigger is a nice tool, but it can do you great harm if you do not understand what it does help you with and what it doesn't help you with. You need to gain yourself to slew-rates where a schmitt trigger would do no harm, and when you are there it will do essentially no good either, as you are looking at a high slew-rate square signal. So, you *can* do better than a Schmitt trigger. A schmitt trigger can be sufficiently good. A schmitt trigger can work well if you have filtering in front of it to significantly reduce unwanted systematic noise. -- ehydra.dyndns.info ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
HI The Collins paper that Bruce referred to is the standard work on limiters / jitter / bandwidth. It can't and doesn't address all the possible issues in a full blown design. The math for the basic approach is all there though. Bob On Jul 21, 2012, at 6:45 PM, ehydra wrote: Interesting discussion but I must say I had several times a brain-problem here ;-) Am I right that for that this is in general not fully understood? Are there interesting papers? I'm interested here for two points: 1. What is the right threshold for a comparator and on what it depends? Looks like bandwidth of input signal, slew-rate of the comparator, noise in the input signal. Maybe more. Surely most of all people here know how to set the trigger right practical. But what is the academic answer to this problem in the view of maximum S/N behind the comparator? 2. What if this is a if-strip amp with interstage filters. Maybe in the look of a BPSK receiver. So we can connect to time-nuts GPS interests back ;-) Recall that the jitter of a trigger point is noise divided by slew-rate. Is it possible to expand here the explanation? Any reference? Thanks! - Henry Magnus Danielson schrieb: You can view the schmitt trigger detector as having a state, and when in proximity of the trigger point, you let the noise control when the trigger point occurs. Schmitt trigger is a nice tool, but it can do you great harm if you do not understand what it does help you with and what it doesn't help you with. You need to gain yourself to slew-rates where a schmitt trigger would do no harm, and when you are there it will do essentially no good either, as you are looking at a high slew-rate square signal. So, you *can* do better than a Schmitt trigger. A schmitt trigger can be sufficiently good. A schmitt trigger can work well if you have filtering in front of it to significantly reduce unwanted systematic noise. -- ehydra.dyndns.info ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
On 07/20/2012 07:42 AM, Chris Albertson wrote: On Thu, Jul 19, 2012 at 5:47 PM, Rick Karlquistrich...@karlquist.com wrote: Hysteresis does nothing to eliminate jitter or temperature Maybe, but it is absolutely needed if there is any noise on the signal. A perfect comparator with zero hysteresis would dither on every zero crossing. Yes, and this dither is due to the additive noise on the signal. The slew-rate at and about the trigger point will determine how much of that additive noise is converted into time-noise. The schmitt trigger is there to make sure that you surpress the dither around each transition, but it will not help you to remove the time polution, as the first time the dither occurs, is bound to be early and bound to be controlled by the noise. Those, the noise will shift the trigger point. You can view the schmitt trigger detector as having a state, and when in proximity of the trigger point, you let the noise control when the trigger point occurs. If you noise is pure gaussian noise, this is not so bad, since the trigger point will be shifted by the noise RMS, but it will be noisy. If you have say a sine signal, then the non-linearity of the trigger point will act like a mixer and it will cause the time jitter to be spread out, and the peak-to-peak amplitude of the signal will when divided by the slew-rate of the trigger point convert to the peak-to-peak time modulation at that frequency. The distribution has a very steep bath-tub look, since the sine spend most of it times at its extremes (where it's slew-rates are low) but very little time in the middle (where it's slew-rate are high). The sine signal would modulate the trigger point up and down on the slope it's at. The schmitt trigger action doesn't help to protect this behaviour. Schmitt trigger is a nice tool, but it can do you great harm if you do not understand what it does help you with and what it doesn't help you with. You need to gain yourself to slew-rates where a schmitt trigger would do no harm, and when you are there it will do essentially no good either, as you are looking at a high slew-rate square signal. So, you *can* do better than a Schmitt trigger. A schmitt trigger can be sufficiently good. A schmitt trigger can work well if you have filtering in front of it to significantly reduce unwanted systematic noise. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
OK, very interesting. Now is it possible to measure/verify this? I think that using any test equipment, the comparator-style approach is unavoidable: the trigger of the scope or the counter cannot be an amplifier/limiter. How to tell what is up to my design under test and what is the trigger contribution? Maybe only by comparison: test design A then design B and see which is better... On Fri, Jul 20, 2012 at 2:31 PM, Magnus Danielson mag...@rubidium.dyndns.org wrote: On 07/20/2012 07:42 AM, Chris Albertson wrote: On Thu, Jul 19, 2012 at 5:47 PM, Rick Karlquistrich...@karlquist.com wrote: Hysteresis does nothing to eliminate jitter or temperature Maybe, but it is absolutely needed if there is any noise on the signal. A perfect comparator with zero hysteresis would dither on every zero crossing. Yes, and this dither is due to the additive noise on the signal. The slew-rate at and about the trigger point will determine how much of that additive noise is converted into time-noise. The schmitt trigger is there to make sure that you surpress the dither around each transition, but it will not help you to remove the time polution, as the first time the dither occurs, is bound to be early and bound to be controlled by the noise. Those, the noise will shift the trigger point. You can view the schmitt trigger detector as having a state, and when in proximity of the trigger point, you let the noise control when the trigger point occurs. If you noise is pure gaussian noise, this is not so bad, since the trigger point will be shifted by the noise RMS, but it will be noisy. If you have say a sine signal, then the non-linearity of the trigger point will act like a mixer and it will cause the time jitter to be spread out, and the peak-to-peak amplitude of the signal will when divided by the slew-rate of the trigger point convert to the peak-to-peak time modulation at that frequency. The distribution has a very steep bath-tub look, since the sine spend most of it times at its extremes (where it's slew-rates are low) but very little time in the middle (where it's slew-rate are high). The sine signal would modulate the trigger point up and down on the slope it's at. The schmitt trigger action doesn't help to protect this behaviour. Schmitt trigger is a nice tool, but it can do you great harm if you do not understand what it does help you with and what it doesn't help you with. You need to gain yourself to slew-rates where a schmitt trigger would do no harm, and when you are there it will do essentially no good either, as you are looking at a high slew-rate square signal. So, you *can* do better than a Schmitt trigger. A schmitt trigger can be sufficiently good. A schmitt trigger can work well if you have filtering in front of it to significantly reduce unwanted systematic noise. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
Hi Simple test: 1) Run sine wave into a power splitter 2) Run one port to your limiter / zero crossing detector / what ever 3) Run other port from the power splitter into the reference port on a DTMD, 5125, or (better yet) TimePod. 4) Route the output of the limiter to the input port on the instrument. You may need to convert it back to a sine wave for some of the above gear. What you read on the instrument will be the jitter added by the detector. None of them use a comparator on the input. Bob On Jul 20, 2012, at 6:09 PM, Azelio Boriani wrote: OK, very interesting. Now is it possible to measure/verify this? I think that using any test equipment, the comparator-style approach is unavoidable: the trigger of the scope or the counter cannot be an amplifier/limiter. How to tell what is up to my design under test and what is the trigger contribution? Maybe only by comparison: test design A then design B and see which is better... On Fri, Jul 20, 2012 at 2:31 PM, Magnus Danielson mag...@rubidium.dyndns.org wrote: On 07/20/2012 07:42 AM, Chris Albertson wrote: On Thu, Jul 19, 2012 at 5:47 PM, Rick Karlquistrich...@karlquist.com wrote: Hysteresis does nothing to eliminate jitter or temperature Maybe, but it is absolutely needed if there is any noise on the signal. A perfect comparator with zero hysteresis would dither on every zero crossing. Yes, and this dither is due to the additive noise on the signal. The slew-rate at and about the trigger point will determine how much of that additive noise is converted into time-noise. The schmitt trigger is there to make sure that you surpress the dither around each transition, but it will not help you to remove the time polution, as the first time the dither occurs, is bound to be early and bound to be controlled by the noise. Those, the noise will shift the trigger point. You can view the schmitt trigger detector as having a state, and when in proximity of the trigger point, you let the noise control when the trigger point occurs. If you noise is pure gaussian noise, this is not so bad, since the trigger point will be shifted by the noise RMS, but it will be noisy. If you have say a sine signal, then the non-linearity of the trigger point will act like a mixer and it will cause the time jitter to be spread out, and the peak-to-peak amplitude of the signal will when divided by the slew-rate of the trigger point convert to the peak-to-peak time modulation at that frequency. The distribution has a very steep bath-tub look, since the sine spend most of it times at its extremes (where it's slew-rates are low) but very little time in the middle (where it's slew-rate are high). The sine signal would modulate the trigger point up and down on the slope it's at. The schmitt trigger action doesn't help to protect this behaviour. Schmitt trigger is a nice tool, but it can do you great harm if you do not understand what it does help you with and what it doesn't help you with. You need to gain yourself to slew-rates where a schmitt trigger would do no harm, and when you are there it will do essentially no good either, as you are looking at a high slew-rate square signal. So, you *can* do better than a Schmitt trigger. A schmitt trigger can be sufficiently good. A schmitt trigger can work well if you have filtering in front of it to significantly reduce unwanted systematic noise. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
I see that from one way or the other, we always end up in a TimePod. OK, then the TimePod has no comparator, no trigger but has A to D conversions. Is the A/D conversion process supposed to be threshold-free? Maybe, in this case, the DTMD is the only analog and threshold-free way. On Sat, Jul 21, 2012 at 12:37 AM, Bob Camp li...@rtty.us wrote: Hi Simple test: 1) Run sine wave into a power splitter 2) Run one port to your limiter / zero crossing detector / what ever 3) Run other port from the power splitter into the reference port on a DTMD, 5125, or (better yet) TimePod. 4) Route the output of the limiter to the input port on the instrument. You may need to convert it back to a sine wave for some of the above gear. What you read on the instrument will be the jitter added by the detector. None of them use a comparator on the input. Bob On Jul 20, 2012, at 6:09 PM, Azelio Boriani wrote: OK, very interesting. Now is it possible to measure/verify this? I think that using any test equipment, the comparator-style approach is unavoidable: the trigger of the scope or the counter cannot be an amplifier/limiter. How to tell what is up to my design under test and what is the trigger contribution? Maybe only by comparison: test design A then design B and see which is better... On Fri, Jul 20, 2012 at 2:31 PM, Magnus Danielson mag...@rubidium.dyndns.org wrote: On 07/20/2012 07:42 AM, Chris Albertson wrote: On Thu, Jul 19, 2012 at 5:47 PM, Rick Karlquistrich...@karlquist.com wrote: Hysteresis does nothing to eliminate jitter or temperature Maybe, but it is absolutely needed if there is any noise on the signal. A perfect comparator with zero hysteresis would dither on every zero crossing. Yes, and this dither is due to the additive noise on the signal. The slew-rate at and about the trigger point will determine how much of that additive noise is converted into time-noise. The schmitt trigger is there to make sure that you surpress the dither around each transition, but it will not help you to remove the time polution, as the first time the dither occurs, is bound to be early and bound to be controlled by the noise. Those, the noise will shift the trigger point. You can view the schmitt trigger detector as having a state, and when in proximity of the trigger point, you let the noise control when the trigger point occurs. If you noise is pure gaussian noise, this is not so bad, since the trigger point will be shifted by the noise RMS, but it will be noisy. If you have say a sine signal, then the non-linearity of the trigger point will act like a mixer and it will cause the time jitter to be spread out, and the peak-to-peak amplitude of the signal will when divided by the slew-rate of the trigger point convert to the peak-to-peak time modulation at that frequency. The distribution has a very steep bath-tub look, since the sine spend most of it times at its extremes (where it's slew-rates are low) but very little time in the middle (where it's slew-rate are high). The sine signal would modulate the trigger point up and down on the slope it's at. The schmitt trigger action doesn't help to protect this behaviour. Schmitt trigger is a nice tool, but it can do you great harm if you do not understand what it does help you with and what it doesn't help you with. You need to gain yourself to slew-rates where a schmitt trigger would do no harm, and when you are there it will do essentially no good either, as you are looking at a high slew-rate square signal. So, you *can* do better than a Schmitt trigger. A schmitt trigger can be sufficiently good. A schmitt trigger can work well if you have filtering in front of it to significantly reduce unwanted systematic noise. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
On 07/21/2012 12:09 AM, Azelio Boriani wrote: OK, very interesting. Now is it possible to measure/verify this? I think that using any test equipment, the comparator-style approach is unavoidable: the trigger of the scope or the counter cannot be an amplifier/limiter. If you like to verify what I described, a scope is a good starting-point. Using a sine of say 10 MHz and then adding a sine of say 1 kHz, you can fool around with trigger point, noise-signal level and source level and essentially learn it. Try trigger at zero-crossing, try trigger near the peaks. Vary the modulation signal amplitude. How to tell what is up to my design under test and what is the trigger contribution? Maybe only by comparison: test design A then design B and see which is better... Varying the amplitudes is one thing. It's a good stress test. I assume you have means to measure it. Doing what I proposed above is also a good stress-test, add a noise signal and see how much you must have for it to cause serious harm. I got myself a TimePod for a reason. I also use a CSA-803A scope when I need to. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
Yes, using a 'scope and the persistence it seems possible to visualize the results. On Sat, Jul 21, 2012 at 1:03 AM, Magnus Danielson mag...@rubidium.dyndns.org wrote: On 07/21/2012 12:09 AM, Azelio Boriani wrote: OK, very interesting. Now is it possible to measure/verify this? I think that using any test equipment, the comparator-style approach is unavoidable: the trigger of the scope or the counter cannot be an amplifier/limiter. If you like to verify what I described, a scope is a good starting-point. Using a sine of say 10 MHz and then adding a sine of say 1 kHz, you can fool around with trigger point, noise-signal level and source level and essentially learn it. Try trigger at zero-crossing, try trigger near the peaks. Vary the modulation signal amplitude. How to tell what is up to my design under test and what is the trigger contribution? Maybe only by comparison: test design A then design B and see which is better... Varying the amplitudes is one thing. It's a good stress test. I assume you have means to measure it. Doing what I proposed above is also a good stress-test, add a noise signal and see how much you must have for it to cause serious harm. I got myself a TimePod for a reason. I also use a CSA-803A scope when I need to. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
albertson.ch...@gmail.com said: Hysteresis does nothing to eliminate jitter or temperature Maybe, but it is absolutely needed if there is any noise on the signal. A perfect comparator with zero hysteresis would dither on every zero crossing. Hysteresis doesn't eliminate the dither from noise. Assume 5 volt CMOS logic with a switching point at 2.5 V. With hysteresis, the low-to high direction switches at (say) 3 V and the high-to-low direction switches at 2 V. If you have noise, whatever happens at 2.5 V without hysteresis happens at 3V with hysteresis. Actually, if you are working with a sine wave, shifting the switching point off center will make the problem worse since the slope will be reduced. Hysterssis will eliminate spikes or double pulses that are caused by noise on a signal with low rise time as long as the noise isn't too big. -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
On 07/21/2012 01:28 AM, Azelio Boriani wrote: Yes, using a 'scope and the persistence it seems possible to visualize the results. Exactly. It's very instructive to see the traces separate appart as result of deterministic jitter, or just see the soft edges from the random jitter. I forgot to mention, you typically view the rising transition one cycle off. For some scopes one need to feed the trigger separately and what I do is use a powersplitter hooked straight onto the trigger input, and then use a coax to compensate for the trigger delay + some offset. It's the difference in delay between trigger input and sampling input which needs to be sufficiently high. This way I can view the trigger point completely, and I can also observe the 1 cycle jitter effect. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
On 07/21/2012 01:41 AM, Hal Murray wrote: albertson.ch...@gmail.com said: Hysteresis does nothing to eliminate jitter or temperature Maybe, but it is absolutely needed if there is any noise on the signal. A perfect comparator with zero hysteresis would dither on every zero crossing. Hysteresis doesn't eliminate the dither from noise. Assume 5 volt CMOS logic with a switching point at 2.5 V. With hysteresis, the low-to high direction switches at (say) 3 V and the high-to-low direction switches at 2 V. If you have noise, whatever happens at 2.5 V without hysteresis happens at 3V with hysteresis. Actually, if you are working with a sine wave, shifting the switching point off center will make the problem worse since the slope will be reduced. Hysterssis will eliminate spikes or double pulses that are caused by noise on a signal with low rise time as long as the noise isn't too big. ... which is what he called dither. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
On 07/21/2012 03:30 AM, Hal Murray wrote: albertson.ch...@gmail.com said: Maybe, but it is absolutely needed if there is any noise on the signal. A perfect comparator with zero hysteresis would dither on every zero crossing. On 07/21/2012 01:41 AM, Hal Murray wrote: Hysterssis will eliminate spikes or double pulses that are caused by noise on a signal with low rise time as long as the noise isn't too big. mag...@rubidium.dyndns.org said: ... which is what he called dither. OK, I need a few hints. What is dither in this context and what does it have to do with hysteresis? I think of dither as being related to noise at the sampling level. In that context, hysteresis just shifts the switching point. It doesn't change anything (much) related to noise. How does that translate into eliminating spikes or double pulses? The jump about around the sampling point which non-schmitt triggered comparators shows results in a signal which is _similar_ to a dithered signal. It causes multiple spikes. The schmitt trigger will shift it's trigger level depending on state to avoid this. Exactly what to call the forrest of spikes for a non-hysteresis trigger is to the best of my knoweldge not really well established. Dither is similar enough to work. Oh, and the dithering noise does not need to be applied specifically, you may use the noise that is there. It works for GPS receivers. It's only when you don't have enough noise that you need to apply it, so the Wikipedia article is incorrect in that aspect. But if you object to the term dither to be applied for this jumping around, then propose a better term. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
I see that from one way or the other, we always end up in a TimePod. OK, then the TimePod has no comparator, no trigger but has A to D conversions. Is the A/D conversion process supposed to be threshold-free? Hey, everybody needs at least one or two TimePods. :) You can use a TimePod or TSC 512xA to measure additive jitter, or for that matter a mixer and a delay line. But these instruments will all do the job by making a phase noise measurement, then integrating the plot to find the equivalent RMS time jitter. This means that you'll have to decide what limits of integration you want to use. A counter, on the other hand, will give you the total jitter seen across its entire front-end bandwidth, so there is less thinking involved. The trouble is, any good shaper or ZCD will have very low jitter, perhaps too low for even a Wavecrest-class TIC to measure. This is what Wenzel's quick-and-dirty differential amp with a pair of 2N3906s looks like, when the splitter test mentioned by Bob is performed with a TimePod, TSC or other phase noise analyzer: http://www.wenzel.com/documents/waveform.html http://www.ke5fx.com/wenzel_shaper_resid_jitter.png That's about 100 fs of additive jitter, measured between 0.1 Hz and 100 kHz. Because the broadband floor is relatively high, a great deal of the total jitter comes from the higher decades. (The circuit's jitter contribution between 0.1 Hz and 100 Hz is only about 10 fs.) A counter will not be limited by the 100 kHz or 1 MHz integration range of a TimePod or TSC 5120, so you might see enough jitter to be noticeable on a Wavecrest in the 1 to 10-ps neighborhood. But maybe you only care about jitter at lower offsets... in which case the counter will make your shaper look a lot worse than it really is. For instance, if the reason you're investigating ZCDs is because you want to build a DMTD, then you may be more interested in a residual ADEV plot instead. The pair of bipolars contributes white and flicker PM noise, so its residual ADEV at t=1s isn't too different from the residual jitter in the ADEV measurement bandwidth, which was 500 Hz in this case: http://www.ke5fx.com/wenzel_shaper_resid_ADEV.png It's worth noting that I made these measurements on a TSC 5120A. The phase noise measurement could have been made on a TimePod, but the residual ADEV plot could not, as it's below the TimePod's ADEV floor. To me, this says that there are better ways to spend one's time than designing a fancy multistage ZCD. The important thing is to consider how much bandwidth is really required in your application, and whether/how it should be limited. -- john, KE5FX Miles Design LLC ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] Zero-Crossing Detector Design?
Can anyone suggest a good reference design for a zero-crossing detector? I am trying to home an ADC sampler trigger to the 1VRMS (50ohm) 10MHz sin from my XL-DC... And now I'm thinking that I should just home the uC clock to it, as well. Essentially, I believe that I'm looking for an efficient, stable, and accurate sine-to-square converter... and I'll welcome any advice in this area. This may also be used in a 1KHz 5Vpp IRIG-B decoder... I don't feel like rectifying the signal, to be honest. I want to try to keep a smaller BOM, sense the waveform primarily, and crunch numbers inside the uC. -CH Chris Hoffman cq.k...@gmail.com http://ar.ctur.us ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
This is sort of a FAQ: the argument was already discussed here. One of the most interesting idea (in my opinion) is to use an RS485 line receiver like the ST3485, MAX483, ADM485. They are actually transceivers so they must be tied permanently in RX. Since they are differential you can also put a 1:1 (or a 1:4 to raise the level) transformer to isolate the input too. On Thu, Jul 19, 2012 at 6:03 PM, Chris Hoffman cq.k...@gmail.com wrote: Can anyone suggest a good reference design for a zero-crossing detector? I am trying to home an ADC sampler trigger to the 1VRMS (50ohm) 10MHz sin from my XL-DC... And now I'm thinking that I should just home the uC clock to it, as well. Essentially, I believe that I'm looking for an efficient, stable, and accurate sine-to-square converter... and I'll welcome any advice in this area. This may also be used in a 1KHz 5Vpp IRIG-B decoder... I don't feel like rectifying the signal, to be honest. I want to try to keep a smaller BOM, sense the waveform primarily, and crunch numbers inside the uC. -CH Chris Hoffman cq.k...@gmail.com http://ar.ctur.us ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
Thank you, Azelio! I don't suppose there's an impromptu FAQ page out there, is there? -CH On Jul 19, 2012, at 11:58, Azelio Boriani azelio.bori...@screen.it wrote: This is sort of a FAQ: the argument was already discussed here. One of the most interesting idea (in my opinion) is to use an RS485 line receiver like the ST3485, MAX483, ADM485. They are actually transceivers so they must be tied permanently in RX. Since they are differential you can also put a 1:1 (or a 1:4 to raise the level) transformer to isolate the input too. On Thu, Jul 19, 2012 at 6:03 PM, Chris Hoffman cq.k...@gmail.com wrote: Can anyone suggest a good reference design for a zero-crossing detector? I am trying to home an ADC sampler trigger to the 1VRMS (50ohm) 10MHz sin from my XL-DC... And now I'm thinking that I should just home the uC clock to it, as well. Essentially, I believe that I'm looking for an efficient, stable, and accurate sine-to-square converter... and I'll welcome any advice in this area. This may also be used in a 1KHz 5Vpp IRIG-B decoder... I don't feel like rectifying the signal, to be honest. I want to try to keep a smaller BOM, sense the waveform primarily, and crunch numbers inside the uC. -CH Chris Hoffman cq.k...@gmail.com http://ar.ctur.us ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
you can search time-nuts there has been a number of very good discussions on this. Sorry to say how you search is equally a good question. On Thu, Jul 19, 2012 at 3:19 PM, Chris Hoffman, KG6O cq.k...@gmail.comwrote: Thank you, Azelio! I don't suppose there's an impromptu FAQ page out there, is there? -CH On Jul 19, 2012, at 11:58, Azelio Boriani azelio.bori...@screen.it wrote: This is sort of a FAQ: the argument was already discussed here. One of the most interesting idea (in my opinion) is to use an RS485 line receiver like the ST3485, MAX483, ADM485. They are actually transceivers so they must be tied permanently in RX. Since they are differential you can also put a 1:1 (or a 1:4 to raise the level) transformer to isolate the input too. On Thu, Jul 19, 2012 at 6:03 PM, Chris Hoffman cq.k...@gmail.com wrote: Can anyone suggest a good reference design for a zero-crossing detector? I am trying to home an ADC sampler trigger to the 1VRMS (50ohm) 10MHz sin from my XL-DC... And now I'm thinking that I should just home the uC clock to it, as well. Essentially, I believe that I'm looking for an efficient, stable, and accurate sine-to-square converter... and I'll welcome any advice in this area. This may also be used in a 1KHz 5Vpp IRIG-B decoder... I don't feel like rectifying the signal, to be honest. I want to try to keep a smaller BOM, sense the waveform primarily, and crunch numbers inside the uC. -CH Chris Hoffman cq.k...@gmail.com http://ar.ctur.us ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
Yes, there are no FAQ but you can search the archive. I don't know how to search the archive because usually I start with google, adding time-nuts to narrow down the search. On Thu, Jul 19, 2012 at 9:23 PM, paul swed paulsw...@gmail.com wrote: you can search time-nuts there has been a number of very good discussions on this. Sorry to say how you search is equally a good question. On Thu, Jul 19, 2012 at 3:19 PM, Chris Hoffman, KG6O cq.k...@gmail.com wrote: Thank you, Azelio! I don't suppose there's an impromptu FAQ page out there, is there? -CH On Jul 19, 2012, at 11:58, Azelio Boriani azelio.bori...@screen.it wrote: This is sort of a FAQ: the argument was already discussed here. One of the most interesting idea (in my opinion) is to use an RS485 line receiver like the ST3485, MAX483, ADM485. They are actually transceivers so they must be tied permanently in RX. Since they are differential you can also put a 1:1 (or a 1:4 to raise the level) transformer to isolate the input too. On Thu, Jul 19, 2012 at 6:03 PM, Chris Hoffman cq.k...@gmail.com wrote: Can anyone suggest a good reference design for a zero-crossing detector? I am trying to home an ADC sampler trigger to the 1VRMS (50ohm) 10MHz sin from my XL-DC... And now I'm thinking that I should just home the uC clock to it, as well. Essentially, I believe that I'm looking for an efficient, stable, and accurate sine-to-square converter... and I'll welcome any advice in this area. This may also be used in a 1KHz 5Vpp IRIG-B decoder... I don't feel like rectifying the signal, to be honest. I want to try to keep a smaller BOM, sense the waveform primarily, and crunch numbers inside the uC. -CH Chris Hoffman cq.k...@gmail.com http://ar.ctur.us ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
The problem of optimal zero crossing detector design was essentially solved by Oliver Collins in the 1990's. Essentially a series of cascaded limiter stages with appropriate gain and bandwidth distribution are used. With a 10MHz 1V rms signal only 2-3 stages suffices. However unless you need fs jitter less complex zero crossing detectors should suffice. 1) a comparator (or line receiver) based design should achieve sub 10ps jitter. 2) AC coupling to the input of a CMOS (AC04, AHC04 LVC04) should achieve a jitter of 1ps or less 3) A simple differential pair with AC coupled emitters (reduces asymmetry due to component tolerances ) is capable of sub ps jitter. There is a spreadsheet to assist design of Collins style zero crossing detectors at: http://www.ko4bb.com/~bruce/ZeroCrossingDetectors.html http://www.ko4bb.com/%7Ebruce/ZeroCrossingDetectors.html Bruce paul swed wrote: you can search time-nuts there has been a number of very good discussions on this. Sorry to say how you search is equally a good question. On Thu, Jul 19, 2012 at 3:19 PM, Chris Hoffman, KG6Ocq.k...@gmail.comwrote: Thank you, Azelio! I don't suppose there's an impromptu FAQ page out there, is there? -CH On Jul 19, 2012, at 11:58, Azelio Borianiazelio.bori...@screen.it wrote: This is sort of a FAQ: the argument was already discussed here. One of the most interesting idea (in my opinion) is to use an RS485 line receiver like the ST3485, MAX483, ADM485. They are actually transceivers so they must be tied permanently in RX. Since they are differential you can also put a 1:1 (or a 1:4 to raise the level) transformer to isolate the input too. On Thu, Jul 19, 2012 at 6:03 PM, Chris Hoffmancq.k...@gmail.com wrote: Can anyone suggest a good reference design for a zero-crossing detector? I am trying to home an ADC sampler trigger to the 1VRMS (50ohm) 10MHz sin from my XL-DC... And now I'm thinking that I should just home the uC clock to it, as well. Essentially, I believe that I'm looking for an efficient, stable, and accurate sine-to-square converter... and I'll welcome any advice in this area. This may also be used in a 1KHz 5Vpp IRIG-B decoder... I don't feel like rectifying the signal, to be honest. I want to try to keep a smaller BOM, sense the waveform primarily, and crunch numbers inside the uC. -CH Chris Hoffman cq.k...@gmail.com http://ar.ctur.us ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
Actually, I being new to the list, I do not feel I the correct verbiage. That said, I will do better on keeping the noise down. Again, my thanks. -CH On Jul 19, 2012, at 12:23, paul swed paulsw...@gmail.com wrote: you can search time-nuts there has been a number of very good discussions on this. Sorry to say how you search is equally a good question. On Thu, Jul 19, 2012 at 3:19 PM, Chris Hoffman, KG6O cq.k...@gmail.comwrote: Thank you, Azelio! I don't suppose there's an impromptu FAQ page out there, is there? -CH On Jul 19, 2012, at 11:58, Azelio Boriani azelio.bori...@screen.it wrote: This is sort of a FAQ: the argument was already discussed here. One of the most interesting idea (in my opinion) is to use an RS485 line receiver like the ST3485, MAX483, ADM485. They are actually transceivers so they must be tied permanently in RX. Since they are differential you can also put a 1:1 (or a 1:4 to raise the level) transformer to isolate the input too. On Thu, Jul 19, 2012 at 6:03 PM, Chris Hoffman cq.k...@gmail.com wrote: Can anyone suggest a good reference design for a zero-crossing detector? I am trying to home an ADC sampler trigger to the 1VRMS (50ohm) 10MHz sin from my XL-DC... And now I'm thinking that I should just home the uC clock to it, as well. Essentially, I believe that I'm looking for an efficient, stable, and accurate sine-to-square converter... and I'll welcome any advice in this area. This may also be used in a 1KHz 5Vpp IRIG-B decoder... I don't feel like rectifying the signal, to be honest. I want to try to keep a smaller BOM, sense the waveform primarily, and crunch numbers inside the uC. -CH Chris Hoffman cq.k...@gmail.com http://ar.ctur.us ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
Thank you, Bruce!!! That is exactly the information I was looking for. I sincerely appreciate the help. -CH On Jul 19, 2012, at 12:47, Bruce Griffiths bruce.griffi...@xtra.co.nz wrote: The problem of optimal zero crossing detector design was essentially solved by Oliver Collins in the 1990's. Essentially a series of cascaded limiter stages with appropriate gain and bandwidth distribution are used. With a 10MHz 1V rms signal only 2-3 stages suffices. However unless you need fs jitter less complex zero crossing detectors should suffice. 1) a comparator (or line receiver) based design should achieve sub 10ps jitter. 2) AC coupling to the input of a CMOS (AC04, AHC04 LVC04) should achieve a jitter of 1ps or less 3) A simple differential pair with AC coupled emitters (reduces asymmetry due to component tolerances ) is capable of sub ps jitter. There is a spreadsheet to assist design of Collins style zero crossing detectors at: http://www.ko4bb.com/~bruce/ZeroCrossingDetectors.html http://www.ko4bb.com/%7Ebruce/ZeroCrossingDetectors.html Bruce paul swed wrote: you can search time-nuts there has been a number of very good discussions on this. Sorry to say how you search is equally a good question. On Thu, Jul 19, 2012 at 3:19 PM, Chris Hoffman, KG6Ocq.k...@gmail.comwrote: Thank you, Azelio! I don't suppose there's an impromptu FAQ page out there, is there? -CH On Jul 19, 2012, at 11:58, Azelio Borianiazelio.bori...@screen.it wrote: This is sort of a FAQ: the argument was already discussed here. One of the most interesting idea (in my opinion) is to use an RS485 line receiver like the ST3485, MAX483, ADM485. They are actually transceivers so they must be tied permanently in RX. Since they are differential you can also put a 1:1 (or a 1:4 to raise the level) transformer to isolate the input too. On Thu, Jul 19, 2012 at 6:03 PM, Chris Hoffmancq.k...@gmail.com wrote: Can anyone suggest a good reference design for a zero-crossing detector? I am trying to home an ADC sampler trigger to the 1VRMS (50ohm) 10MHz sin from my XL-DC... And now I'm thinking that I should just home the uC clock to it, as well. Essentially, I believe that I'm looking for an efficient, stable, and accurate sine-to-square converter... and I'll welcome any advice in this area. This may also be used in a 1KHz 5Vpp IRIG-B decoder... I don't feel like rectifying the signal, to be honest. I want to try to keep a smaller BOM, sense the waveform primarily, and crunch numbers inside the uC. -CH Chris Hoffman cq.k...@gmail.com http://ar.ctur.us ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
On the Bruce page there is a table with increasing stage amplification from low-level to the output. If this is the optimum for low jitter how does it connect to the well-known rf design philosophy to have the highest amplification at the first stage, not the last stage, to have maximum S/N ? Any idea? - Henry Chris Hoffman, KG6O schrieb: Thank you, Bruce!!! That is exactly the information I was looking for. I sincerely appreciate the help. -CH On Jul 19, 2012, at 12:47, Bruce Griffiths bruce.griffi...@xtra.co.nz wrote: The problem of optimal zero crossing detector design was essentially solved by Oliver Collins in the 1990's. Essentially a series of cascaded limiter stages with appropriate gain and bandwidth distribution are used. With a 10MHz 1V rms signal only 2-3 stages suffices. However unless you need fs jitter less complex zero crossing detectors should suffice. 1) a comparator (or line receiver) based design should achieve sub 10ps jitter. 2) AC coupling to the input of a CMOS (AC04, AHC04 LVC04) should achieve a jitter of 1ps or less 3) A simple differential pair with AC coupled emitters (reduces asymmetry due to component tolerances ) is capable of sub ps jitter. There is a spreadsheet to assist design of Collins style zero crossing detectors at: http://www.ko4bb.com/~bruce/ZeroCrossingDetectors.html http://www.ko4bb.com/%7Ebruce/ZeroCrossingDetectors.html ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
Hi The numbers change rather dramatically if you are looking at the 1 to 10 Hz sine wave out of a beat note system… Bob On Jul 19, 2012, at 3:47 PM, Bruce Griffiths wrote: The problem of optimal zero crossing detector design was essentially solved by Oliver Collins in the 1990's. Essentially a series of cascaded limiter stages with appropriate gain and bandwidth distribution are used. With a 10MHz 1V rms signal only 2-3 stages suffices. However unless you need fs jitter less complex zero crossing detectors should suffice. 1) a comparator (or line receiver) based design should achieve sub 10ps jitter. 2) AC coupling to the input of a CMOS (AC04, AHC04 LVC04) should achieve a jitter of 1ps or less 3) A simple differential pair with AC coupled emitters (reduces asymmetry due to component tolerances ) is capable of sub ps jitter. There is a spreadsheet to assist design of Collins style zero crossing detectors at: http://www.ko4bb.com/~bruce/ZeroCrossingDetectors.html http://www.ko4bb.com/%7Ebruce/ZeroCrossingDetectors.html Bruce paul swed wrote: you can search time-nuts there has been a number of very good discussions on this. Sorry to say how you search is equally a good question. On Thu, Jul 19, 2012 at 3:19 PM, Chris Hoffman, KG6Ocq.k...@gmail.comwrote: Thank you, Azelio! I don't suppose there's an impromptu FAQ page out there, is there? -CH On Jul 19, 2012, at 11:58, Azelio Borianiazelio.bori...@screen.it wrote: This is sort of a FAQ: the argument was already discussed here. One of the most interesting idea (in my opinion) is to use an RS485 line receiver like the ST3485, MAX483, ADM485. They are actually transceivers so they must be tied permanently in RX. Since they are differential you can also put a 1:1 (or a 1:4 to raise the level) transformer to isolate the input too. On Thu, Jul 19, 2012 at 6:03 PM, Chris Hoffmancq.k...@gmail.com wrote: Can anyone suggest a good reference design for a zero-crossing detector? I am trying to home an ADC sampler trigger to the 1VRMS (50ohm) 10MHz sin from my XL-DC... And now I'm thinking that I should just home the uC clock to it, as well. Essentially, I believe that I'm looking for an efficient, stable, and accurate sine-to-square converter... and I'll welcome any advice in this area. This may also be used in a 1KHz 5Vpp IRIG-B decoder... I don't feel like rectifying the signal, to be honest. I want to try to keep a smaller BOM, sense the waveform primarily, and crunch numbers inside the uC. -CH Chris Hoffman cq.k...@gmail.com http://ar.ctur.us ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
On 07/19/2012 11:53 PM, ehydra wrote: On the Bruce page there is a table with increasing stage amplification from low-level to the output. If this is the optimum for low jitter how does it connect to the well-known rf design philosophy to have the highest amplification at the first stage, not the last stage, to have maximum S/N ? Any idea? You balance noise bandwidth with slew-rate gain. Normally you just look at the noise of the amplifiers and comes up with the traditional gain formula. Here you only want the first amplifier to have the bandwidth that supports the slew-rate it will have, in the same way the next amplifier's bandwidth and gain is set to optimum. The goal becomes to achieve optimum slew-rate gain with least added noise. The formulas in the article is derived for same amplifier noise, where as Bruce generalized them for the case where the amplifier noises may be different. So, different design goals makes for different solutions. Makes sense or should I go into more detail? Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
Are you speaking of slew rate limiting in the strict sense of the word, that is a current starved input stage due to the presence of a compensation cap? Or are you using the term slew more vaguely. -Original Message- From: Magnus Danielson mag...@rubidium.dyndns.org Sender: time-nuts-boun...@febo.com Date: Fri, 20 Jul 2012 00:15:58 To: time-nuts@febo.com Reply-To: Discussion of precise time and frequency measurement time-nuts@febo.com Subject: Re: [time-nuts] Zero-Crossing Detector Design? On 07/19/2012 11:53 PM, ehydra wrote: On the Bruce page there is a table with increasing stage amplification from low-level to the output. If this is the optimum for low jitter how does it connect to the well-known rf design philosophy to have the highest amplification at the first stage, not the last stage, to have maximum S/N ? Any idea? You balance noise bandwidth with slew-rate gain. Normally you just look at the noise of the amplifiers and comes up with the traditional gain formula. Here you only want the first amplifier to have the bandwidth that supports the slew-rate it will have, in the same way the next amplifier's bandwidth and gain is set to optimum. The goal becomes to achieve optimum slew-rate gain with least added noise. The formulas in the article is derived for same amplifier noise, where as Bruce generalized them for the case where the amplifier noises may be different. So, different design goals makes for different solutions. Makes sense or should I go into more detail? Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
Are you speaking of slew rate limiting in the strict sense of the word, that is a current starved input stage due to the presence of a compensation cap? Or are you using the term slew more vaguely. -Original Message- From: Magnus Danielson mag...@rubidium.dyndns.org Sender: time-nuts-boun...@febo.com Date: Fri, 20 Jul 2012 00:15:58 To: time-nuts@febo.com Reply-To: Discussion of precise time and frequency measurement time-nuts@febo.com Subject: Re: [time-nuts] Zero-Crossing Detector Design? On 07/19/2012 11:53 PM, ehydra wrote: On the Bruce page there is a table with increasing stage amplification from low-level to the output. If this is the optimum for low jitter how does it connect to the well-known rf design philosophy to have the highest amplification at the first stage, not the last stage, to have maximum S/N ? Any idea? You balance noise bandwidth with slew-rate gain. Normally you just look at the noise of the amplifiers and comes up with the traditional gain formula. Here you only want the first amplifier to have the bandwidth that supports the slew-rate it will have, in the same way the next amplifier's bandwidth and gain is set to optimum. The goal becomes to achieve optimum slew-rate gain with least added noise. The formulas in the article is derived for same amplifier noise, where as Bruce generalized them for the case where the amplifier noises may be different. So, different design goals makes for different solutions. Makes sense or should I go into more detail? Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
A fast comparator seems like a good idea, and it is simple, however it is actually the last thing you want to use. High thermal sensitivity and high jitter. Rick On 7/19/2012 1:35 PM, Dan Kemppainen wrote: Or use a fast comparator such as an ADCMP600 series. Much lower delays, and faster rising/falling edges. FYI, I've had good luck with this at 30Mhz. You could transformer couple this one, or simply couple it through a cap. Dan On 7/19/2012 3:47 PM, time-nuts-requ...@febo.com wrote: This is sort of a FAQ: the argument was already discussed here. One of the most interesting idea (in my opinion) is to use an RS485 line receiver like the ST3485, MAX483, ADM485. They are actually transceivers so they must be tied permanently in RX. Since they are differential you can also put a 1:1 (or a 1:4 to raise the level) transformer to isolate the input too. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
On 07/20/2012 12:33 AM, li...@lazygranch.com wrote: Are you speaking of slew rate limiting in the strict sense of the word, that is a current starved input stage due to the presence of a compensation cap? Or are you using the term slew more vaguely. I am speaking neither. If you have a sine of a particular frequency and amplitude, then you have a known slew-rate, it peaks at 2*pi*f*A, where A is the amplitude of the sine. As you amplify this signal, the slew-rate will grow proportionally. Recall that the jitter of a trigger point is noise divided by slew-rate. This is why we want to increase the slew-rate to a maximum while adding minimal noise. Now, as the amplifiers has a gain, to increase the slew-rate by say 5 times, the bandwidth of the amplifier needs to be high enough to support this, but in order to minimize the added noise, we want to keep the bandwidth down. This may be best realized by also recalling that it is the wideband noise at the trigger points which this first-degree analysis depends on, and the RMS level. A 1 Hz amplifier bandwidth is nice, but it won't support a high slew-rate... In a two amp setup the later amp will have a higher bandwidth, but the noise added of the first amp will also be gained up, so a tigther bandwidth there will keep its contribution lower. You end up with having high benefit for low noise amps in the beginning, but as you gain slew-rate the amplifier slew-rate capability becomes more important over it's noise properties. It's being balanced by amplifier feedback terms for both gain and bandwidth. Also, diode limiters will maintain the output as clipped sine, so we can continue to gain the output for slopes. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
On 07/20/2012 12:57 AM, Richard (Rick) Karlquist wrote: A fast comparator seems like a good idea, and it is simple, however it is actually the last thing you want to use. High thermal sensitivity and high jitter. Once your signal has past by a comparator, you can't treat it to remove the noise-induced jitter. As you gain the signal, the slew-rates can be made steeper and steeper prior to the comparator. The benefit of a comparator is that if you add hysteresis, it stays in that position and does not cause transition spikes, which can cause false extra triggers, with resulting state-polution. You can see this on some counters when you trigger them on a slope with bad slew-rate... and the frequency goes unstably up. This is when the experienced trims the trigger point for lower jitter (better slew-rate). Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
That was worth the elaboration. 2*pi*f*A is the classic design criteria used to insure your amplifier has sufficient slew rate for the task, where I am using slew in the strict sense of the word. Generally we use dv/dt when referring to the signal and slew when referring to the amplifier. Hey, some people say alligator clips and some say crocodile clips. (Yeah, I know there is a difference.) ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
On 07/20/2012 01:19 AM, li...@lazygranch.com wrote: That was worth the elaboration. 2*pi*f*A is the classic design criteria used to insure your amplifier has sufficient slew rate for the task, where I am using slew in the strict sense of the word. Generally we use dv/dt when referring to the signal and slew when referring to the amplifier. Hey, some people say alligator clips and some say crocodile clips. (Yeah, I know there is a difference.) In a DMTD setup, the amplifiers will operate very closely to the signal properties, so in that case the distinction becomes almost academic. Notice how I say that bandwidth (rather than slew) and gain is being controlled and calculated, which implies the slew-rate of the outgoing signal. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
Chris, The simplest zero crossing detector would be to feed your 1 volt, 10 mHz from the XL-DC into the input of an IC with schmidt trigger inputs. You would need to provide a series coupling cap and probably some DC bias from a pot to adjust symmetry of the output. I would also think that if you ran the four or six inverters of a schmidt trigger inverter chip in series that you would get a pretty good square wave out the end. I have an XL-DC with four 10 mHz sine outputs but have not had the need yet for a square wave. For that matter, it may be posible to find a 10 mHz square wave somewhere inside the box before it is converted to a sine wave that could be used for your application. Al Subject: [time-nuts] Zero-Crossing Detector Design? Can anyone suggest a good reference design for a zero-crossing detector? I am trying to home an ADC sampler trigger to the 1VRMS (50ohm) 10MHz sin from my XL-DC... And now I'm thinking that I should just home the uC clock to it, as well. Essentially, I believe that I'm looking for an efficient, stable, and accurate sine-to-square converter... and I'll welcome any advice in this area. This may also be used in a 1KHz 5Vpp IRIG-B decoder... I don't feel like rectifying the signal, to be honest. I want to try to keep a smaller BOM, sense the waveform primarily, and crunch numbers inside the uC. -CH Chris Hoffman cq.k...@gmail.com http://ar.ctur.us ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
On 07/19/2012 07:36 PM, Al Wolfe wrote: Chris, The simplest zero crossing detector would be to feed your 1 volt, 10 mHz from the XL-DC into the input of an IC with schmidt trigger inputs. You would need to provide a series coupling cap and probably some DC bias from a pot to adjust symmetry of the output. I would also think that if you ran the four or six inverters of a schmidt trigger inverter chip in series that you would get a pretty good square wave out the end. One circuit I was recommended when I was looking for ideas uses a 1M resistor to feed the output of the inverter back to the input to self-bias, like this: http://partiallystapled.com/~gxti/circuits/2012/07/06-beanpole.png I'm also trying a discrete approach based on the TADD-2 / T2-mini: http://partiallystapled.com/~gxti/circuits/2012/07/06-tadpole.png The latter has definitely been used successfully in timing applications but the simplicity of the inverter approach is very appealing, so I'm giving both a test, along with some other miscellaneous GPSDO components, before proceeding with a full GPSDO. -- m. tharp ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
Michael wrote: One circuit I was recommended when I was looking for ideas uses a 1M resistor to feed the output of the inverter back to the input to self-bias That works OK, but you have to be careful. Without an input signal, there can be excessive quiescent current through the inverter (Vcc to ground) -- for which it was not designed. Best regards, Charles ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
Hi I think I'd call that a limiter rather than a zero crossing detector, that is indeed a bit picky. I think you will have better luck with a fixed bias on the input to the first inverter rather than with the 1 meg feedback resistor. With the feedback resistor the inverter tends to self oscillate. The self biased stage tends to go to one or the other state when the input is removed. With either approach, you will get the best performance when the AC signal is almost over-driving the input. Bob On Jul 19, 2012, at 8:23 PM, Michael Tharp wrote: On 07/19/2012 07:36 PM, Al Wolfe wrote: Chris, The simplest zero crossing detector would be to feed your 1 volt, 10 mHz from the XL-DC into the input of an IC with schmidt trigger inputs. You would need to provide a series coupling cap and probably some DC bias from a pot to adjust symmetry of the output. I would also think that if you ran the four or six inverters of a schmidt trigger inverter chip in series that you would get a pretty good square wave out the end. One circuit I was recommended when I was looking for ideas uses a 1M resistor to feed the output of the inverter back to the input to self-bias, like this: http://partiallystapled.com/~gxti/circuits/2012/07/06-beanpole.png I'm also trying a discrete approach based on the TADD-2 / T2-mini: http://partiallystapled.com/~gxti/circuits/2012/07/06-tadpole.png The latter has definitely been used successfully in timing applications but the simplicity of the inverter approach is very appealing, so I'm giving both a test, along with some other miscellaneous GPSDO components, before proceeding with a full GPSDO. -- m. tharp ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
On Thu, Jul 19, 2012 at 3:57 PM, Richard (Rick) Karlquist rich...@karlquist.com wrote: A fast comparator seems like a good idea, and it is simple, however it is actually the last thing you want to use. High thermal sensitivity and high jitter. The comparator will work but you need some positive feedback to create hysteresis. The problem is the hysteresis cause the output square wave to be not quite 50% duty cycle. But maybe you don't care if the goal is to count cycles. or if you only look at (say) raising edges. Rick On 7/19/2012 1:35 PM, Dan Kemppainen wrote: Or use a fast comparator such as an ADCMP600 series. Much lower delays, and faster rising/falling edges. FYI, I've had good luck with this at 30Mhz. You could transformer couple this one, or simply couple it through a cap. Dan On 7/19/2012 3:47 PM, time-nuts-requ...@febo.com wrote: This is sort of a FAQ: the argument was already discussed here. One of the most interesting idea (in my opinion) is to use an RS485 line receiver like the ST3485, MAX483, ADM485. They are actually transceivers so they must be tied permanently in RX. Since they are differential you can also put a 1:1 (or a 1:4 to raise the level) transformer to isolate the input too. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. -- Chris Albertson Redondo Beach, California ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
Chris Albertson wrote: The comparator will work but you need some positive feedback to create hysteresis. The problem is the hysteresis cause the output square wave to be not quite 50% duty cycle. But maybe you don't care if the goal is to count cycles. or if you only look at (say) raising edges. Hysteresis does nothing to eliminate jitter or temperature drift. Rick ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
The reason I suggested using a schmidt trigger gate is that a schmidt trigger gate switches states at different points at its input. That is, the input positive going switch point is higher than the negative going switch point, maybe half a volt or so. So, driving this gate with a volt RMS or so (3 volts P to P) from the XL-DC should give pretty noiseless, chatter free results. Used to use them all the time to generate 60 Hz square waves from the power mains. Probably work OK at 10 mHz. Al Chris, The simplest zero crossing detector would be to feed your 1 volt, 10 mHz from the XL-DC into the input of an IC with schmidt trigger inputs. You snip ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
On 7/19/12 4:09 PM, Magnus Danielson wrote: On 07/20/2012 12:33 AM, li...@lazygranch.com wrote: Are you speaking of slew rate limiting in the strict sense of the word, that is a current starved input stage due to the presence of a compensation cap? Or are you using the term slew more vaguely. I am speaking neither. If you have a sine of a particular frequency and amplitude, then you have a known slew-rate, it peaks at 2*pi*f*A, where A is the amplitude of the sine. As you amplify this signal, the slew-rate will grow proportionally. Recall that the jitter of a trigger point is noise divided by slew-rate. This is why we want to increase the slew-rate to a maximum while adding minimal noise. snip nice simple explanation... ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Zero-Crossing Detector Design?
On Thu, Jul 19, 2012 at 5:47 PM, Rick Karlquist rich...@karlquist.com wrote: Hysteresis does nothing to eliminate jitter or temperature Maybe, but it is absolutely needed if there is any noise on the signal. A perfect comparator with zero hysteresis would dither on every zero crossing. Chris Albertson Redondo Beach, California ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
