Hi Will,
Given that you already have an FPGA in the system I'll assume that you are
comfortable with digital solutions. Have a look at
https://www.analog.com/en/products/ad7402.html ; it's a 1-bit sigma-delta
modulator with a built-in galvanic isolation for its output. TI and ST have
similar
Dear Joe,
Thank you for your mail; always happy with the dialogue.
In a way we have come full circle; the Sherman/Jördens NIST paper was one
of my primary references for the design I made last summer. (It would have
been helpful had I linked to it upthread; I could have sworn I had done so,
but
are there).
JDB.
On Sun, Feb 23, 2020 at 10:13 PM Bob kb8tq wrote:
> Hi
>
> What does the temperature coefficient of your “hardware HPF” filter caps
> look like?
> Are they a type that has significant hysteresis?
>
> Bob
>
> > On Feb 23, 2020, at 3:05 PM, Jan-Derk
od evening!
>
> I'm going through some old stuff...
>
>
> On Wed, 27 Nov 2019 00:29:19 +0100
> Jan-Derk Bakker wrote:
>
> > This has yielded a combined "simple" signal
> > processing path of a differentiator, a double comb filter and the offset
> > estim
Dear Magnus,
Removing the slope between the two sample end points (or: trimming/adding
the fractional sample part of the period) is the point of the estimator I
posted earlier (
http://lists.febo.com/pipermail/time-nuts_lists.febo.com/2019-November/098450.html
).
In general: as much as I like
Dear Joe,
On Wed, Nov 27, 2019 at 7:22 PM Joseph Gwinn wrote:
> > [snip]
> > The 1001-point FIR band pass filter is a good reference to get an idea of
> > the best case performance of the system, but it is computationally
> > infeasible to run on an 8-bit processor. While a cheap comb filter
nce by a factor of 10 (if only by averaging all 100 samples rather
than just dropping 99 of them), mostly because it makes comparing sources
with different frequencies much easier (which is one of my use cases).
Any suggestions?
Once again to be continued,
JDB.
On Sun, Nov 3, 2019 at 1:41 AM Jan-D
gt; the phase noise or stability of the offset oscillator is not of very high
> importance in DMTD measurements.
>
> Best
> Tobias
> HB9FSX
>
> ________
> From: time-nuts [time-nuts-boun...@lists.febo.com] on behalf of Jan-Derk
> Bakker [jdbak...
gt;
> Why not just sample at 100 kHz?
>
> What am I missing ?
>
> Thanks for considering,
> Scott W7SLS
>
> > On Nov 3, 2019, at 12:59 PM, Jan-Derk Bakker wrote:
> >
> > Is this not caused by the fact that I'm currently subsampling the
will be fully correlated well inside the loop bandwidth. The
> loop bandwidth
> normally used for this sort of thing is >> 1 Hz. By the time you start
> doing ADEV, you
> are in the correlated region.
>
> Bob
>
> > On Nov 3, 2019, at 3:42 PM, Jan-Derk Bakker wro
Dear Attila,
> The test was run for 175k seconds (just over 2 days) in a very much
> > non-temperature controlled attic. The resulting ADEV can be found at
> > http://www.lartmaker.nl/time-nuts/DMTD%20self-noise%20ADEV.pdf ; the
>
> This looks good, but I would still expect the start of the ADEV
maser; I'm looking at a similar setup (with
the expected LO performance being significantly worse than the incoming
signals).
JDB.
On Sun, Nov 3, 2019 at 2:40 PM Bob kb8tq wrote:
> Hi
>
> > On Nov 2, 2019, at 8:41 PM, Jan-Derk Bakker wrote:
> >
> > Dear all,
> >
>
er to extend
the number of samples used by the ZCD without running into linearity
issues. Meanwhile I'm working on a daughterboard with twin Lattice iCE40
FPGAs.
Any suggestions so far?
To be continued,
JDB.
On Tue, Oct 22, 2019 at 12:33 AM Jan-Derk Bakker wrote:
> Dear Attila,
>
&g
Dear Attila,
Thank you for your feedback, replies inline:
On Tue, Oct 15, 2019 at 6:01 PM Attila Kinali wrote:
[snip]
> The biggest change I would make, would be to use a higher sampling
> frequency and use an FPGA with a CORDIC as phase detector. Especially
> as your goal is to measure the
; I expect to
be able to get back to the DMTD by the end of this month.
To be continued,
JDB.
[have not made any further attempts to get raw samples out of the FTDI-chip
yet, either]
On Sun, Sep 22, 2019 at 11:32 PM Jan-Derk Bakker wrote:
> Update: last Friday our students have populated
to get this working.
To be continued,
JDB.
[listadmin: do let me know if you feel these updates are more noise than
signal]
On Sat, Sep 14, 2019 at 2:25 PM Jan-Derk Bakker wrote:
> Update: I have finished routing the board (placement diagram at
> http://www.lartmaker.nl/time-nuts/DMTD%20r
the main PCB.
To be continued,
JDB.
On Sun, Sep 1, 2019 at 2:09 AM Jan-Derk Bakker wrote:
> Dear all,
>
> I've been working on a design for a (relatively) simple, standalone
> sampling DMTD. Very rough preliminary schematics can be found at
> http://www.lartmaker.nl/time-nuts/D
Correction:
On Sun, Sep 1, 2019 at 8:24 PM Jan-Derk Bakker wrote:
> Especially with the addition of the LPF the simulator is showing quite
> literally unbelievably good performance (example: running the ZCD over
> 1/40th of the sine for an input signal of 0dBm/-10dBFS gives sin
Dear Jim,
Thank you for your feedback.
The very short version: this design works 'on paper', but there are a few
undocumented unknowns that I can only resolve by actually building and
testing it.
>
> 1. The input bandwidth of the digitizer chip is 750 MHz (very
> impressive), but what happens
On Sat, Aug 24, 2019 at 10:31 PM Attila Kinali wrote:
> Another important thing to know with audio ADCs is, that they are
> almost always some sigma-delta variant. This gives them a high linearity
> and low noise with moderate cost. But that also means that the higher
> the bandwidth you are
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