[time-nuts] 1PPS questions

Are there any suggested method to reduce your 1 PPS signal to a safe level for your test equipment? It seems like my HP Z8316A is outputting slightly more than 5V into 50 Ohms. Up till now I have been using a 10 MHz output from the Z3816A. But I understand 1PPS is a better signal to put to

[time-nuts] Time goodies at Stuff Day

We weren't able to host our usual annual stuff day event in person this year, so it has all moved on line instead. You can see the items here: https://www.sphere.bc.ca/test/stuffday.html There is a special section just for *time fans* if

Re: [time-nuts] 30 MHz freq adjust by Hz

FB I was thinking of FM on the (30 MHz) carrier. (which the FM- the deviation  will multiply) . (A multiplication does not change the information rate  of course) BUT  you are right ! that's not what will happen, there is no FM !  there are (relatd) unmodulated discrete frequency

Re: [time-nuts] 30 MHz freq adjust by Hz

RRR Stability over about a 2 minute period, preferably within a Hz at 1296 MHz , IE about 1e-09 is all that is required. I'll make it and figure out what I missed :-). The unwanted sideband (and some of the original will of course leak through depending on the DBM balance) will generate

Re: [time-nuts] 30 MHz freq adjust by Hz

Hi The same “small fraction of a degree” and “small fraction of a db” issues that plagued the analog SSB generation process still get into this approach. For “good” ADEV you need spurs down below the -130 dbc range (and likely much lower). This only gets you to 60 db or so …. Bob > On Jul 1,

Re: [time-nuts] 30 MHz freq adjust by Hz

Hi Um …. e ….. If the phase spur is at 1.5 Hz at 10 MHz, it still will be at 1.5 Hz at 1296. The multiplication process does not change the offset frequency. What you *do* get is a change in level. If the spur is 40 db down at 10 MHz, then it goes up by 10 log (1296 / 10). Net

Re: [time-nuts] 30 MHz freq adjust by Hz

Hi Bob I imagine in physics there are times when you want an oscillator to move a few Hz for offset, and the oscillator is fixed due to some physical / atomic property. yes, the whole thing will be phase locked, so no issue with freq error. For a fixed frequency operation , +45 and -45 deg

Re: [time-nuts] low power divide by 5

On 7/1/20 1:41 PM, ed breya wrote: Yeah, I know. I was just lamenting the lack of nice medium-density count functions in 74AC. It's hard to beat the simplicity of a '390 when you Anyway, I've always liked having a wide assortment of MSI logic devices available in all families, that you

Re: [time-nuts] low power divide by 5

I designed a marine radio in 1976 that used 74LS161's. They could do something like 15 MHz on a good day at room temperature. I did a lot of characterization on them. 100 MHz? In your dreams... BTW, if you want to divide by ten in the LS family, the 74LS160 is a better choice, because it will

Re: [time-nuts] 30 MHz freq adjust by Hz

Hello Glen, Any progress on the Anylocker? I’d still like to get two for the FT817, 1pps input first choice, 10 MHz second choice. Cheers, Steve WB0DBS > On Jul 1, 2020, at 2:30 AM, glen english LIST > wrote: > > Hello group > > I have an idea that might work, and I wanted to discuss

Re: [time-nuts] low power divide by 5

There was once upon the time a very good data/application-book from Fairchild for TTL logic, they published many different modulo frequency dividers with 50% duty-cycle for the "9316" which is the functional equivalent grandfather  for 74161 and therefore for the AC161 to. For frequency

Re: [time-nuts] low power divide by 5

>When I was looking for a 100 MHz divide by 10 in a dip package I was advised by someone on the list to use the 74LS161. It's available on Ebay on ebay from several sources for reasonable prices. 74LS161 won't go that fast - 20-25 MHz is max. Pete On Wed, Jul 1, 2020 at 2:46 PM Perry Sandeen

Re: [time-nuts] low power divide by 5

Tom wrote: "Ed, For division, there's less need for a dedicated divide-by-10 counter since the '161 and '163 are *presettable* synchronous binary counters. As such you can wire them to divide by anything from 2 to 16, which includes 10. In addition they are *cascadable*, which means that you

[time-nuts] low power divide by 5

Learned List When I was looking for a 100 MHz divide by 10 in a dip package I was advised by someone on the list to use the 74LS161. It's available on Ebay on ebay from several sources for reasonable prices. Regards, Perrier ___ time-nuts mailing

Re: [time-nuts] 30 MHz freq adjust by Hz

Hi There is a NIST paper (somewhere) that has an example of doing this. Like any image reject mixer approach, it only does just so well. It’s no different than generating SSB the same way. You get a spur that is 40 to 60 db down at the “image” frequency. You can tweak this or that to get it

Re: [time-nuts] low power divide by 5

On 7/1/20 5:24 AM, Detlef Schuecker via time-nuts wrote: Hi, there are three JK-FF, with Q1 as MSB, Q3 as LSB. J1,K1 ist input to Q1, etc. . There are 8^6 possibilties (6 inputs to the Qx or QxNOT or to HIGH or to LOW) of which 2069 generate a cycle length of 5. The following wiring will

Re: [time-nuts] low power divide by 5

Just a thought: https://www.analog.com/media/en/technical-documentation/data-sheets/hmc438.pdf Although it isn't really 'low power', and the input and output ranges are somewhat limited. Certainly not logic level. Dan On 7/1/2020 2:50 AM, time-nuts-requ...@lists.febo.com wrote: Message:

Re: [time-nuts] FA 2 Counter variations

My FA-2 variation has: FA-2 Precision Freq Counter BG7TBL on the top left of the face plate. There is also a variation for frequency coverage. Mine is good to 12 GHz. Stan, W1LE On 7/1/2020 2:13 AM, Perry Sandeen via time-nuts wrote: Learned List, Checking the Ebay listings for the FA-2

[time-nuts] low power divide by 5

Hi, there are three JK-FF, with Q1 as MSB, Q3 as LSB. J1,K1 ist input to Q1, etc. . There are 8^6 possibilties (6 inputs to the Qx or QxNOT or to HIGH or to LOW) of which 2069 generate a cycle length of 5. The following wiring will generate the cycle 1 3 5 2 4 : J1=Q2 K1=Q1 J2=Q3 K2=Q2

Re: [time-nuts] low power divide by 5

hm, first example of divide by 5 needs an additional AND, second example gets stuck in an unused state :( Cheers Detlef Am 01.07.2020 um 02:14 schrieb David: Here's a web page with several JK flip-flop dividers, including divide by 5:

Re: [time-nuts] low power divide by 5

Am 01.07.20 um 03:04 schrieb Hal Murray: What logic family might be appropriate for a divide by 5 from 50 to 10MHz, low power, running off 3.3 or 5V? How important is the "low" power? Do you have other logic/CPU around? Do you need 50/50 duty cycle (or close) or is 20/80 OK? How about a CPU

Re: [time-nuts] low power divide by 5

Hi, As suggested by others, another approach could be to use a cpld of some type, for example look at the lattice mach or the old cool-runner varieties. You can usually DDR the clock. This should give the same symmetry as the input clock. With a 50% duty cycle 50MHz input this should give a

[time-nuts] FA 2 Counter variations

Learned List, Checking the Ebay listings for the FA-2 counter I saw three variations. One had just BG7TBL on the bottom of the face plate. A second -since deleted- had BG7TBL XX- XX- (date). A third one was labeled  BG7TBL 20190622. All had wildly different prices. So is this just some form

[time-nuts] 30 MHz freq adjust by Hz

Hello group I have an idea that might work, and I wanted to discuss  with likeminded that might already have experience with the problem. Shifting a fixed oscillator a few Hz using a image reject mixer. background : From time to time I (and others) make lock boards for ham gear, pulling the

Re: [time-nuts] low power divide by 5

Take a look at the "modified" shift-register like counter in the attached jpg file. When simulated online it behaved as expected for a divide by 5. I believe it also is self-clearing from illegal states, but the other simulator I tested that in wasn't good for documenting the design. Bob L. >

Re: [time-nuts] low power divide by 5

On 6/30/20 5:04 PM, Richard (Rick) Karlquist wrote: On 6/30/2020 3:47 PM, dschuecker wrote: Hi, a divide by five should possible with a synchronous state-machine made of 3 ( sufficiently fast-) JK-FlipFlops. All 3 FFs are clocked with the input freq. , the outputs of the FFs are fed back

Re: [time-nuts] low power divide by 5

> What logic family might be appropriate for a divide by 5 from 50 to 10MHz, > low power, running off 3.3 or 5V? How important is the "low" power? Do you have other logic/CPU around? Do you need 50/50 duty cycle (or close) or is 20/80 OK? How about a CPU with a counter/timer block setup to