Re: [time-nuts] 50/60 Hz clocks
On 03/22/2011 11:45 PM, Hal Murray wrote: mag...@rubidium.dyndns.org said: On the other hand, it would not be difficult to make a DDS which hit 60/ 1000 exactly. Reducing it by 20 on each side you get 3/50 so a 19 bit accumulator (mod 50) incrementing with 3 on every 100 ns period would do it. Neat. Thanks. I'd noticed that adding in decimal rather than binary would make exact target frequencies in some cases, but I hadn't generalized to adding modulo N. Using N of 10,000,000 with a 10 MHz clock gets you all exact integer frequencies in the audio range. Which was my main point... it doesn't have to be THAT complex. A 50 entry LUT is however expensive. A LUT for sine would be possible. Playing a few tricks with the LUT table (realizing that the LUT would be walked through three times with three different start-alignments) converts it into a LUT of the same size and a increment by one or decrement by one counter modulus 50. A decrement by one counter allows wrap-around loading with 49 easy. CPLD or CMOS/TTL implementations would be trivial for the counter. The LUT will be large... More neat. Thanks again. It's just a simple state machine cycling through some collection of states. Exactly. It really helps when trying to understand spurious response. A DDS has a large number of states and for most frequencies, all states will be visited before looping. A 32-bit DDS clocked at 10 MHz wraps in 429.4967296 s. Half the possible settings will wrap quicker (at various power of 2 variants). If we are willing to rearrange the LUT/ROM, we can simplify the next state calculation from a modulo adder to a re-loadable counter. Which is what I propose above. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 50/60 Hz clocks, start at 60M0 Hz
Just thinking here about making a 60M0 Hz oscillator and phase locking it to the 10M0 reference. Then divide the 60M0 by 1e6. Youve got a perfectly locked 60 Hz square wave. For low harmonic 60 Hz sine wave one can go for 480 Hz to start a Walsh -Hadamard converter. Take 60M0 divide by 125 (easy with a binary counter) then divide by 1000. Result is 480 Hz. Take the 480 Hz and build the output stage with a DG201 CMOS switches (or similar) and a couple of opamps. Result is very low harmonic perfectly locked 60 Hz signal ready to drive an audio amplifier. Greg On 3/23/2011 1:03 PM, Magnus Danielson wrote: On 03/22/2011 11:45 PM, Hal Murray wrote: mag...@rubidium.dyndns.org said: On the other hand, it would not be difficult to make a DDS which hit 60/ 1000 exactly. Reducing it by 20 on each side you get 3/50 so a 19 bit accumulator (mod 50) incrementing with 3 on every 100 ns period would do it. Neat. Thanks. I'd noticed that adding in decimal rather than binary would make exact target frequencies in some cases, but I hadn't generalized to adding modulo N. Using N of 10,000,000 with a 10 MHz clock gets you all exact integer frequencies in the audio range. Which was my main point... it doesn't have to be THAT complex. A 50 entry LUT is however expensive. A LUT for sine would be possible. Playing a few tricks with the LUT table (realizing that the LUT would be walked through three times with three different start-alignments) converts it into a LUT of the same size and a increment by one or decrement by one counter modulus 50. A decrement by one counter allows wrap-around loading with 49 easy. CPLD or CMOS/TTL implementations would be trivial for the counter. The LUT will be large... More neat. Thanks again. It's just a simple state machine cycling through some collection of states. Exactly. It really helps when trying to understand spurious response. A DDS has a large number of states and for most frequencies, all states will be visited before looping. A 32-bit DDS clocked at 10 MHz wraps in 429.4967296 s. Half the possible settings will wrap quicker (at various power of 2 variants). If we are willing to rearrange the LUT/ROM, we can simplify the next state calculation from a modulo adder to a re-loadable counter. Which is what I propose above. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 50/60 Hz clocks
On 03/10/2011 11:41 PM, Robert LaJeunesse wrote:
Poor man's solution: Use an Arduino to read the Thunderbolt 1PPS and lock a 50Hz
(or 60Hz) square wave to the 1PPS. Any resulting jitter can likely be kept in
Here is an even poorer man's solution (and plug):
A DDS using both compare outputs of an 8 pin part to get
a phase-centered PWM with half the usual ripple.
With PPS input as a bonus so the zero crossing occurs where
you want it to.
http://n1.taur.dk/gen60a.jpg
Output 5Vpp@60Hz +1.1mVpp@39kHz. Very pretty sinewave.
//
TinyAWG.c
// 60Hz generator - 2011 Kasper Pedersen - Beerware license
//
// This is an arbirtrary waveform generator set up to produce 60Hz sine
// Compile with GCC -Os
//
//
// 2-5V ---+-+
// | |
// |__ |
// | __|* |__|
// | | |__| VCC |__|---+--||--+
// 3k| | | | 1u |
// | __| |_ _|_
// 10MHz ---||--+|__| CLK LOCK|__| GND
// 1n | | |
// | |__| |_____ ___
// 3k| | |__| PPS PWM1|__|---___--+---___---+
// | | | 2k2 | 3k3 |
// | __| |_____ | |
// GND ---+|__| GND PWM0|__|---___--+--||--+--||--+-
// | |__| 2k2100n | 100n
// | ATTINY13V |60Hz out
// | |
// +-+
//
//
// Rising edge on PPS input (optional) will steer the output
// so that, after 128 edges, the positive zero crossing
// of the output will coincide with PPS.
// When this happens, LOCK will go high.
//
// PWM frequency is 39kHz
// first filter stage attenuates 27x
// second filter stage attenuates 81x and pulls phase 1 deg.
#includeavr/io.h
#includeavr/interrupt.h
#includeavr/pgmspace.h
#define DCBIAS 127
PROGMEM unsigned char table[256]={
127,130,133,136,139,142,145,149,152,155,158,161,164,167,169,172,
175,178,181,184,186,189,192,194,197,200,202,205,207,209,212,214,
216,218,220,222,224,226,228,230,232,233,235,237,238,240,241,242,
243,245,246,247,248,248,249,250,251,251,252,252,252,253,253,253,
253,253,253,253,252,252,252,251,251,250,249,248,248,247,246,245,
243,242,241,240,238,237,235,233,232,230,228,226,224,222,220,218,
216,214,212,209,207,205,202,200,197,194,192,189,186,184,181,178,
175,172,169,167,164,161,158,155,152,149,145,142,139,136,133,130,
127,124,121,118,115,112,109,105,102,99,96,93,90,87,85,82,
79,76,73,70,68,65,62,60,57,54,52,49,47,45,42,40,
38,36,34,32,30,28,26,24,22,21,19,17,16,14,13,12,
11,9,8,7,6,6,5,4,3,3,2,2,2,1,1,1,
1,1,1,1,2,2,2,3,3,4,5,6,6,7,8,9,
11,12,13,14,16,17,19,21,22,24,26,28,30,32,34,36,
38,40,42,45,47,49,52,54,57,60,62,65,68,70,73,76,
79,82,85,87,90,93,96,99,102,105,109,112,115,118,121,124};
unsigned char phase;
signed acc;
unsigned char lastp=1;
ISR(SIG_OVERFLOW0)
{
signed s;
unsigned char v;
//60Hz*256=15360Hz increment rate.
//irq rate is 10MHz/256=39062.5Hz.
//we need to increment at: 60*256*256 / 10M
//split into primes and eliminate common factors:
//10MHz = 2^7 * 5* 5^6
//60*256 *256 = 2^7 *2 * 5 *2*2*3 * 2^8
//scaler = 2*2*2*3*256 / 5*5*5*5*5*5
// = 6144 / 15625
v=__LPM(table[phase]); //generate output
OCR0A=v;
OCR0B=(2*DCBIAS)-v;
s=acc; //generate phase
s-=6144;
if (s0) {
acc= s+15625;
++phase;
} else {
acc= s;
}
if (PINB16) { //on rising edge: adjust phase so this conincides with
the positive zero crossing.
if (!lastp) { //we need 128 pulses to become adjusted
lastp=1;
if (!phase) {
//phase is 0. At 15kHz we are within 65us
PORTB|=4;
} else
if (phase0x80) {
++phase; // 65us adjustments
PORTB=~4;
} else {
--phase;
PORTB=~4;
}
}
} else {
lastp=0;
}
}
void main(void)
{
TCCR0A=0xB3; //A is clear on match, positive output when bigger
TCCR0B=0x01;
TIMSK0=0x02;
DDRB|=1; //output
DDRB|=2;
DDRB|=4; //locked output
PORTB|=16; //~50uA pullup on PPS pin.
sei();
for (;;);
}
Re: [time-nuts] 50/60 Hz clocks
Hi You can do the drop / add pulse thing with a sub 50 cent micro. The only real sorting function is that you rule out the ones that won't take an external 10 MHz clock. If you want pseudo sine wave with PWM that likely will fit. We're only driving a motor here, low distortion is hardly a requirement. Bob On Mar 23, 2011, at 7:20 PM, Chris Albertson wrote: On Wed, Mar 23, 2011 at 3:18 PM, Mark Sims hol...@hotmail.com wrote: it doesn't have to be THAT complex. A 50 entry LUT is however expensive. Yeah, might even cost as much as a whole US dollar (ragged as they are these days). 512 kbyte EPROMs can be had for under $1... connect the outputs to a resistor ladder (might need an output latch), filter, voila rather nice sine wave. I think if you really needed a 500K entry LUT then each entry would need to be 3 bytes wide or you loose the point of having a large table.So you are up to a 1.5 Mbyte table. That said a sine wave can be compressed. First off you only need to store 1/4 of the wave. Then because the function is monotonic you only need the deltas from the last sample and we assume the first sample is zero. The wide table could easy be compressed to 512K But even so, one can buy a small micro controller with way more than 1.5MB for only a few dollars. Or for that matter AD will give you sample DDS chips for free if you ask. -- = Chris Albertson Redondo Beach, California ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 50/60 Hz clocks
On Wed, Mar 23, 2011 at 4:23 PM, Bob Camp li...@rtty.us wrote: Hi We're only driving a motor here, low distortion is hardly a requirement. You mean this is for a mechanical clock? Then telk of a 512K LUT is pointless. You need only 8-bit samples and to shore 90 degrees of the sine function takes 64 bytes. Yes the entire sine wave generators would go into an 80 cent uP. that fits in an 8-pin package.. I've seen examples of this in higher-end battery backup supplies and power inverters. I think I had a desktop computer in about 1980 that I used for word processing mostly. Itwas far less then what now can fit into an 8pin dip and sell for under a buck. I remember it had a 4Mhz 8-bit CPU with about 32MB RAM -- = Chris Albertson Redondo Beach, California ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 50/60 Hz clocks
mag...@rubidium.dyndns.org said: On the other hand, it would not be difficult to make a DDS which hit 60/ 1000 exactly. Reducing it by 20 on each side you get 3/50 so a 19 bit accumulator (mod 50) incrementing with 3 on every 100 ns period would do it. Neat. Thanks. I'd noticed that adding in decimal rather than binary would make exact target frequencies in some cases, but I hadn't generalized to adding modulo N. Using N of 10,000,000 with a 10 MHz clock gets you all exact integer frequencies in the audio range. A LUT for sine would be possible. Playing a few tricks with the LUT table (realizing that the LUT would be walked through three times with three different start-alignments) converts it into a LUT of the same size and a increment by one or decrement by one counter modulus 50. A decrement by one counter allows wrap-around loading with 49 easy. CPLD or CMOS/TTL implementations would be trivial for the counter. The LUT will be large... More neat. Thanks again. It's just a simple state machine cycling through some collection of states. If we are willing to rearrange the LUT/ROM, we can simplify the next state calculation from a modulo adder to a re-loadable counter. -- These are my opinions, not necessarily my employer's. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 50/60 Hz clocks
Hi Since you are starting with a 100 ns pulse train as an input, you can bracket any period you need inside a 100 ns window. Put another way, your error will always be less than 100 ns. In this case you would either be off by 33.3 ns or 66.6 ns. A mechanical clock is not going to notice jitter in the sub microsecond region. Put out the periods in a 2:1 ratio and you have a 60 Hz signal that the clock will be quite happy with. Generating the divides and switching between them should work pretty well with a fairly small CPLD. Bob On Mar 20, 2011, at 11:51 PM, Flemming Larsen wrote: You could also take the simple approach and divide the 10 MHz signal into a signal with a more convenient period, say 1 mS. If you then take the 1 mS and feed it into a simple flip-flop and set or reset this at any interval that falls closest to 1/60 second, you should have an output with a reasonable close to a 50-50 duty cycle, but at EXACTLY 60 Hz. According to my old-school math, if you decode the 1 mS counts intervals using whole counts, 8, 17, 25, 33, 42, 50, then keep repeating this you should come up with a 60 Hz signal at something that resembles a square wave. If you need something closer to a square wave output, you could start with a 10 KHz signal, divide that signal by any convenient number, then decode the counts 83, 167, 250, etc. Somebody else can do the math, but this should produce a 60 Hz signal with a close enough to a 50-50 duty cycle to keep a motor running at the right speed. -- Flemming Larsen, KB6ADS/OZ6OI, Berkeley, CA, USA Disclaimer: This method has not been tested, and is not endorsed by any rocket scientist. Use with caution, and always be sure to wear proper eye-protection. --- Den søn 20/3/11 skrev WB6BNQ wb6...@cox.net: Fra: WB6BNQ wb6...@cox.net Emne: Re: [time-nuts] 50/60 Hz clocks Til: Discussion of precise time and frequency measurement time-nuts@febo.com Dato: søndag 20. marts 2011 19.40 Paul, Even the low end regular DDS, like the 9831, using a 10 MHz striaght through clock will produce a frequency of 60.0004568696022 Hz or 50.0003807246685 Hz as an output. Simple (ok, perhaps not) amplification after that will get the clock drive needed. Just because some of Analog Devices' more unique products sound neet, they do not always perform as well as the simpler parts. While not easy to find, here is a tool on the A/D site that allows for design simulation of the DDS clock functions. You can even see a tabular table of the spur generation. In the above simulation case they are quite low. http://designtools.analog.com/dtDDSWeb/dtDDSMain.aspx BillWB6BNQ paul swed wrote: Speaking of dds the ad5932 can do this also 10 MC in and 60.20069122 out Change 1 bit and you get 59.6046448 it would be quite easy to bounce back and fourth between the two frequencies like the power company does over time. Thats a small 16 pin chip for a few $. Plus a small pic to make it do what you might want. It could also use any number of other ref clock frequencies1, 5, 15, 20, 50 MC and even ones that aren't sensible to drive the chip. You can take the square wave out or a true sine wave or a triangle if needed. Regards Paul WB8TSL On Sun, Mar 20, 2011 at 7:22 PM, Magnus Danielson mag...@rubidium.dyndns.org wrote: On 03/21/2011 12:10 AM, Hal Murray wrote: If the plan is to drive a mechanical clock, I assume long term stability is more important than phase noise. Many small microcontrollers (I use 8051's from Silabs) have a built-in PLL that can be set to run at 15 MHz from an external 10 MHz reference (applied to the external oscillator input), and use the program space to implement a divider that will give you exactly 60 Hz. That is a one chip solution. The processor will accept the sinewave from the reference oscillator without extra shaping circuit. In case your favorite chip doesn't have a PLL... You can run directly from a 10 MHz clock as long as you can tolerate a bit more phase noise and/or spurs. The software just gets a bit more complicated. Instead of dividing by N, it has to mix delays of N and N+1 in the right ratio. You can also do it with a DDS in a FPGA. The trick is to use a decimal adder rather than a binary adder. 60/1000 in binary isn't a clean fraction so the clock will drift slightly. [This should be simple, but I'm not sure I've got it right.] On the other hand, if you use a 64 bit binary adder, that's 16*2^30*2^30 or 16*1E9*1E9 or 16E18. Call it 1E19. We are clocking at 10E7 Hz, so (worst case) the counter will be off by a full cycle every 1E12 seconds. There are 3E9 seconds per century. So after a century, the clock would be off by 3E-3 cycles or 50 microseconds. On the other hand, it would not be difficult to make a DDS which hit 60/1000 exactly. Reducing it by 20 on each
Re: [time-nuts] 50/60 Hz clocks
Another method would be to make a little drive circuit for the stepper and just divide the 100 nS down to 1 pps. Just observe the drive pulse to the clock and duplicate it. It seems to me it is under a mS and battery Voltage for the amplitude. Greg On 3/21/2011 5:44 AM, Bob Camp wrote: Hi Since you are starting with a 100 ns pulse train as an input, you can bracket any period you need inside a 100 ns window. Put another way, your error will always be less than 100 ns. In this case you would either be off by 33.3 ns or 66.6 ns. A mechanical clock is not going to notice jitter in the sub microsecond region. Put out the periods in a 2:1 ratio and you have a 60 Hz signal that the clock will be quite happy with. Generating the divides and switching between them should work pretty well with a fairly small CPLD. Bob On Mar 20, 2011, at 11:51 PM, Flemming Larsen wrote: You could also take the simple approach and divide the 10 MHz signal into a signal with a more convenient period, say 1 mS. If you then take the 1 mS and feed it into a simple flip-flop and set or reset this at any interval that falls closest to 1/60 second, you should have an output with a reasonable close to a 50-50 duty cycle, but at EXACTLY 60 Hz. According to my old-school math, if you decode the 1 mS counts intervals using whole counts, 8, 17, 25, 33, 42, 50, then keep repeating this you should come up with a 60 Hz signal at something that resembles a square wave. If you need something closer to a square wave output, you could start with a 10 KHz signal, divide that signal by any convenient number, then decode the counts 83, 167, 250, etc. Somebody else can do the math, but this should produce a 60 Hz signal with a close enough to a 50-50 duty cycle to keep a motor running at the right speed. -- Flemming Larsen, KB6ADS/OZ6OI, Berkeley, CA, USA Disclaimer: This method has not been tested, and is not endorsed by any rocket scientist. Use with caution, and always be sure to wear proper eye-protection. --- Den søn 20/3/11 skrev WB6BNQwb6...@cox.net: Fra: WB6BNQwb6...@cox.net Emne: Re: [time-nuts] 50/60 Hz clocks Til: Discussion of precise time and frequency measurementtime-nuts@febo.com Dato: søndag 20. marts 2011 19.40 Paul, Even the low end regular DDS, like the 9831, using a 10 MHz striaght through clock will produce a frequency of 60.0004568696022 Hz or 50.0003807246685 Hz as an output. Simple (ok, perhaps not) amplification after that will get the clock drive needed. Just because some of Analog Devices' more unique products sound neet, they do not always perform as well as the simpler parts. While not easy to find, here is a tool on the A/D site that allows for design simulation of the DDS clock functions. You can even see a tabular table of the spur generation. In the above simulation case they are quite low. http://designtools.analog.com/dtDDSWeb/dtDDSMain.aspx BillWB6BNQ paul swed wrote: Speaking of dds the ad5932 can do this also 10 MC in and 60.20069122 out Change 1 bit and you get 59.6046448 it would be quite easy to bounce back and fourth between the two frequencies like the power company does over time. Thats a small 16 pin chip for a few $. Plus a small pic to make it do what you might want. It could also use any number of other ref clock frequencies1, 5, 15, 20, 50 MC and even ones that aren't sensible to drive the chip. You can take the square wave out or a true sine wave or a triangle if needed. Regards Paul WB8TSL On Sun, Mar 20, 2011 at 7:22 PM, Magnus Danielson mag...@rubidium.dyndns.org wrote: On 03/21/2011 12:10 AM, Hal Murray wrote: If the plan is to drive a mechanical clock, I assume long term stability is more important than phase noise. Many small microcontrollers (I use 8051's from Silabs) have a built-in PLL that can be set to run at 15 MHz from an external 10 MHz reference (applied to the external oscillator input), and use the program space to implement a divider that will give you exactly 60 Hz. That is a one chip solution. The processor will accept the sinewave from the reference oscillator without extra shaping circuit. In case your favorite chip doesn't have a PLL... You can run directly from a 10 MHz clock as long as you can tolerate a bit more phase noise and/or spurs. The software just gets a bit more complicated. Instead of dividing by N, it has to mix delays of N and N+1 in the right ratio. You can also do it with a DDS in a FPGA. The trick is to use a decimal adder rather than a binary adder. 60/1000 in binary isn't a clean fraction so the clock will drift slightly. [This should be simple, but I'm not sure I've got it right.] On the other hand, if you use a 64 bit binary adder, that's 16*2^30*2^30 or 16*1E9*1E9 or 16E18. Call it 1E19. We are clocking at 10E7 Hz, so (worst case) the counter will be off by a full cycle every 1E12 seconds. There are 3E9 seconds per century. So after
Re: [time-nuts] 50/60 Hz clocks
I suspect we have given a ton of approaches and whatever was attempting to be done is lost in the thread someplace. Lots of options these days On Mon, Mar 21, 2011 at 10:00 AM, Greg Broburg semif...@comcast.net wrote: Another method would be to make a little drive circuit for the stepper and just divide the 100 nS down to 1 pps. Just observe the drive pulse to the clock and duplicate it. It seems to me it is under a mS and battery Voltage for the amplitude. Greg On 3/21/2011 5:44 AM, Bob Camp wrote: Hi Since you are starting with a 100 ns pulse train as an input, you can bracket any period you need inside a 100 ns window. Put another way, your error will always be less than 100 ns. In this case you would either be off by 33.3 ns or 66.6 ns. A mechanical clock is not going to notice jitter in the sub microsecond region. Put out the periods in a 2:1 ratio and you have a 60 Hz signal that the clock will be quite happy with. Generating the divides and switching between them should work pretty well with a fairly small CPLD. Bob On Mar 20, 2011, at 11:51 PM, Flemming Larsen wrote: You could also take the simple approach and divide the 10 MHz signal into a signal with a more convenient period, say 1 mS. If you then take the 1 mS and feed it into a simple flip-flop and set or reset this at any interval that falls closest to 1/60 second, you should have an output with a reasonable close to a 50-50 duty cycle, but at EXACTLY 60 Hz. According to my old-school math, if you decode the 1 mS counts intervals using whole counts, 8, 17, 25, 33, 42, 50, then keep repeating this you should come up with a 60 Hz signal at something that resembles a square wave. If you need something closer to a square wave output, you could start with a 10 KHz signal, divide that signal by any convenient number, then decode the counts 83, 167, 250, etc. Somebody else can do the math, but this should produce a 60 Hz signal with a close enough to a 50-50 duty cycle to keep a motor running at the right speed. -- Flemming Larsen, KB6ADS/OZ6OI, Berkeley, CA, USA Disclaimer: This method has not been tested, and is not endorsed by any rocket scientist. Use with caution, and always be sure to wear proper eye-protection. --- Den søn 20/3/11 skrev WB6BNQwb6...@cox.net: Fra: WB6BNQwb6...@cox.net Emne: Re: [time-nuts] 50/60 Hz clocks Til: Discussion of precise time and frequency measurement time-nuts@febo.com Dato: søndag 20. marts 2011 19.40 Paul, Even the low end regular DDS, like the 9831, using a 10 MHz striaght through clock will produce a frequency of 60.0004568696022 Hz or 50.0003807246685 Hz as an output. Simple (ok, perhaps not) amplification after that will get the clock drive needed. Just because some of Analog Devices' more unique products sound neet, they do not always perform as well as the simpler parts. While not easy to find, here is a tool on the A/D site that allows for design simulation of the DDS clock functions. You can even see a tabular table of the spur generation. In the above simulation case they are quite low. http://designtools.analog.com/dtDDSWeb/dtDDSMain.aspx BillWB6BNQ paul swed wrote: Speaking of dds the ad5932 can do this also 10 MC in and 60.20069122 out Change 1 bit and you get 59.6046448 it would be quite easy to bounce back and fourth between the two frequencies like the power company does over time. Thats a small 16 pin chip for a few $. Plus a small pic to make it do what you might want. It could also use any number of other ref clock frequencies1, 5, 15, 20, 50 MC and even ones that aren't sensible to drive the chip. You can take the square wave out or a true sine wave or a triangle if needed. Regards Paul WB8TSL On Sun, Mar 20, 2011 at 7:22 PM, Magnus Danielson mag...@rubidium.dyndns.org wrote: On 03/21/2011 12:10 AM, Hal Murray wrote: If the plan is to drive a mechanical clock, I assume long term stability is more important than phase noise. Many small microcontrollers (I use 8051's from Silabs) have a built-in PLL that can be set to run at 15 MHz from an external 10 MHz reference (applied to the external oscillator input), and use the program space to implement a divider that will give you exactly 60 Hz. That is a one chip solution. The processor will accept the sinewave from the reference oscillator without extra shaping circuit. In case your favorite chip doesn't have a PLL... You can run directly from a 10 MHz clock as long as you can tolerate a bit more phase noise and/or spurs. The software just gets a bit more complicated. Instead of dividing by N, it has to mix delays of N and N+1 in the right ratio. You can also do it with a DDS in a FPGA. The trick is to use a decimal adder rather than a binary adder. 60/1000 in binary isn't a clean fraction so the clock will drift slightly
Re: [time-nuts] 50/60 Hz clocks
If the plan is to drive a mechanical clock, I assume long term stability is more important than phase noise. Many small microcontrollers (I use 8051's from Silabs) have a built-in PLL that can be set to run at 15 MHz from an external 10 MHz reference (applied to the external oscillator input), and use the program space to implement a divider that will give you exactly 60 Hz. That is a one chip solution. The processor will accept the sinewave from the reference oscillator without extra shaping circuit. Didier KO4BB Sent from my BlackBerry Wireless thingy while I do other things... -Original Message- From: Bruce Griffiths bruce.griffi...@xtra.co.nz Sender: time-nuts-boun...@febo.com Date: Sun, 20 Mar 2011 09:30:03 To: Discussion of precise time and frequency measurementtime-nuts@febo.com Reply-To: Discussion of precise time and frequency measurement time-nuts@febo.com Subject: Re: [time-nuts] 50/60 Hz clocks An OTT solution might employ a regenerative divider to generate a 15MHz signal from a 10MHz input followed by a digital divide by 250,000 circuit. One could employ an inexpensive Gilbert cell mixer in the regenerative divider to keep the cost down. Bruce Bob Camp wrote: Hi Most likely the lowest parts count is to divide to a narrow(ish) 20 Hz square wave and then drive a resonated transformer with a pulse. The output won't look pretty, but it should drive a small clock motor just fine. Done properly, there should be very little power involved. If you are going to use anything complicated, just run a gizmo that lets you have a PLL at a factor of 3 times the input. Once that's done - problem solved. Bob On Mar 19, 2011, at 3:01 PM, Michael Poulos wrote: Robert LaJeunesse wrote: Poor man's solution: Use an Arduino to read the Thunderbolt 1PPS and lock a 50Hz (or 60Hz) square wave to the 1PPS. Any resulting jitter can likely be kept in the tens of microsecond range, easily filtered out by the clock mechanics. Filter the square wave a bit and feed it into an audio amplifier (or two) of sufficient power to run the clock. (Possibly a 12V powered bridge amplifier at ~14W would be adequate?) Use some sort of audio output or filament transformer backwards to create the proper line voltage to run the clock. Maybe run the whole thing off a 12V battery with float charger for uninterruptible timing. When using the power transformer backwards keep in mind the impedance output of the amplifier. Audio amplifiers are rated in watts into an 8 ohm (or 4 ohm) load. So, what you want is a power transformer of desired wattage and the low voltage side having a volt and amps rating that would match an 8 ohm load or 4 ohm load. Then, you hook it backwards (i.e. as a step-up transformer) to an audio amp of a rating higher than the transformer then hook the signal to the input and use the volume knob as a throttle. Turn up until desired voltage is reached. Have fun! ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 50/60 Hz clocks
If the plan is to drive a mechanical clock, I assume long term stability is more important than phase noise. Many small microcontrollers (I use 8051's from Silabs) have a built-in PLL that can be set to run at 15 MHz from an external 10 MHz reference (applied to the external oscillator input), and use the program space to implement a divider that will give you exactly 60 Hz. That is a one chip solution. The processor will accept the sinewave from the reference oscillator without extra shaping circuit. In case your favorite chip doesn't have a PLL... You can run directly from a 10 MHz clock as long as you can tolerate a bit more phase noise and/or spurs. The software just gets a bit more complicated. Instead of dividing by N, it has to mix delays of N and N+1 in the right ratio. You can also do it with a DDS in a FPGA. The trick is to use a decimal adder rather than a binary adder. 60/1000 in binary isn't a clean fraction so the clock will drift slightly. [This should be simple, but I'm not sure I've got it right.] On the other hand, if you use a 64 bit binary adder, that's 16*2^30*2^30 or 16*1E9*1E9 or 16E18. Call it 1E19. We are clocking at 10E7 Hz, so (worst case) the counter will be off by a full cycle every 1E12 seconds. There are 3E9 seconds per century. So after a century, the clock would be off by 3E-3 cycles or 50 microseconds. -- These are my opinions, not necessarily my employer's. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 50/60 Hz clocks
On 03/21/2011 12:10 AM, Hal Murray wrote: If the plan is to drive a mechanical clock, I assume long term stability is more important than phase noise. Many small microcontrollers (I use 8051's from Silabs) have a built-in PLL that can be set to run at 15 MHz from an external 10 MHz reference (applied to the external oscillator input), and use the program space to implement a divider that will give you exactly 60 Hz. That is a one chip solution. The processor will accept the sinewave from the reference oscillator without extra shaping circuit. In case your favorite chip doesn't have a PLL... You can run directly from a 10 MHz clock as long as you can tolerate a bit more phase noise and/or spurs. The software just gets a bit more complicated. Instead of dividing by N, it has to mix delays of N and N+1 in the right ratio. You can also do it with a DDS in a FPGA. The trick is to use a decimal adder rather than a binary adder. 60/1000 in binary isn't a clean fraction so the clock will drift slightly. [This should be simple, but I'm not sure I've got it right.] On the other hand, if you use a 64 bit binary adder, that's 16*2^30*2^30 or 16*1E9*1E9 or 16E18. Call it 1E19. We are clocking at 10E7 Hz, so (worst case) the counter will be off by a full cycle every 1E12 seconds. There are 3E9 seconds per century. So after a century, the clock would be off by 3E-3 cycles or 50 microseconds. On the other hand, it would not be difficult to make a DDS which hit 60/1000 exactly. Reducing it by 20 on each side you get 3/50 so a 19 bit accumulator (mod 50) incrementing with 3 on every 100 ns period would do it. A LUT for sine would be possible. Playing a few tricks with the LUT table (realizing that the LUT would be walked through three times with three different start-alignments) converts it into a LUT of the same size and a increment by one or decrement by one counter modulus 50. A decrement by one counter allows wrap-around loading with 49 easy. CPLD or CMOS/TTL implementations would be trivial for the counter. The LUT will be large... Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 50/60 Hz clocks
Speaking of dds the ad5932 can do this also 10 MC in and 60.20069122 out Change 1 bit and you get 59.6046448 it would be quite easy to bounce back and fourth between the two frequencies like the power company does over time. Thats a small 16 pin chip for a few $. Plus a small pic to make it do what you might want. It could also use any number of other ref clock frequencies1, 5, 15, 20, 50 MC and even ones that aren't sensible to drive the chip. You can take the square wave out or a true sine wave or a triangle if needed. Regards Paul WB8TSL On Sun, Mar 20, 2011 at 7:22 PM, Magnus Danielson mag...@rubidium.dyndns.org wrote: On 03/21/2011 12:10 AM, Hal Murray wrote: If the plan is to drive a mechanical clock, I assume long term stability is more important than phase noise. Many small microcontrollers (I use 8051's from Silabs) have a built-in PLL that can be set to run at 15 MHz from an external 10 MHz reference (applied to the external oscillator input), and use the program space to implement a divider that will give you exactly 60 Hz. That is a one chip solution. The processor will accept the sinewave from the reference oscillator without extra shaping circuit. In case your favorite chip doesn't have a PLL... You can run directly from a 10 MHz clock as long as you can tolerate a bit more phase noise and/or spurs. The software just gets a bit more complicated. Instead of dividing by N, it has to mix delays of N and N+1 in the right ratio. You can also do it with a DDS in a FPGA. The trick is to use a decimal adder rather than a binary adder. 60/1000 in binary isn't a clean fraction so the clock will drift slightly. [This should be simple, but I'm not sure I've got it right.] On the other hand, if you use a 64 bit binary adder, that's 16*2^30*2^30 or 16*1E9*1E9 or 16E18. Call it 1E19. We are clocking at 10E7 Hz, so (worst case) the counter will be off by a full cycle every 1E12 seconds. There are 3E9 seconds per century. So after a century, the clock would be off by 3E-3 cycles or 50 microseconds. On the other hand, it would not be difficult to make a DDS which hit 60/1000 exactly. Reducing it by 20 on each side you get 3/50 so a 19 bit accumulator (mod 50) incrementing with 3 on every 100 ns period would do it. A LUT for sine would be possible. Playing a few tricks with the LUT table (realizing that the LUT would be walked through three times with three different start-alignments) converts it into a LUT of the same size and a increment by one or decrement by one counter modulus 50. A decrement by one counter allows wrap-around loading with 49 easy. CPLD or CMOS/TTL implementations would be trivial for the counter. The LUT will be large... Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 50/60 Hz clocks
Paul, Even the low end regular DDS, like the 9831, using a 10 MHz striaght through clock will produce a frequency of 60.0004568696022 Hz or 50.0003807246685 Hz as an output. Simple (ok, perhaps not) amplification after that will get the clock drive needed. Just because some of Analog Devices' more unique products sound neet, they do not always perform as well as the simpler parts. While not easy to find, here is a tool on the A/D site that allows for design simulation of the DDS clock functions. You can even see a tabular table of the spur generation. In the above simulation case they are quite low. http://designtools.analog.com/dtDDSWeb/dtDDSMain.aspx BillWB6BNQ paul swed wrote: Speaking of dds the ad5932 can do this also 10 MC in and 60.20069122 out Change 1 bit and you get 59.6046448 it would be quite easy to bounce back and fourth between the two frequencies like the power company does over time. Thats a small 16 pin chip for a few $. Plus a small pic to make it do what you might want. It could also use any number of other ref clock frequencies1, 5, 15, 20, 50 MC and even ones that aren't sensible to drive the chip. You can take the square wave out or a true sine wave or a triangle if needed. Regards Paul WB8TSL On Sun, Mar 20, 2011 at 7:22 PM, Magnus Danielson mag...@rubidium.dyndns.org wrote: On 03/21/2011 12:10 AM, Hal Murray wrote: If the plan is to drive a mechanical clock, I assume long term stability is more important than phase noise. Many small microcontrollers (I use 8051's from Silabs) have a built-in PLL that can be set to run at 15 MHz from an external 10 MHz reference (applied to the external oscillator input), and use the program space to implement a divider that will give you exactly 60 Hz. That is a one chip solution. The processor will accept the sinewave from the reference oscillator without extra shaping circuit. In case your favorite chip doesn't have a PLL... You can run directly from a 10 MHz clock as long as you can tolerate a bit more phase noise and/or spurs. The software just gets a bit more complicated. Instead of dividing by N, it has to mix delays of N and N+1 in the right ratio. You can also do it with a DDS in a FPGA. The trick is to use a decimal adder rather than a binary adder. 60/1000 in binary isn't a clean fraction so the clock will drift slightly. [This should be simple, but I'm not sure I've got it right.] On the other hand, if you use a 64 bit binary adder, that's 16*2^30*2^30 or 16*1E9*1E9 or 16E18. Call it 1E19. We are clocking at 10E7 Hz, so (worst case) the counter will be off by a full cycle every 1E12 seconds. There are 3E9 seconds per century. So after a century, the clock would be off by 3E-3 cycles or 50 microseconds. On the other hand, it would not be difficult to make a DDS which hit 60/1000 exactly. Reducing it by 20 on each side you get 3/50 so a 19 bit accumulator (mod 50) incrementing with 3 on every 100 ns period would do it. A LUT for sine would be possible. Playing a few tricks with the LUT table (realizing that the LUT would be walked through three times with three different start-alignments) converts it into a LUT of the same size and a increment by one or decrement by one counter modulus 50. A decrement by one counter allows wrap-around loading with 49 easy. CPLD or CMOS/TTL implementations would be trivial for the counter. The LUT will be large... Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 50/60 Hz clocks
Thanks Bill parts is parts. Do like the ad5329 and its working well. Have 5 of them now. About the hardest thing is soldering the devils to a breakout board and not bridging pins. But I am sure other parts will work as fine. Indeed those are some very fine outputs. Regards Paul. On Sun, Mar 20, 2011 at 10:40 PM, WB6BNQ wb6...@cox.net wrote: Paul, Even the low end regular DDS, like the 9831, using a 10 MHz striaght through clock will produce a frequency of 60.0004568696022 Hz or 50.0003807246685 Hz as an output. Simple (ok, perhaps not) amplification after that will get the clock drive needed. Just because some of Analog Devices' more unique products sound neet, they do not always perform as well as the simpler parts. While not easy to find, here is a tool on the A/D site that allows for design simulation of the DDS clock functions. You can even see a tabular table of the spur generation. In the above simulation case they are quite low. http://designtools.analog.com/dtDDSWeb/dtDDSMain.aspx BillWB6BNQ paul swed wrote: Speaking of dds the ad5932 can do this also 10 MC in and 60.20069122 out Change 1 bit and you get 59.6046448 it would be quite easy to bounce back and fourth between the two frequencies like the power company does over time. Thats a small 16 pin chip for a few $. Plus a small pic to make it do what you might want. It could also use any number of other ref clock frequencies1, 5, 15, 20, 50 MC and even ones that aren't sensible to drive the chip. You can take the square wave out or a true sine wave or a triangle if needed. Regards Paul WB8TSL On Sun, Mar 20, 2011 at 7:22 PM, Magnus Danielson mag...@rubidium.dyndns.org wrote: On 03/21/2011 12:10 AM, Hal Murray wrote: If the plan is to drive a mechanical clock, I assume long term stability is more important than phase noise. Many small microcontrollers (I use 8051's from Silabs) have a built-in PLL that can be set to run at 15 MHz from an external 10 MHz reference (applied to the external oscillator input), and use the program space to implement a divider that will give you exactly 60 Hz. That is a one chip solution. The processor will accept the sinewave from the reference oscillator without extra shaping circuit. In case your favorite chip doesn't have a PLL... You can run directly from a 10 MHz clock as long as you can tolerate a bit more phase noise and/or spurs. The software just gets a bit more complicated. Instead of dividing by N, it has to mix delays of N and N+1 in the right ratio. You can also do it with a DDS in a FPGA. The trick is to use a decimal adder rather than a binary adder. 60/1000 in binary isn't a clean fraction so the clock will drift slightly. [This should be simple, but I'm not sure I've got it right.] On the other hand, if you use a 64 bit binary adder, that's 16*2^30*2^30 or 16*1E9*1E9 or 16E18. Call it 1E19. We are clocking at 10E7 Hz, so (worst case) the counter will be off by a full cycle every 1E12 seconds. There are 3E9 seconds per century. So after a century, the clock would be off by 3E-3 cycles or 50 microseconds. On the other hand, it would not be difficult to make a DDS which hit 60/1000 exactly. Reducing it by 20 on each side you get 3/50 so a 19 bit accumulator (mod 50) incrementing with 3 on every 100 ns period would do it. A LUT for sine would be possible. Playing a few tricks with the LUT table (realizing that the LUT would be walked through three times with three different start-alignments) converts it into a LUT of the same size and a increment by one or decrement by one counter modulus 50. A decrement by one counter allows wrap-around loading with 49 easy. CPLD or CMOS/TTL implementations would be trivial for the counter. The LUT will be large... Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 50/60 Hz clocks
Like the tool. Thats sure makes things easy. I see the 9831 is about $11 which is a great price. However the many pin tsop even with an adapter will be a sun of gun to solder. I will be on the hunt at the sping fleas for some smaller irons. Regards Paul. On Sun, Mar 20, 2011 at 10:47 PM, paul swed paulsw...@gmail.com wrote: Thanks Bill parts is parts. Do like the ad5329 and its working well. Have 5 of them now. About the hardest thing is soldering the devils to a breakout board and not bridging pins. But I am sure other parts will work as fine. Indeed those are some very fine outputs. Regards Paul. On Sun, Mar 20, 2011 at 10:40 PM, WB6BNQ wb6...@cox.net wrote: Paul, Even the low end regular DDS, like the 9831, using a 10 MHz striaght through clock will produce a frequency of 60.0004568696022 Hz or 50.0003807246685 Hz as an output. Simple (ok, perhaps not) amplification after that will get the clock drive needed. Just because some of Analog Devices' more unique products sound neet, they do not always perform as well as the simpler parts. While not easy to find, here is a tool on the A/D site that allows for design simulation of the DDS clock functions. You can even see a tabular table of the spur generation. In the above simulation case they are quite low. http://designtools.analog.com/dtDDSWeb/dtDDSMain.aspx BillWB6BNQ paul swed wrote: Speaking of dds the ad5932 can do this also 10 MC in and 60.20069122 out Change 1 bit and you get 59.6046448 it would be quite easy to bounce back and fourth between the two frequencies like the power company does over time. Thats a small 16 pin chip for a few $. Plus a small pic to make it do what you might want. It could also use any number of other ref clock frequencies1, 5, 15, 20, 50 MC and even ones that aren't sensible to drive the chip. You can take the square wave out or a true sine wave or a triangle if needed. Regards Paul WB8TSL On Sun, Mar 20, 2011 at 7:22 PM, Magnus Danielson mag...@rubidium.dyndns.org wrote: On 03/21/2011 12:10 AM, Hal Murray wrote: If the plan is to drive a mechanical clock, I assume long term stability is more important than phase noise. Many small microcontrollers (I use 8051's from Silabs) have a built-in PLL that can be set to run at 15 MHz from an external 10 MHz reference (applied to the external oscillator input), and use the program space to implement a divider that will give you exactly 60 Hz. That is a one chip solution. The processor will accept the sinewave from the reference oscillator without extra shaping circuit. In case your favorite chip doesn't have a PLL... You can run directly from a 10 MHz clock as long as you can tolerate a bit more phase noise and/or spurs. The software just gets a bit more complicated. Instead of dividing by N, it has to mix delays of N and N+1 in the right ratio. You can also do it with a DDS in a FPGA. The trick is to use a decimal adder rather than a binary adder. 60/1000 in binary isn't a clean fraction so the clock will drift slightly. [This should be simple, but I'm not sure I've got it right.] On the other hand, if you use a 64 bit binary adder, that's 16*2^30*2^30 or 16*1E9*1E9 or 16E18. Call it 1E19. We are clocking at 10E7 Hz, so (worst case) the counter will be off by a full cycle every 1E12 seconds. There are 3E9 seconds per century. So after a century, the clock would be off by 3E-3 cycles or 50 microseconds. On the other hand, it would not be difficult to make a DDS which hit 60/1000 exactly. Reducing it by 20 on each side you get 3/50 so a 19 bit accumulator (mod 50) incrementing with 3 on every 100 ns period would do it. A LUT for sine would be possible. Playing a few tricks with the LUT table (realizing that the LUT would be walked through three times with three different start-alignments) converts it into a LUT of the same size and a increment by one or decrement by one counter modulus 50. A decrement by one counter allows wrap-around loading with 49 easy. CPLD or CMOS/TTL implementations would be trivial for the counter. The LUT will be large... Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and
Re: [time-nuts] 50/60 Hz clocks
You could also take the simple approach and divide the 10 MHz signal into a signal with a more convenient period, say 1 mS. If you then take the 1 mS and feed it into a simple flip-flop and set or reset this at any interval that falls closest to 1/60 second, you should have an output with a reasonable close to a 50-50 duty cycle, but at EXACTLY 60 Hz. According to my old-school math, if you decode the 1 mS counts intervals using whole counts, 8, 17, 25, 33, 42, 50, then keep repeating this you should come up with a 60 Hz signal at something that resembles a square wave. If you need something closer to a square wave output, you could start with a 10 KHz signal, divide that signal by any convenient number, then decode the counts 83, 167, 250, etc. Somebody else can do the math, but this should produce a 60 Hz signal with a close enough to a 50-50 duty cycle to keep a motor running at the right speed. -- Flemming Larsen, KB6ADS/OZ6OI, Berkeley, CA, USA Disclaimer: This method has not been tested, and is not endorsed by any rocket scientist. Use with caution, and always be sure to wear proper eye-protection. --- Den søn 20/3/11 skrev WB6BNQ wb6...@cox.net: Fra: WB6BNQ wb6...@cox.net Emne: Re: [time-nuts] 50/60 Hz clocks Til: Discussion of precise time and frequency measurement time-nuts@febo.com Dato: søndag 20. marts 2011 19.40 Paul, Even the low end regular DDS, like the 9831, using a 10 MHz striaght through clock will produce a frequency of 60.0004568696022 Hz or 50.0003807246685 Hz as an output. Simple (ok, perhaps not) amplification after that will get the clock drive needed. Just because some of Analog Devices' more unique products sound neet, they do not always perform as well as the simpler parts. While not easy to find, here is a tool on the A/D site that allows for design simulation of the DDS clock functions. You can even see a tabular table of the spur generation. In the above simulation case they are quite low. http://designtools.analog.com/dtDDSWeb/dtDDSMain.aspx BillWB6BNQ paul swed wrote: Speaking of dds the ad5932 can do this also 10 MC in and 60.20069122 out Change 1 bit and you get 59.6046448 it would be quite easy to bounce back and fourth between the two frequencies like the power company does over time. Thats a small 16 pin chip for a few $. Plus a small pic to make it do what you might want. It could also use any number of other ref clock frequencies1, 5, 15, 20, 50 MC and even ones that aren't sensible to drive the chip. You can take the square wave out or a true sine wave or a triangle if needed. Regards Paul WB8TSL On Sun, Mar 20, 2011 at 7:22 PM, Magnus Danielson mag...@rubidium.dyndns.org wrote: On 03/21/2011 12:10 AM, Hal Murray wrote: If the plan is to drive a mechanical clock, I assume long term stability is more important than phase noise. Many small microcontrollers (I use 8051's from Silabs) have a built-in PLL that can be set to run at 15 MHz from an external 10 MHz reference (applied to the external oscillator input), and use the program space to implement a divider that will give you exactly 60 Hz. That is a one chip solution. The processor will accept the sinewave from the reference oscillator without extra shaping circuit. In case your favorite chip doesn't have a PLL... You can run directly from a 10 MHz clock as long as you can tolerate a bit more phase noise and/or spurs. The software just gets a bit more complicated. Instead of dividing by N, it has to mix delays of N and N+1 in the right ratio. You can also do it with a DDS in a FPGA. The trick is to use a decimal adder rather than a binary adder. 60/1000 in binary isn't a clean fraction so the clock will drift slightly. [This should be simple, but I'm not sure I've got it right.] On the other hand, if you use a 64 bit binary adder, that's 16*2^30*2^30 or 16*1E9*1E9 or 16E18. Call it 1E19. We are clocking at 10E7 Hz, so (worst case) the counter will be off by a full cycle every 1E12 seconds. There are 3E9 seconds per century. So after a century, the clock would be off by 3E-3 cycles or 50 microseconds. On the other hand, it would not be difficult to make a DDS which hit 60/1000 exactly. Reducing it by 20 on each side you get 3/50 so a 19 bit accumulator (mod 50) incrementing with 3 on every 100 ns period would do it. A LUT for sine would be possible. Playing a few tricks with the LUT table (realizing that the LUT would be walked through three times with three different start-alignments) converts it into a LUT of the same size and a increment by one or decrement by one counter modulus 50. A decrement by one counter allows wrap-around loading with 49 easy. CPLD or CMOS/TTL implementations would
Re: [time-nuts] 50/60 Hz clocks
Cezary Rozluski wrote: Well – it is nice solution presented, but I would like ask you what would be from time-nuts perspective simple (the simplest ?) solution to drive such 50/60 Hz clocks without to much overweighed stuff (and of course without modifying the clock itself addig e.g step motor etc, etc) We had this discussion a while back. Try the archives and search on Got 60HZ?. I started that discussion with having come up with a dithering strategy to make a nearly exact 60HZ squarewave out of 10,000HZ from a frequency dividing chip. From 10,000HZ, making 50HZ would be easy if you don't mind a squarewave. You rig an Arduino to the frequency dividing chip and program to taste. The hardest part is to make the 1/2 volt 10MHZ sinewave into the 10MHZ TTL-compliant squarewave! ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 50/60 Hz clocks
Robert LaJeunesse wrote: Poor man's solution: Use an Arduino to read the Thunderbolt 1PPS and lock a 50Hz (or 60Hz) square wave to the 1PPS. Any resulting jitter can likely be kept in the tens of microsecond range, easily filtered out by the clock mechanics. Filter the square wave a bit and feed it into an audio amplifier (or two) of sufficient power to run the clock. (Possibly a 12V powered bridge amplifier at ~14W would be adequate?) Use some sort of audio output or filament transformer backwards to create the proper line voltage to run the clock. Maybe run the whole thing off a 12V battery with float charger for uninterruptible timing. When using the power transformer backwards keep in mind the impedance output of the amplifier. Audio amplifiers are rated in watts into an 8 ohm (or 4 ohm) load. So, what you want is a power transformer of desired wattage and the low voltage side having a volt and amps rating that would match an 8 ohm load or 4 ohm load. Then, you hook it backwards (i.e. as a step-up transformer) to an audio amp of a rating higher than the transformer then hook the signal to the input and use the volume knob as a throttle. Turn up until desired voltage is reached. Have fun! ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 50/60 Hz clocks
Hi Most likely the lowest parts count is to divide to a narrow(ish) 20 Hz square wave and then drive a resonated transformer with a pulse. The output won't look pretty, but it should drive a small clock motor just fine. Done properly, there should be very little power involved. If you are going to use anything complicated, just run a gizmo that lets you have a PLL at a factor of 3 times the input. Once that's done - problem solved. Bob On Mar 19, 2011, at 3:01 PM, Michael Poulos wrote: Robert LaJeunesse wrote: Poor man's solution: Use an Arduino to read the Thunderbolt 1PPS and lock a 50Hz (or 60Hz) square wave to the 1PPS. Any resulting jitter can likely be kept in the tens of microsecond range, easily filtered out by the clock mechanics. Filter the square wave a bit and feed it into an audio amplifier (or two) of sufficient power to run the clock. (Possibly a 12V powered bridge amplifier at ~14W would be adequate?) Use some sort of audio output or filament transformer backwards to create the proper line voltage to run the clock. Maybe run the whole thing off a 12V battery with float charger for uninterruptible timing. When using the power transformer backwards keep in mind the impedance output of the amplifier. Audio amplifiers are rated in watts into an 8 ohm (or 4 ohm) load. So, what you want is a power transformer of desired wattage and the low voltage side having a volt and amps rating that would match an 8 ohm load or 4 ohm load. Then, you hook it backwards (i.e. as a step-up transformer) to an audio amp of a rating higher than the transformer then hook the signal to the input and use the volume knob as a throttle. Turn up until desired voltage is reached. Have fun! ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 50/60 Hz clocks
An OTT solution might employ a regenerative divider to generate a 15MHz signal from a 10MHz input followed by a digital divide by 250,000 circuit. One could employ an inexpensive Gilbert cell mixer in the regenerative divider to keep the cost down. Bruce Bob Camp wrote: Hi Most likely the lowest parts count is to divide to a narrow(ish) 20 Hz square wave and then drive a resonated transformer with a pulse. The output won't look pretty, but it should drive a small clock motor just fine. Done properly, there should be very little power involved. If you are going to use anything complicated, just run a gizmo that lets you have a PLL at a factor of 3 times the input. Once that's done - problem solved. Bob On Mar 19, 2011, at 3:01 PM, Michael Poulos wrote: Robert LaJeunesse wrote: Poor man's solution: Use an Arduino to read the Thunderbolt 1PPS and lock a 50Hz (or 60Hz) square wave to the 1PPS. Any resulting jitter can likely be kept in the tens of microsecond range, easily filtered out by the clock mechanics. Filter the square wave a bit and feed it into an audio amplifier (or two) of sufficient power to run the clock. (Possibly a 12V powered bridge amplifier at ~14W would be adequate?) Use some sort of audio output or filament transformer backwards to create the proper line voltage to run the clock. Maybe run the whole thing off a 12V battery with float charger for uninterruptible timing. When using the power transformer backwards keep in mind the impedance output of the amplifier. Audio amplifiers are rated in watts into an 8 ohm (or 4 ohm) load. So, what you want is a power transformer of desired wattage and the low voltage side having a volt and amps rating that would match an 8 ohm load or 4 ohm load. Then, you hook it backwards (i.e. as a step-up transformer) to an audio amp of a rating higher than the transformer then hook the signal to the input and use the volume knob as a throttle. Turn up until desired voltage is reached. Have fun! ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 50/60 Hz clocks
Hi Lucent simply divided the 10 MHz by two and then tripled that in their standard base station gear. Lots of ways to do it. None of them very hard at all. Bob On Mar 19, 2011, at 4:30 PM, Bruce Griffiths wrote: An OTT solution might employ a regenerative divider to generate a 15MHz signal from a 10MHz input followed by a digital divide by 250,000 circuit. One could employ an inexpensive Gilbert cell mixer in the regenerative divider to keep the cost down. Bruce Bob Camp wrote: Hi Most likely the lowest parts count is to divide to a narrow(ish) 20 Hz square wave and then drive a resonated transformer with a pulse. The output won't look pretty, but it should drive a small clock motor just fine. Done properly, there should be very little power involved. If you are going to use anything complicated, just run a gizmo that lets you have a PLL at a factor of 3 times the input. Once that's done - problem solved. Bob On Mar 19, 2011, at 3:01 PM, Michael Poulos wrote: Robert LaJeunesse wrote: Poor man's solution: Use an Arduino to read the Thunderbolt 1PPS and lock a 50Hz (or 60Hz) square wave to the 1PPS. Any resulting jitter can likely be kept in the tens of microsecond range, easily filtered out by the clock mechanics. Filter the square wave a bit and feed it into an audio amplifier (or two) of sufficient power to run the clock. (Possibly a 12V powered bridge amplifier at ~14W would be adequate?) Use some sort of audio output or filament transformer backwards to create the proper line voltage to run the clock. Maybe run the whole thing off a 12V battery with float charger for uninterruptible timing. When using the power transformer backwards keep in mind the impedance output of the amplifier. Audio amplifiers are rated in watts into an 8 ohm (or 4 ohm) load. So, what you want is a power transformer of desired wattage and the low voltage side having a volt and amps rating that would match an 8 ohm load or 4 ohm load. Then, you hook it backwards (i.e. as a step-up transformer) to an audio amp of a rating higher than the transformer then hook the signal to the input and use the volume knob as a throttle. Turn up until desired voltage is reached. Have fun! ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 50/60 Hz clocks
The exclusive solution feasible is: http://shop-emea.u-blox.com/abashop?s=274p=productdetailsku=553 Nice, as you can program it for PPS at 10KHz or some other frequency. More cheap, not so spectacular: Cirrus CS2000 PLL Locks on 50Hz or more - Henry -- ehydra.dyndns.info Cezary Rozluski schrieb: Let us suppose I have Thunderbolt (I really have one) as a time/frequency source, but any other time-nuts recognized frequency source should by sufficient for the fun to drive old 50/60Hz stuff with the highest precision available (and for fun, comparable to www.leapsecond.com solution, modulo cesium/hydrogen clock). It would be very nice to see correction for leap seconds as well :-) :-) Regards, Cezary ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 50/60 Hz clocks
At 04:54 PM 3/10/2011, Cezary Rozluski wrote... Let us suppose I have Thunderbolt (I really have one) as a time/frequency source, but any other time-nuts recognized frequency source should by sufficient for the fun to drive old 50/60Hz stuff with the highest precision available (and for fun, comparable to www.leapsecond.com solution, modulo cesium/hydrogen clock). It would be very nice to see correction for leap seconds as well :-) :-) Perhaps a cheap DC/AC inverter (like they make to run AC electronics in cars or recreational vehicles). I suspect most are crystal controlled for the frequency. Divide down your 10 MHz to match the crystal, and inject your more precise frequency. 50 Hz is likely to be easier than 60 Hz, because it is an integer division from 10 MHz. Then again, even if they're crystal controlled, they may cheat and just be close enough. i.e. 32768 Hz crystal, /656 for ~49.95 Hz, /546 for ~60.01 Hz. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
