Hi Prafulla,
Is there any chance for theses patches to be reviewed in time for next release ?
Can you get it reviewed by anyone else ?
Enjoy,
On 15/09/2014 06:36, drEagle wrote:
Hi Preafulla,
Any news about these patches ?
Regards,
On 09/09/2014 08:59, Prafulla Wadaskar wrote:
Hi
The mentioned binutils port got removed while the patch was
pending. As Ian pointed out there is another port providing
the binutils for arm now. Update the instructions accordingly.
Cc: i...@freebsd.org
Cc: Tom Rini tr...@ti.com
Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl
---
On 09/21/14 02:05, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
We should not hardcode CONFIG_NETMASK in the config file.
That is correct no doubts.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
Cc'd Nikita,
Acked-by: Igor Grinberg
From: Pavel Machek pa...@denx.de
Remove this symbol from configs, since it's unused.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom
Fix remaining cache alignment issues in the DWC Ethernet driver.
Please note that the cache handling in the driver is making the
code hideous and thus the next patch cleans that up. In order to
make this change reviewable though, the cleanup is split from it.
Signed-off-by: Marek Vasut
From: Pavel Machek pa...@denx.de
Add base addresses for all subsystems as documented in the
Cyclone V HPS documentation.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud
This entire series is the second stab at making SoCFPGA usable with
mainline U-Boot again. There are much fewer bits missing than in the
last series, more cleanup happened and bugs were fixed. This allows
me to use mainline U-Boot on my SoCFPGA systems.
The big missing part is the SPL generation,
From: Charles Manning cdhmann...@gmail.com
Like many platforms, the Altera socfpga platform requires that the
preloader be signed in a certain way or the built-in boot ROM will
not boot the code.
This change automatically creates an appropriately signed preloader
from an SPL image.
The signed
From: Pavel Machek pa...@denx.de
Old saying says that more than three exclamation marks in a row are
sign of mental disease. Cleanup micrel.c.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen
From: Pavel Machek pa...@denx.de
The dw_mmc driver was responding to errors with debug(). Change that
to prinf()/puts() respectively so that any errors are immediately
obvious. Also adjust english in comments.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc:
Add a few new variables to make the cache handling less cryptic.
Add a variable for DMA and DATA descriptor start and end, so the
correctness of the code is easier to inspect.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc:
Clean up the system manager register definition and add the missing
register definitions in place.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang
The DMA descriptors used by the DW MMC block must be aligned to cacheline
size, otherwise we are unable to properly flush/inval cache over them and
we get data corruption.
The reason I chose this approach of expanding the structure is because
the driver allocates the descriptors in bulk. This
Sort the list of functional block addresses and fix indentation.
No functional change.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk
From: Pavel Machek pa...@denx.de
This adds watchdog disable. It is neccessary for running Linux kernel.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud
The bit definitions for clock manager are complete chaos. Implement
some basic logical order into them.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc:
From: Pavel Machek pa...@denx.de
Add the entire bulk of code to read out clock configuration from the SoCFPGA
CPU registers. This is important for MMC, QSPI and UART drivers as otherwise
they cannot determine the frequency of their upstream clock.
Signed-off-by: Pavel Machek pa...@denx.de
Add some stub defines, which are used by the clock code, but are
missing from the auto-generated header file for the SoCFPGA family.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc:
The inlining is done by GCC when needed, there is no need to do it
explicitly. Furthermore, the inline keyword does not force-inline
the code, but is only a hint for the compiler. Scrub this hint.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen
Pull out functions to read frequency of Main clock VCO and
PLL clock VCO as the code is duplicated multiple times.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini
Add the missing pieces from the reference clock code from Altera. This
puts the code on par with the Altera U-Boot fork for all but the SDRAM
self-refresh bits, which are not part of this patch.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen
Clean up the clock code definitions so they are aligned with mainline
standards. There are no functional changes in this patch.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom
From: Pavel Machek pa...@denx.de
Make the SoCFPGA MMC stub pick clock via the clock manager
frequency accessors instead of hard-coding the frequency.
Also fix calloc() misuse.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
The timer reload value is a property of the timer hardware and there
is no reason for this to be configurable. Place this into the timer
driver just like on the other hardware.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc:
Add functions to reset the EMAC ethernet blocks. We cannot handle
two EMAC ethernet blocks yet, therefore the ifdefs. Once there is
hardware using both EMAC blocks, this ifdef will have to go.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen
From: Pavel Machek pa...@denx.de
Add function to initialize the EMAC blocks upon board startup.
The preprocessor guards against building on SoCFPGA-VT and against
SPL build are not needed as those are handled implicitly via both
SPL framework and the socfpga_cyclone5.h config file, which will
not
From: Pavel Machek pa...@denx.de
Cosmetic change to the print_cpuinfo() function output. Align the
output with the rest of initial output produced by U-Boot.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen
From: Pavel Machek pa...@denx.de
Add CPU function to register and initialize the dw_mmc SD controller.
This allows us to use the HPS SDMMC block.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen
From: Pavel Machek pa...@denx.de
The bi_boot_params must point to offset 0x100 in DRAM. Make it so.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud
Cosmetic change to the checkboard() function output. Align the
output with the rest of initial output produced by U-Boot.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini
On Saturday, September 20, 2014 at 04:54:33 PM, Hans de Goede wrote:
Hi Marek,
Here is the second set of USB patches / fixes I've been working on,
currently u-boot does really bad things (tm) when doing usb reset
while using an usb keyboard. This set fixes this.
Given that these fix
On Saturday, September 20, 2014 at 05:03:51 PM, Hans de Goede wrote:
Hi Marek,
And last 2 misc. fixes for USB for next. The first patch is self
explanatory, the second patch is a result of me looking into why u-boot's
usb scanning is so slww, not that it really helps there, but it is
On Saturday, September 20, 2014 at 04:51:22 PM, Hans de Goede wrote:
For full / low speed devices we need to get the devnum and portnr of the
tt, so of the first upstream usb-2 hub, not of the parent device (which
may be a usb-1 hub).
Signed-off-by: Hans de Goede hdego...@redhat.com
Applied
On Saturday, September 20, 2014 at 05:01:05 PM, Hans de Goede wrote:
Hi Marek,
This time a patch-set for next :)
Currently one can choose between 2 poll methods for usb keyboards, both of
which are suboptimal. One option is to use control messages to get reports,
which some devices (e.g.
Clean up the printf() statements and get rid of the PRINTF()
macro by replacing it with debug_cond().
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc:
Boldly go, where no programmer has gone before and just clean up
the indentation mayhem. No functional change.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Get rid of the line-over-80 problems and zap the typedef that
went alongside those enums.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk
Further improve the indentation in the rest of the file, where
the indentation is initially a bit less brutal. There is no
functional change in this patch.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud
Make the function return either 0 or -EINVAL, that is, normal
expected error codes and success codes instead of true/false
nonsense.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc:
Add function to enable and disable FPGA bridges. This code is used
by the FPGA manager to disable the bridges before programming the
FPGA and will later be also used by the initialization code for the
chip to put the chip into well defined state during startup.
Signed-off-by: Marek Vasut
Add missing system manager bits from Altera U-Boot to make the code
comparable. These are the bits which depend on the FPGA manager.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc:
Add configuration for the write-allocate mode of L1 D-Cache on ARM.
This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA .
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc:
Add a table of FPGA family with matching functions associated with
it and make all the code just look up the family in that table and
call the associated function instead of the horrible switch voodoo
which was duplicated all over the place.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang
From: Pavel Machek pa...@denx.de
Add code necessary to program the FPGA part of SoCFPGA from U-Boot
with an RBF blob. This patch also integrates the code into the
FPGA driver framework in U-Boot so it can be used via the 'fpga'
command.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by:
Move the function to the top of the file to avoid forward declaration.
No functional change.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk
The code is now fixed to the point where we can safely enable
the L1 data cache. Enable the D-Cache and set it as write-alloc.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini
Enable the PL310 L2 cache controller support for the SoCFPGA.
With the cache related issues resolved, this is safe to be done.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini
The Cortex-A9 has 32-byte long L1 cachelines. Define this value.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek
Add the Snoop Control Unit register definition file.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek
Add register definition for the NIC-301 used on SoCFPGA.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek
From: Pavel Machek pa...@denx.de
Add code which configures the AMBA NIC-301 and the SCU on the SoCFPGA .
The code sets the access permissions for the CPU to the AMBA slaves such
that the CPU can access them in both secure and non-secure mode.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin
Configure the PL310 address filter to make sure DRAM is mapped to 0x0.
This code also configures the remap register of NIC-301 and sets the
required 'mpuzero' bit.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud
From: Chin Liang See cl...@altera.com
Enable the DesignWare MMC controller driver support
for SOCFPGA Cyclone5 dev kit
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Pavel Machek pa...@denx.de
Cc: Marek Vasut ma...@denx.de
Cc: Tom Rini tr...@ti.com
Cc:
From: Pavel Machek pa...@denx.de
Add command to enable and disable the bridges between HPS and FPGA.
This patch does have a checkpatch issue with the assembler portion,
checkpatch correctly complains that there should be no whitespace
before quoted newline. I do not agree that fixing this
From: Chin Liang See cl...@altera.com
Enable the SDMMC boot as default boot for SOCFPGA U-Boot dev kit.
Enable the bootz command as zImage is used instead uImage.
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Pavel Machek pa...@denx.de
Cc: Marek Vasut
From: Pavel Machek pa...@denx.de
Split the SoCFPGA configuration into SoC-specific part which is
common for all boards (socfpga_cyclone5_common.h) and a board
specific part. There is currently only one board, which is the
generic SoCFPGA board (socfpga_cyclone5.h), but there are more
to come.
Enable and use the CONFIG_CMD_FS_GENERIC to avoid hard-coding the
filesystem type into the environment.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc:
From: Pavel Machek pa...@denx.de
Reorganize and cleanup the configuration file for SoCFPGA. There
is no functional change after this cleanup. This was necessary,
since the file was a wild mess and it was impossible to make sense
of it's content, let alone change something without breaking some
Move icache_enable() and dcache_enable() function calls from
board code into the CPU code and into the enable_caches()
function. This is how the cache enabling code was designed
to work.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Dinh Nguyen dingu...@altera.com
Cc: Pavel Machek pa...@denx.de
Enable support for the DWC2 USB controller.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
From: Oleksandr Tymoshenko go...@bluezbox.com
This is the USB host controller used on the Altera SoCFPGA and Raspbery Pi.
This code has three checkpatch warnings, but to make sure it stays at least
readable and clear, these are not fixed. These bugs are in the USB request
handling combinatorial
This series adds reworked DWC2 USB driver based on work from Oleksandr.
This series also enables that driver on Altera SoCFPGA Cyclone V SoC
and RPi B+ .
The patch 2/3 in this series depends on another series, but as this
series is targetting next, that would be no problem or it can be
skipped.
Enable DWC2 USB, storage and ethernet support. Tested on RPi B+.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Stephen Warren swar...@wwwdotorg.org
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc:
Add support for the Kosagi Novena board. Currently supported are:
- I2C busses
- FEC Ethernet
- MMC0, MMC1, Booting from MMC
- SATA
- USB ports
- USB Ethernet
Signed-off-by: Marek Vasut ma...@denx.de
---
arch/arm/Kconfig | 4 +
board/kosagi/novena/Kconfig | 23 ++
On Tuesday, September 16, 2014 at 01:00:11 PM, Stefano Babic wrote:
On 30/08/2014 16:20, Marek Vasut wrote:
On Saturday, August 30, 2014 at 03:55:48 PM, Fabio Estevam wrote:
On Sat, Aug 30, 2014 at 9:40 AM, Marek Vasut ma...@denx.de wrote:
On Friday, August 29, 2014 at 07:08:54 PM, Fabio
Hi Fabio,
On 21/09/14 02:05, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
We should not hardcode CONFIG_NETMASK in the config file.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
Acked-by: Nikita Kiryanov nik...@compulab.co.il
--
Regards,
Nikita
On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
BOOT_TARGET_DEVICES includes USB unconditionally. This breaks when
CONFIG_CMD_USB is not defined. Use a secondary macro to conditionally
include it when CONFIG_EHCI is enabled, as we do for CONFIG_AHCI.
Signed-off-by: Chen-Yu Tsai
On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
From: Oliver Schinagl oli...@schinagl.nl
A31 has several new and changed memory address. This patch adds them.
Signed-off-by: Oliver Schinagl oli...@schinagl.nl
Signed-off-by: Hans de Goede hdego...@redhat.com
Signed-off-by: Chen-Yu
Hi Andreas,
On Fri, 19 Sep 2014 08:32:28 +0200, Andreas Bießmann
andreas.de...@googlemail.com wrote:
Dear Albert Aribaud,
please pull the following changes into u-boot-arm/master.
The following changes since commit 9170818a4e004af7893fa0113f6e5b4afafded55:
kconfiglib: change
Hi Robert,
On 17 September 2014 02:03, Robert Baldyga r.bald...@samsung.com wrote:
Define CONFIG_SYS_GENERIC_BOARD to make board generic.
Signed-off-by: Robert Baldyga r.bald...@samsung.com
Please see this patch too:
http://patchwork.ozlabs.org/patch/389163/
Regards,
Simon
On 3 September 2014 17:36, Simon Glass s...@chromium.org wrote:
In order to support GPIO access in board_early_init_f() we must set up
driver model before this function is called. In any case, earlier is
better since driver model is (or will become) a key function for most
init.
On 3 September 2014 17:37, Simon Glass s...@chromium.org wrote:
Since driver model registers itself with the stdio subsystem, and we
want to avoid delayed registration and other complexity associated with
the current serial console, move the stdio subsystem init earlier when
driver model is
On 3 September 2014 17:37, Simon Glass s...@chromium.org wrote:
For some boards board_init() will change GPIOs, so we need to have driver
model available before then. Adjust the board init to arrange this, but
enable it for driver model only, just to be safe.
This does create additional
On 3 September 2014 17:37, Simon Glass s...@chromium.org wrote:
Allocate 1KB so that driver model can operate before relocation.
Signed-off-by: Simon Glass s...@chromium.org
Applied to u-boot-dm/master and now in mainline.
___
U-Boot mailing list
On 3 September 2014 17:37, Simon Glass s...@chromium.org wrote:
This is an implementation of GPIOs for Tegra that uses driver model. It has
been tested on trimslice and also using the new iotrace feature.
The implementation uses a top-level GPIO device (which has no actual GPIOS).
Under this
On 4 September 2014 16:27, Simon Glass s...@chromium.org wrote:
The stdio_dev structure has a private pointer for its creator, but it is
not set up by the serial system. Set it to point to the serial device so
that it can be found by code called by stdio.
Signed-off-by: Simon Glass
On 4 September 2014 16:27, Simon Glass s...@chromium.org wrote:
Within /chosen we may have a node which points to another node, similar
to how /aliases works. Add a helper function to do this lookup.
Signed-off-by: Simon Glass s...@chromium.org
Applied to u-boot-dm/master and now in mainline.
On 4 September 2014 16:27, Simon Glass s...@chromium.org wrote:
Allow the caller to find out the device that was bound in response to this
call.
Signed-off-by: Simon Glass s...@chromium.org
Applied to u-boot-dm/master and now in mainline.
___
U-Boot
On 4 September 2014 16:27, Simon Glass s...@chromium.org wrote:
Serial devices support simple byte input/output and a few operations to find
out whether data is available. Add a basic uclass for serial devices to be
used by drivers that are converted to driver model.
Signed-off-by: Simon
On 4 September 2014 16:27, Simon Glass s...@chromium.org wrote:
Adjust the sandbox serial driver to use the new driver model uclass. The
driver works much as before, but within the new framework.
Signed-off-by: Simon Glass s...@chromium.org
Applied to u-boot-dm/master and now in mainline.
On 4 September 2014 16:27, Simon Glass s...@chromium.org wrote:
The current sandbox serial driver is a pretty trivial example and does not
have the featues that might be needed for other board serial drivers. To
help provide a better example, add a text colour property to the device
tree for
On 4 September 2014 16:27, Simon Glass s...@chromium.org wrote:
If the sandbox device tree is provided to U-Boot (with the -d flag) then it
will use the device tree version in preference to the built-in device. The
only difference is the colour.
Signed-off-by: Simon Glass s...@chromium.org
On 4 September 2014 16:27, Simon Glass s...@chromium.org wrote:
Move the function that calculates the baud rate divisor into ns16550.c so
it can be used by that file.
Signed-off-by: Simon Glass s...@chromium.org
Applied to u-boot-dm/master and now in mainline.
On 4 September 2014 16:27, Simon Glass s...@chromium.org wrote:
The same sequence is used in several places, so move it into a function.
Note that UART_LCR_BKSE is an alias for UART_LCR_DLAB.
Signed-off-by: Simon Glass s...@chromium.org
Applied to u-boot-dm/master and now in mainline.
On 4 September 2014 16:27, Simon Glass s...@chromium.org wrote:
Add driver model support so that ns16550 can support operation both with
and without driver model.
The driver needs a clock frequency so cannot stand alone unfortunately. The
clock frequency must be provided by a separate driver.
On 4 September 2014 16:27, Simon Glass s...@chromium.org wrote:
Some Tegra device tree files do not include information about the serial
ports. Add this and also add information about the input clock speed.
The console alias needs to be set up to indicate which port is used for
the console.
On 4 September 2014 16:27, Simon Glass s...@chromium.org wrote:
Use driver model for serial ports.
Since Tegra now uses driver model for serial, adjust the definition of
V_NS16550_CLK so that it is clear that this is only used for SPL.
Signed-off-by: Simon Glass s...@chromium.org
Applied to
Hi Tom,
On Thu, 18 Sep 2014 08:34:22 -0400, Tom Rini tr...@ti.com wrote:
Hello,
The following changes since commit c292adae170fa8c27dca75963bdb0a9afc640e57:
Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' (2014-09-17
23:35:34 +0200)
are available in the git repository at:
On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
From: Oliver Schinagl oli...@schinagl.nl
To setup clocks and control voltages.
perhaps add ... For P2WI and PIO, since that is apparently what it is
doing?
HdG: Rename the files from the somewhat generic pmu name to prcm.{c,h}
HdG:
Hi Tom,
The following changes since commit
9170818a4e004af7893fa0113f6e5b4afafded55:
kconfiglib: change SPDX-License-Identifier to ISC (2014-09-17
21:03:18 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-arm master
for you to fetch changes up to
Hi,
On 09/20/2014 07:42 PM, Michael Trimarchi wrote:
Hi
On Sat, Sep 20, 2014 at 5:01 PM, Hans de Goede hdego...@redhat.com wrote:
Preperation patch to use create_int_queue outside of ehci-hcd.c .
Signed-off-by: Hans de Goede hdego...@redhat.com
---
drivers/usb/host/ehci-hcd.c | 36
Hi,
On 09/20/2014 07:53 PM, Michael Trimarchi wrote:
Hi
On Sat, Sep 20, 2014 at 5:01 PM, Hans de Goede hdego...@redhat.com wrote:
Instead of looking them up every time we need them.
split subject and patch description
Signed-off-by: Hans de Goede hdego...@redhat.com
---
On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
+#ifdef CONFIG_SPL_BUILD
Since there is no SPL support this is dead code right now, correct?
I'm wondering whether we should leave it out of mainline until the SPL
stuff is done, so SPL will be upstreamed all at once. What do others
think?
On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
From: Hans de Goede hdego...@redhat.com
Signed-off-by: Hans de Goede hdego...@redhat.com
[w...@csie.org: use setbits_le32 for reset control, drop obsolete changes,
squash sunxi-mmc: sun6i has its fifo at a different
On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
From: Maxime Ripard maxime.rip...@free-electrons.com
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Signed-off-by: Hans de Goede hdego...@redhat.com
[w...@csie.org: commit message was ARM: sunxi: Setup the A31 UART0
On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
From: Maxime Ripard maxime.rip...@free-electrons.com
Add a new sun6i machine that doesn't do much for now.
Can you briefly outline here what it _does_ do, please.
The actual code looks ok to me. There is some possibility we might
Hi Ian,
On Sun, Sep 21, 2014 at 07:51:17PM +0100, Ian Campbell wrote:
On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
From: Maxime Ripard maxime.rip...@free-electrons.com
Add a new sun6i machine that doesn't do much for now.
Can you briefly outline here what it _does_ do,
On Sunday, September 21, 2014 at 07:53:35 PM, Hans de Goede wrote:
Hi,
[...]
- if (length usb_maxpacket(dev, pipe)) {
- printf(%s: Interrupt transfers requiring several
- transactions are not supported.\n, __func__);
- return -1;
Hi Marek
On Sun, Sep 21, 2014 at 9:36 PM, Marek Vasut ma...@denx.de wrote:
On Sunday, September 21, 2014 at 07:53:35 PM, Hans de Goede wrote:
Hi,
[...]
- if (length usb_maxpacket(dev, pipe)) {
- printf(%s: Interrupt transfers requiring several
-
On Sunday, September 21, 2014 at 10:00:24 PM, Michael Trimarchi wrote:
Hi Marek
On Sun, Sep 21, 2014 at 9:36 PM, Marek Vasut ma...@denx.de wrote:
On Sunday, September 21, 2014 at 07:53:35 PM, Hans de Goede wrote:
Hi,
[...]
- if (length usb_maxpacket(dev, pipe)) {
-
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