Rename the existing bd82x6x_init() to bd82x6x_init_extra(). We will remove
this in a later patch.
Signed-off-by: Simon Glass
---
Changes in v2:
- Drop the init() method in the PCH
- Rename this commit from 'x86: ivybridge: Set up the PCH init'
We have a way to find a regmap by its syscon driver data value. Add the same
for syscon itself.
Signed-off-by: Simon Glass
---
Changes in v2:
- Add missing 'given' word
drivers/core/syscon-uclass.c | 31 +++
include/syscon.h | 14
Move SPI and port80 init to lpc_early_init(), called from the LPC's probe()
method.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/ivybridge/cpu.c | 43 ---
At present this BIOS emulator uses a bus/device/function number. Change
it to use a device if CONFIG_DM_PCI is enabled.
Signed-off-by: Simon Glass
---
Changes in v2:
- Drop unnecessary/incorrect non-DM code in dm_pci_run_vga_bios()
drivers/bios_emulator/atibios.c | 109
This init can happen in the driver also. Move it.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/ivybridge/cpu.c | 4
arch/x86/cpu/ivybridge/lpc.c | 3 +++
2 files changed, 3 insertions(+), 4 deletions(-)
Instead of manually initing the device, probe the SATA device and move the
init there.
Signed-off-by: Simon Glass
---
Changes in v2:
- Update to use the disk uclass
arch/x86/cpu/ivybridge/bd82x6x.c | 13 +
arch/x86/cpu/ivybridge/sata.c
Drop the lpc_init_extra() function and just use the post-relocation LPC
probe() instead.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2:
- Update to use LPC probe() method instead of init()
arch/x86/cpu/ivybridge/bd82x6x.c |
These devices currently need to be inited early in boot. Once we have the
init in the right places (with each device doing its own init and no
problems with ordering) we should be able to remove this. For now it is
needed to keep things working.
Signed-off-by: Simon Glass
---
Hi,
Is there any hook for performing board specific actions prior to
booting the OS. A quick google search turned up this thread from
2014[1]. But the eventual outcome seemed to be that the device model
will take care of restoring devices to their unused state, for
anything else there is
On Tue, 5 Jan 2016 09:31:06 -0700
Simon Glass wrote:
> These two functions are conceptually the same. Move them together in the
> pre-relocation init.
>
> Signed-off-by: Simon Glass
> ---
>
> common/board_f.c | 28 ++--
> 1 file
On Tue, 5 Jan 2016 09:31:12 -0700
Simon Glass wrote:
> Add tests that check that the video console is working correcty. Also check
> that text output produces the expected result. Test coverage includes
> character output, wrapping and scrolling.
>
> Signed-off-by: Simon
Add a compatible string to allow this to be specified in the device tree
if needed.
Signed-off-by: Simon Glass
---
Changes in v2:
- Add missing of_match member init so that ehci_pci_ids[] is used
drivers/usb/host/ehci-pci.c | 6 ++
1 file changed, 6 insertions(+)
diff
We have drivers for several more devices now, so drop the strings which are
no-longer used.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2:
- Drop bd82x6x_pci_init() function and associated DM-conversion patch
- Drop LPC init method an
Adjust this code to use the driver model PCI API. This is all called through
lpc_init_extra().
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/ivybridge/lpc.c | 129 ++-
1
Convert these functions to use the driver model PCI API.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/ivybridge/report_platform.c | 11 ++-
arch/x86/cpu/ivybridge/sdram.c| 2
Instead of calling the northbridge and PCH init from bd82x6x_init_extra()
when the PCI bus is probed, call it from the respective drivers. Also drop
the Northbridge init as it has no effect. The registers it touches appear to
be read-only.
Signed-off-by: Simon Glass
---
Each system controller can have a number to identify it. It can then be
accessed using syscon_get_by_driver_data(). Put this in a shared header
file and update the only current user.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2:
-
Adjust most of the remaining functions in this file to use the driver model
PCI API. The one remaining function is bridge_silicon_revision() which will
need a little more work.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2:
- Drop
Convert this function to use the the driver model PCI API. We just need
to pass in the northbridge device.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/ivybridge/sdram.c | 19 ++-
1 file changed,
This is done by default with PCI auto-config. Drop it.
Signed-off-by: Simon Glass
---
Changes in v2:
- Rename from 'Move northbridge setup to the northbridge driver'
- Drop this unnecessary init
arch/x86/cpu/ivybridge/pci.c | 20
1 file changed, 20
Convert the top part of the DRAM init to use the driver model PCI API.
Further work will complete the transformation.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/ivybridge/sdram.c | 39
We will use a system controller to model the Intel Management Engine. Enable
this for link.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
configs/chromebook_link_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git
On Tue, 5 Jan 2016 09:31:08 -0700
Simon Glass wrote:
> This command can use the bitmap display code in the uclass. This is similar
> to the code in lcd.c and cfb_console.c. These other copies will go away when
> all boards are converted to use driver model for video.
>
>
On Tue, 5 Jan 2016 09:31:11 -0700
Simon Glass wrote:
> Now that driver model support is available, convert sandbox over to use it.
> We can remove a few of the special hooks that sandbox currently has.
>
> Signed-off-by: Simon Glass
> ---
>
>
This is used on most Intel platforms. We don't have a driver for it yet, but
add a stub to handle the init. For now this targets ivybridge so we may want
to add a device tree binding and generalise it when other platforms are
supported.
Signed-off-by: Simon Glass
Reviewed-by:
Adjust the functions in this file to use the driver model PCI API.
Signed-off-by: Simon Glass
---
Changes in v2:
- Drop unnecessary IRQ and command register init
arch/x86/cpu/ivybridge/sata.c | 94 +--
1 file changed, 45
There is nothing special about the ivybridge pci driver now, so just use
the generic one.
Signed-off-by: Simon Glass
---
Changes in v2:
- Drop the special compatible string in chromebook_link.dts
arch/x86/cpu/ivybridge/Makefile | 1 -
arch/x86/cpu/ivybridge/pci.c | 46
We don't need to init the graphics controller so early. Move it alongside
the other graphics setup, just before we run the ROM.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/ivybridge/cpu.c| 1 -
On Tue, 5 Jan 2016 09:31:09 -0700
Simon Glass wrote:
> Register video drivers with stdio so that they can be used for text output.
> This needs to be done explicitly for now. At some point we should be able to
> convert stdio itself to driver model and avoid this step.
>
>
This is often -96 (-EPFNOSUPPORT) which indicates that the uclass is not
compiled in. Display the error number to make this easier to spot.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2:
- Fix -EEPFNOSUPPORT typo
At present ivybridge is the only x86 implementation that includes a
reasonably full board init. This means there is a lot more code than with
a board that uses FSP (even then we don't have memory init or graphics init
code).
This code does not use proper drivers for the devices and so its use of
When the final MRC cache record is the same as the one we want to write, we
skip writing since there is no point. This is normal behaviour.
Avoiding printing an error when this happens.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2:
This function does nothing now so can be dropped.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/ivybridge/bd82x6x.c | 16
arch/x86/cpu/ivybridge/pci.c | 1 -
The watchdog can be reset later when probing the LPC after relocation.
Move it.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2:
- Update to drop LPC init method and use probe() instead
arch/x86/cpu/ivybridge/early_init.c | 16
Add a driver with an empty probe function where we can move init code in
follow-on patches.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/ivybridge/early_init.c | 18 ++
Move this code to the LPC's probe() method so that it will happen
automatically when the LPC is probed before relocation.
Signed-off-by: Simon Glass
---
Changes in v2:
- Drop unused 'gen-dec' device tree property
arch/x86/cpu/ivybridge/cpu.c | 9 -
Add a uclass for the northbridge / SDRAM controller found on some older
Intel chipsets.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2:
- Drop unnecessary DECLARE_GLOBAL_DATA_PTR
arch/x86/lib/Makefile | 1 +
Now that we have a proper driver for the nortbridge, set it up in by probing
it, and move the early init code into the probe() method.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/ivybridge/cpu.c| 2 ++
Find the LPC device in arch_cpu_init_dm() as a first step to converting
this code to use driver model. Probing the LPC will probe its parent (the
PCH) automatically, so make sure that probing the PCH does nothing before
relocation.
Signed-off-by: Simon Glass
---
Changes in
Move the init code into the I2C driver.
Signed-off-by: Simon Glass
Reviewed-by: Heiko Schocher
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/ivybridge/cpu.c | 39 +++
Convert this file to use the driver model PCI API.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/ivybridge/lpc.c | 10
arch/x86/cpu/ivybridge/pch.c | 35
Use the CPU driver's probe() method to perform the CPU init. This will happen
automatically when the first CPU is probed.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/ivybridge/bd82x6x.c | 6 --
The SATA device needs to set itself up so that it appears correctly on the
PCI bus. The easiest way to do this is to set it up to probe before
relocation. This can do the early setup.
Signed-off-by: Simon Glass
---
Changes in v2:
- Update to use the disk uclass
This is not used and MTRRs are set up elsewhere now. Drop it.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/ivybridge/model_206ax.c | 10 --
1 file changed, 10 deletions(-)
diff --git
On Monday, January 18, 2016 at 12:11:07 AM, Simon Glass wrote:
> Add a compatible string to allow this to be specified in the device tree
> if needed.
>
> Signed-off-by: Simon Glass
Acked-by: Marek Vasut
Best regards,
Marek Vasut
Hi Stefan,
On Mon, Jan 18, 2016 at 1:44 AM, Stefan Roese wrote:
> Hi Bin,
>
> On 17.01.2016 03:35, Stefan Roese wrote:
>>
>> On 16.01.2016 15:08, Bin Meng wrote:
>>>
>>> On Fri, Jan 15, 2016 at 10:37 PM, Stefan Roese wrote:
Hi Simon, Hi Bin!
I'm
Hi Tom,
Thanks for your review.
I will update this patch.
Regards,
-Dongsheng
> On Mon, Jan 11, 2016 at 02:51:39AM +, Dongsheng Wang wrote:
> > Hi Tom,
> >
> > Sorry for my late reply, and thanks for your reply.
> >
> > How about the following comments, following your suggestion I remove
>
To enable snooping on CAAM transactions following programmign is done
1. Enable core snooping (CCI interface, Core is Slave5 on CCI)
This setting is also required for making the system coherent
2. CAAM IP lies behind SMMU3 in teh system. Configure SMMU3 to do teh following:
a) Program SCR to
2016-01-17 6:49 GMT+01:00 Wills Wang :
>
>
> On 01/17/2016 03:05 AM, Marek Vasut wrote:
>>
>> On Saturday, January 16, 2016 at 07:13:46 PM, Wills Wang wrote:
>>>
>>> These series of patch add support for atheros ath79 based SOCs in u-boot,
>>> at the present moment it's just
There are two phases in Secure Boot
1. ISBC: In BootROM, validate the BootLoader (U-Boot).
2. ESBC: In U-Boot, continuing the Chain of Trust by
validating and booting LINUX.
For ESBC phase, there is no difference in SoC's based on ARM or PowerPC
cores.
But the exit conditions after ISBC
The file fsl_secure_boot.h must be included in config file
for Secure Boot. This is not required to be protected by any
macro.
CONFIG_FSL_CAAM must be defined and CONFIG_CMD_HASH should be
turned on.
The above was missing in some config files and all files have been
made uniform in this respect.
A function is created to detrmine if the boot mode is secure
or non-secure for differnt SoC's.
Signed-off-by: Aneesh Bansal
---
Changes in v2:
Corrected the macro for SB_EN bit in RCW.
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 ++
There are two phases in Secure Boot
1. ISBC: In BootROM, validate the BootLoader (U-Boot).
2. ESBC: In U-Boot, continuing the Chain of Trust by
validating and booting LINUX.
For ESBC phase, there is no difference in SoC's based on ARM or PowerPC
cores.
But the exit conditions after ISBC
In case of error while executing esbc_validate command, SNVS
transition and issue of reset is required only for secure-boot.
If boot mode is non-secure, this is not required.
Similarly, esbc_halt command which puts the core in Spin Loop
is applicable only for Secure Boot.
Signed-off-by: Aneesh
Chain of Trust is enabled for ARM platforms (LS1021 and LS1043).
In board_late_init(), fsl_setenv_chain_of_trust() is called which
will perform the following:
- If boot mode is non-secure, return (No Change)
- If boot mode is secure, set the following environmet variables:
bootdelay = 0 (To
Chain of Trust is enabled for PowerPC platforms for Secure Boot.
CONFIG_BOARD_LATE_INIT is defined.
In board_late_init(), fsl_setenv_chain_of_trust() is called which
will perform the following:
- If boot mode is non-secure, return (No Change)
- If boot mode is secure, set the following environmet
CONFIG_CMD_BLOB must be defined in case of Secure Boot.
It was earlier defined in all config files. The definition
has been moved to a common file which is included by all configs.
Signed-off-by: Aneesh Bansal
---
Changes in v2:
None (Changed the Sign-Off with New E-Mail
PAMU driver basic support for usage in Secure Boot.
In secure boot PAMU is not in bypass mode. Hence to use
any peripheral (SEC Job ring in our case), PAMU has to be
configured.
The patch reverts commit 7cad2e38d61e27ea59fb7944f7e647e97ef292d3.
The Header file pamu.h and few functions in driver
On 01/17/2016 06:24 PM, Daniel Schwierzeck wrote:
2016-01-17 6:49 GMT+01:00 Wills Wang :
On 01/17/2016 03:05 AM, Marek Vasut wrote:
On Saturday, January 16, 2016 at 07:13:46 PM, Wills Wang wrote:
These series of patch add support for atheros ath79 based SOCs in u-boot,
Convert omap3_spi driver to DM and keep compatibility with previous
mode.
Signed-off-by: Christophe Ricard
---
drivers/spi/Kconfig | 6 +
drivers/spi/omap3_spi.c | 439 ++--
drivers/spi/omap3_spi.h | 14 +-
3 files
For several reasons:
- code clarity
- DM trends in u-boot
...
It is better to make omap3_spi driver 100% DM_SPI based.
Signed-off-by: Christophe Ricard
---
drivers/spi/omap3_spi.c | 474 +++-
drivers/spi/omap3_spi.h | 121
Hi Simon,
This patchset tries to convert the TI omap3_spi driver to Driver Model.
It has been tested on a TI BeagleBoard xM.
Best Regards
Christophe
Christophe Ricard (4):
spi: omap3: Remove unused variable irqstatus in omap3_spi_txrx
spi: spi-uclass: Set slave wordlen with
Remove unused variable irqstatus in omap3_spi_txrx
Signed-off-by: Christophe Ricard
---
drivers/spi/omap3_spi.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index 85f9e85..95cdfa3 100644
---
In some case wordlen may not be set. Use SPI_DEFAULT_WORDLEN as default.
Signed-off-by: Christophe Ricard
---
drivers/spi/spi-uclass.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index 677c020..5561f36
I2C_WAIT macro is not used in the code.
200 is bound to a fixed 10 Hz i2c speed based on an existing formula:
( 1000 / speed ) * 2 where speed = 100 000.
Signed-off-by: Christophe Ricard
---
drivers/i2c/omap24xx_i2c.c | 3 ---
1 file changed, 3 deletions(-)
After several testings and experiment, it appears that waitdelay calculation
formula was giving different behavior on the i2c status registers.
Experiment shows waitdelay needs to be extended at least 4 times to get
proper results.
Signed-off-by: Christophe Ricard
For several reasons:
- code clarity
- DM trends in u-boot
...
It is better to make omap24xx_i2c driver 100% DM_I2C based.
Signed-off-by: Christophe Ricard
---
drivers/i2c/omap24xx_i2c.c | 447 +
drivers/i2c/omap24xx_i2c.h
Work based on i2c-omap.c from linux kernel.
fsscll/fssclh and hsscll/hssclh was always negative in high speed.
i2c high speed frequency start after 400Khz.
Signed-off-by: Christophe Ricard
---
drivers/i2c/omap24xx_i2c.c | 17 +
1 file changed, 9
Convert omap24xx_i2c driver to DM
Signed-off-by: Christophe Ricard
---
drivers/i2c/Kconfig| 8 ++
drivers/i2c/omap24xx_i2c.c | 280 +++--
2 files changed, 277 insertions(+), 11 deletions(-)
diff --git
Hi Simon,
This patchset tries to convert the TI omap24xx_i2c driver to Driver Model.
It has been tested on a TI BeagleBoard xM.
Best Regards
Christophe
Christophe Ricard (5):
i2c: omap24xx: Convert to DM
i2c: omap24xx: Fix waitdelay value for I2C HS
i2c: omap24xx: Remove unused
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
Hi all,
I have found weird feature of Kconfig.
If I misused something, please let me know - I found at least one place
where the same error occurs.
Let's consider the following Kconfig (you can put it anywhere in the source
tree):
Hi,
The following patch series fixes a number of issues I noticed while updating
a sheevaplug from 2013.10 to 2016.01:
Peter Korsgaard (4):
ARM: sheevaplug: unbreak default environment
ARM: sheevaplug: unbreak kernel bootargs / mtdparts command by dropping
double mtdparts=
Commit 1e3d640316 (ARM: sheevaplug: redefine MTDPARTS) changed the partition
layout (without any description why), but didn't change the offset/size to
load the kernel from or the root=/dev/mtdblockX in the bootargs.
The 3MB forseen for a kernel is furthermore too little. A 4.4 build of
Commit 1e3d640316 (ARM: sheevaplug: redefine MTDPARTS) changed the mtdparts
part of the default environment, but dropped the trailing zero termination -
So the definition of x_bootcmd_kernel becomes part of the x_bootargs
variable.
Fix it by reintroducing the zero termination.
Signed-off-by:
Commit 1e3d640316 (ARM: sheevaplug: redefine MTDPARTS) prepended mtdparts=
to the flash partition information in CONFIG_MTDPARTS, but it is used like
"mtdparts=" CONFIG_MTDPARTS - So we end up passing mtdparts=mtdparts=.. to
the kernel, confusing the cmdline partition parser.
Fix it by dropping
The default bootcommand executes x_bootcmd_usb AFTER loading a kernel from
nand and just before executing it, which only slows down boot without adding
any functionality - So drop it.
Signed-off-by: Peter Korsgaard
---
include/configs/sheevaplug.h | 2 +-
1 file changed, 1
Hi Bin,
On 17.01.2016 03:35, Stefan Roese wrote:
On 16.01.2016 15:08, Bin Meng wrote:
On Fri, Jan 15, 2016 at 10:37 PM, Stefan Roese wrote:
Hi Simon, Hi Bin!
I'm currently busy with porting U-Boot to a Bay Trail board.
Equipped with an Intel Atom E3845 and additionally the
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