Hello Marek,
If the USB is detected successfully, then below are the logs.
U-Boot > usb start
(Re)start USB...
USB0: USB EHCI 1.00
scanning bus 0 for devices... New Device 0
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x100 index 0x0 length
0x40
set address 1
usb_control_msg: req
This patch adds DM support to the designware I2C driver. It currently
supports DM and the legacy I2C support. The legacy support should be
removed, once all platforms using it have DM enabled.
Signed-off-by: Stefan Roese
Reviewed-by: Simon Glass
Reviewed-by: Bin Meng
Cc: Marek Vasut
Cc: Heiko
This patch adds support for the PCI(e) based I2C cores. Which can be
found for example on the Intel Bay Trail SoC. It has 7 I2C controllers
implemented as PCI devices.
This patch also adds the fixed values for the timing registers for
BayTrail which are taken from the Linux designware I2C driver.
Integrating set_speed() into dw_i2c_set_bus_speed() will make the
conversion to DM easier for this driver.
Signed-off-by: Stefan Roese
Cc: Simon Glass
Reviewed-by: Bin Meng
Cc: Marek Vasut
Cc: Heiko Schocher
---
v4:
- Rebased on latest mainline
drivers/i2c/designware_i2c.c | 37
This patch prepares the designware I2C driver for the DM conversion.
This is mainly done by removing struct i2c_adapter from the functions
that shall be used by the DM driver version as well.
Signed-off-by: Stefan Roese
Reviewed-by: Simon Glass
Reviewed-by: Bin Meng
Cc: Marek Vasut
Cc: Heiko S
dw_i2c_enable() is used to dis-/en-able the I2C controller. It makes
sense to add such a function, as the controller is dis-/en-abled
multiple times in the code. Additionally, this function now checks,
if the controller is really dis-/en-abled. This code is copied
from the Linux I2C driver version.
Add the ic_enable_status register to the i2c_regs struct. Additionally
the register offsets are added, to better check, if the offset matches
the register description in the datasheet.
Signed-off-by: Stefan Roese
Cc: Simon Glass
Reviewed-by: Bin Meng
Cc: Marek Vasut
Cc: Heiko Schocher
---
v4:
On Friday 15 April 2016 05:57 PM, Dan Murphy wrote:
> The code assumed that if the interface is not RGMII configured
> then it must be SGMII configured. This device has the ability
> to support most of the MII interfaces. Therefore add the
> helper for SGMII and only configure the device if the i
On Friday 15 April 2016 05:57 PM, Dan Murphy wrote:
> Not all devices use the same internal delay or fifo depth.
> Add the ability to set the internal delay for rx or tx and the
> fifo depth via the devicetree. If the value is not set in the
> devicetree then set the delay to the default.
>
> If
On Friday 15 April 2016 05:57 PM, Dan Murphy wrote:
> Add a helper to phy.h to identify whether the
> phy is configured for SGMII all variables.
>
> Signed-off-by: Dan Murphy
> Reviewed-by: Mugunthan V N
> Reviewed-by: Michal Simek
Tested this on dra72 rev C evm
Tested-by: Mugunthan V N
Reg
On Friday 15 April 2016 05:57 PM, Dan Murphy wrote:
> Move the phy_interface_is_rgmii to the phy.h
> file for all phy's to be able to use the API.
>
> This now aligns with the Linux kernel based on
> commit e463d88c36d42211aa72ed76d32fb8bf37820ef1
>
> Signed-off-by: Dan Murphy
> Reviewed-by: Mug
On Friday 15 April 2016 05:57 PM, Dan Murphy wrote:
> Add the device tree bindings and the accompanying documentation
> for the TI DP83867 Giga bit ethernet phy driver.
>
> The original document was from:
> [commit 2a10154abcb75ad0d7b6bfea6210ac743ec60897 from the Linux kernel]
>
> Signed-off
On Friday 15 April 2016 05:57 PM, Dan Murphy wrote:
> Add the ability to read the phy-handle node of the
> cpsw slave. Upon reading this handle the phy-id
> can be stored based on the reg node in the DT.
>
> The phy-handle also needs to be stored and passed
> to the phy to access any phy data tha
On Wednesday 20 April 2016 08:09 PM, Simon Glass wrote:
> Hi Mugunthan,
>
> On 1 April 2016 at 05:29, Mugunthan V N wrote:
>> Implement a NAND uclass so that the NAND devices can be
>> accessed via the DM framework.
>>
>> Signed-off-by: Mugunthan V N
>> ---
>> drivers/mtd/nand/Kconfig | 1
- Forwarded Message -
From: "Manjunath"
To: "fabio estevam"
Sent: Wednesday, April 20, 2016 4:03:05 PM
Subject: Re: EHCI timed out on TD - token=0x80008d80
Hi Fabio,
No it doesn't.
I enabled debug prints and i get the following.
U-Boot > usb start
(Re)start USB...
USB0: USB EHCI 1
On 04/06/2016 05:22 AM, Jagan Teki wrote:
On 5 April 2016 at 05:31, Tom Rini wrote:
On Mon, Apr 04, 2016 at 11:03:52AM -0600, Stephen Warren wrote:
From: Stephen Warren
get_timer() returns an unsigned 64-bit value, but is currently assigned to
a signed 32-bit variable. Due to sign extension
On 20.4.2016 21:41, Dan Murphy wrote:
> Bump?
> On 04/15/2016 07:27 AM, Dan Murphy wrote:
>> Add the ability to pass the phy-handle node offset
>> to the phy driver. This allows the phy driver
>> to access the DT subnode's data and parse accordingly.
>>
>> Signed-off-by: Dan Murphy
>> Tested-by:
The current table look-up for the DTB file name turned out bothersome
in terms of maintainability; I ended up adding a new entry every time
a new board is supported.
There is a common pattern between the DT compatible string and the
corresponding file name; drop the vendor prefix "socionext," and
PH1-LD20 does not support 1.8V signaling for SD card; only Default
Speed and High Speed (up to 50MHz) with 3.3V signaling is supported.
Signed-off-by: Masahiro Yamada
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/dts/uniphier-ph1-ld20.dtsi | 17 +
1 f
On 1 April 2016 at 05:29, Mugunthan V N wrote:
> The terminator endif of ifdef _NAND_H_ should be at the
> end of file as a fail safe.
>
> Signed-off-by: Mugunthan V N
> ---
> include/nand.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Simon Glass
__
Hi Hugo,
On 24 March 2016 at 04:44, Hugo Heutinck wrote:
> Hello, I was attempting to create a custom u-boot command. But I am not
> able to get the
> "run_command" or "cli_simple_run_command" to work.
>
> I`m building u-boot: am335x_boneblack_defconfig
>
> Attempting to use the "run_command" fun
On Tue, Apr 19, 2016 at 05:19:52PM -0300, Otavio Salvador wrote:
> On Tue, Apr 19, 2016 at 5:13 PM, Fabio Estevam wrote:
> > On Tue, Apr 19, 2016 at 4:22 PM, Otavio Salvador
> > wrote:
> >
> >> This is a huge step back; why it cannot be fixed in the SPL properly?
> >
> > Maybe it can, but as expl
Hi Bin,
On 20 April 2016 at 07:45, Bin Meng wrote:
>
> Hi Simon,
>
> On Wed, Apr 20, 2016 at 9:13 PM, Simon Glass wrote:
> > Hi Bin,
> >
> > On 13 April 2016 at 01:52, Bin Meng wrote:
> >> Our own ACPI implementation (when CONFIG_QEMU_ACPI_TABLE is not set)
> >> does not build anymore after x86
On Tue, Apr 19, 2016 at 08:41:52PM -0500, Dinh Nguyen wrote:
> Move common config options like these to socfpga_*_defconfig:
>
> CONFIG_CMD_ASKENV
> CONFIG_CMD_BOOTZ
> CONFIG_CMD_CACHE
> CONFIG_CMD_DHCP
> CONFIG_CMD_EXT4
> CONFIG_CMD_EXT4_WRITE
> CONFIG_CMD_FAT
> CONFIG_CMD_FS_GENERIC
> CONFIG_CM
On Wed, Apr 20, 2016 at 12:05:59PM +0300, Sam Protsenko wrote:
> According to common eMMC partition table for Android boot (see
> PARTS_DEFAULT definition in include/configs/dra7xx_evm.h), "bootloader"
> partition (where u-boot.img is stored) starts at 256 KiB. Which is equal
> to 512 sectors (as
Make function/array names match the file names for consistency.
Signed-off-by: Masahiro Yamada
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c | 34
drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c | 34 +
Bump?
On 04/15/2016 07:27 AM, Dan Murphy wrote:
> Add the ability to pass the phy-handle node offset
> to the phy driver. This allows the phy driver
> to access the DT subnode's data and parse accordingly.
>
> Signed-off-by: Dan Murphy
> Tested-by: Michal Simek
> ---
>
> v6 - No changes - https:
On 19 April 2016 at 14:58, Stephen Warren wrote:
> From: Stephen Warren
>
> TEGRA_PORTS_PER_BANK and TEGRA_GPIO_PORTS represent the same thing.
> TEGRA_GPIO_PORTS is more widely used, so replace all usage with that,
> and remove the redundant definition.
>
> Signed-off-by: Stephen Warren
> ---
>
On 12 April 2016 at 05:33, Vignesh R wrote:
> Convert davinci_spi driver to comply with SPI DM framework.
>
> Signed-off-by: Vignesh R
> ---
> drivers/spi/davinci_spi.c | 326
> +-
> 1 file changed, 237 insertions(+), 89 deletions(-)
>
> diff --git a/
On 11 April 2016 at 21:09, Wills Wang wrote:
> The correct pinctrl is handled automatically so we don't need to do it in
> the driver.
>
> Signed-off-by: Wills Wang
> ---
>
> drivers/serial/serial_ar933x.c | 16 ++--
> 1 file changed, 2 insertions(+), 14 deletions(-)
Reviewed-by: Si
Masahiro Yamada (13):
pinctrl: uniphier: rename function/array names
pinctrl: uniphier: fix NAND and SD pin-mux settings for PH1-LD11/LD20
ARM: uniphier: avoid unaligned access to DT on 64bit SoC
ARM: dts: uniphier: use Ref Daughter board on PH1-LD20 Ref board
ARM: dts: uniphier: move al
Copy the kernel image double-word-wise rather than byte-wise.
Signed-off-by: Masahiro Yamada
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
include/configs/uniphier.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/configs/uniphier.h b/include/con
PH1-LD20 needs this for its SD card controller.
Signed-off-by: Masahiro Yamada
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/clk/uniphier/clk-uniphier-mio.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c
b/drivers/clk/
This makes the EEPROM device on the Reference Daughter board
available.
Signed-off-by: Masahiro Yamada
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/dts/uniphier-ph1-ld20-ref.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/uniphier-ph1-ld20-ref.d
Currently, fdtgrep would not accept uniphier-ph1-ld20-ref.dtb
and uniphier-ph1-ld11-ref.dtb unless the aliases node comes
the first in the root node.
$ make -s uniphier_pxs2_ld6b_defconfig
$ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-ld20-ref
[snip]
LDS spl/u-boot-spl.l
The last 64 byte of each DDR channel of PH1-LD20 is periodically
used as a scratch area for the DDR PHY training.
Signed-off-by: Masahiro Yamada
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
include/configs/uniphier.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/incl
This is the first ARMv8 SoC from Socionext Inc.
Signed-off-by: Masahiro Yamada
---
Changes in v4: None
Changes in v3:
- Implement spin-table
- Add timer_init
- Add cci-500 init
Changes in v2:
- Enable booti command
- add early_clk_init func()
arch/arm/mach-uniphier/Kconfig
I found many mistakes in the initial version.
Fixes: 8a3328c209d0 ("pinctrl: uniphier: support UniPhier PH1-LD20 pinctrl
driver")
Signed-off-by: Masahiro Yamada
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c | 8
1 fil
No need to stop booting U-Boot even if boot mode is unknown.
Setting the "bootmode" environment is only useful for booting
Linux Kernel. Anyway, U-Boot has already booted by this point.
Signed-off-by: Masahiro Yamada
---
Changes in v4:
- Newly added
Changes in v3: None
Changes in v2: None
For PH1-LD20 or later, per-pin input-enable control is supported,
that is, we need to set-up IECTRL registers for a group of pins.
This helper function will be useful for a bunch of register settings.
Signed-off-by: Masahiro Yamada
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
Because DT properties are 4-byte aligned, the pointer access
*(fdt64_t *) in this code causes unaligned access.
Signed-off-by: Masahiro Yamada
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/mach-uniphier/dram_init.c | 10 --
1 file changed, 4 insertions(+), 6
On 19 April 2016 at 14:58, Stephen Warren wrote:
> From: Stephen Warren
>
> Future Tegra chips contain multiple entirely separate GPIO controllers. It
> is plausible that boards using those chips will end up with non-DT-driven
> code that manipulates GPIOs, just like a few Tegra boards do today.
On Wed, Apr 20, 2016 at 05:46:53PM +0200, Marek Vasut wrote:
> On 04/20/2016 05:01 PM, Tom Rini wrote:
> > Previously, ret could be used uninitialized if
> > blk_get_device_part_str() failed. Default to ret being set to -1 so
> > that we always return an err up if we have a problem and then invert
On 04/11/2016 02:02 AM, Zhao Qiang wrote:
> This reverts commit 5066e62847bddf6030262ade2aa3e7bcdc930037.
>
> The reverted patch will block t2080RDB iNiC, it was a workaround for
> T2080QDS
> down-training issue, we need to revert it and find the root cause for
> T2080QDS
> down-training issue.
Y
This patch adds myself as maintainer for the hikey
U-Boot port.
Signed-off-by: Peter Griffin
---
MAINTAINERS | 6 ++
board/hisilicon/hikey/MAINTAINERS | 6 ++
2 files changed, 12 insertions(+)
create mode 100644 board/hisilicon/hikey/MAINTAINERS
diff --git a/MAINT
On 04/20/2016 04:06 AM, Aneesh Bansal wrote:
>> -Original Message-
>> From: York Sun [mailto:york@nxp.com]
>> Sent: Tuesday, April 19, 2016 10:03 PM
>> To: Aneesh Bansal ; u-boot@lists.denx.de
>> Cc: Ruchika Gupta ; Prabhakar Kushwaha
>>
>> Subject: Re: [PATCH] powerpc/mpc85xx: set L2P
On some platforms (e.g. x86), the return value of dev_get_addr() can't
be assigned to a pointer type variable directly. As there might be a
difference between the size of fdt_addr_t and the pointer type. On
x86 for example, "fdt_addr_t" is 64bit but "void *" only 32bit. So
assigning the register ba
With the addition of GPIO_ACTIVE_LOW parsing in gpio-uclass,
the omap gpio driver doesn't need a custom xlate routine.
Signed-off-by: Eric Nelson
Acked-by: Simon Glass
---
V2 removes the include of
drivers/gpio/omap_gpio.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/driver
Hi Michal,
On 14 April 2016 at 07:02, Michal Simek wrote:
> Fix fdtdec_get_alias_seq() which is not checking full path to certain
> node and it incorrectly provides incorrect seq number.
> Checking full path ensure that if alias is present correct seq number is
> return.
> This problem was found
Hi Simon,
On 04/20/2016 07:40 AM, Simon Glass wrote:
> Hi Eric,
>
> On 11 April 2016 at 11:17, Eric Nelson wrote:
>> On 04/11/2016 09:53 AM, Simon Glass wrote:
>>> On 11 April 2016 at 10:10, Stephen Warren wrote:
On 04/11/2016 09:12 AM, Simon Glass wrote:
> On 11 April 2016 at 09:10, E
Hi Dinh,
On 19 April 2016 at 19:41, Dinh Nguyen wrote:
> Add the following CMD options to Kconfig:
>
> CMD_BOOTZ
> CMD_ASKENV
> CMD_GREPENV
> CMD_USB_MASS_STORAGE
> CMD_FAT
> CMD_MII
> CMD_CACHE
> CMD_DFU
> CMD_EXT2
> CMD_EXT4
> CMD_EXT4_WRITE
> CMD_FS_GENERIC
> CMD_MMC
>
> Signed-off-by: Dinh Ng
Hi Michal,
On 14 April 2016 at 06:15, Michal Simek wrote:
> Add support for common TI i2c mux which is available on ZynqMP zcu102
> board.
> DM i2c mux core code is selecting/deselecting bus before/after
> every command is performed that's why only one channel is active at a
> time. That's also t
On 14 April 2016 at 02:21, wrote:
> From: Tang Yuantian
>
> Ensure data the following sata command used is flushed out of dcache
> and written to physical memory or timeout error may happen.
>
> Signed-off-by: Tang Yuantian
> ---
> drivers/block/ahci.c | 1 +
> 1 file changed, 1 insertion(+)
Hi Peng,
On 13 April 2016 at 01:18, Peng Fan wrote:
> Introduce driver to support "fairchild,74hc595" devices.
> 1. Take linux drivers/drivers/gpio/gpio-74x164.c as reference.
> 2. Following the naming used in Linux driver with gen_7x164 as the prefix.
> 3. Enable CONFIG_DM_74X164 to use this dri
On 13 April 2016 at 01:18, Peng Fan wrote:
> 1. Support compatible string "spi-gpio" which is used by Linux
>Linux use different bindings, so use UBOOT_COMPAT and
>LINUX_COMPAT to differentiate them.
> 2. Introduce SPI_MASTER_NO_RX and SPI_MASTER_NO_TX to handle
>no rx or no tx case.
>
On 13 April 2016 at 01:18, Peng Fan wrote:
> When doing xfer, should use device->parent, but not device
> When doing bit xfer, should use "!!(tmpdout & 0x80)", but not
> "(tmpdout & 0x80)"
>
> Signed-off-by: Peng Fan
> Cc: Simon Glass
> ---
>
> V2:
> Follow Simon's comments, split bug fix into
On 11 April 2016 at 16:21, Eric Nelson wrote:
> Call blk_dwrite to ensure that the block cache is notified
> if enabled and remove build breakage when CONFIG_BLK is enabled.
>
> Signed-off-by: Eric Nelson
> ---
> lib/gunzip.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
Reviewed
On 11 April 2016 at 21:09, Wills Wang wrote:
> The correct pinctrl is handled automatically so we don't need to do it in
> the driver.
>
> Signed-off-by: Wills Wang
> ---
>
> drivers/spi/ath79_spi.c | 12
> 1 file changed, 12 deletions(-)
Reviewed-by: Simon Glass
_
On some platforms (e.g. x86), the return value of dev_get_addr() can't
be assigned to a pointer type variable directly. As there might be a
difference between the size of fdt_addr_t and the pointer type. On
x86 for example, "fdt_addr_t" is 64bit but "void *" only 32bit. So
assigning the register ba
Hi Eric,
On 11 April 2016 at 11:17, Eric Nelson wrote:
> On 04/11/2016 09:53 AM, Simon Glass wrote:
>> Hi,
>>
>> On 11 April 2016 at 10:10, Stephen Warren wrote:
>>> On 04/11/2016 09:12 AM, Simon Glass wrote:
Hi Eric,
On 11 April 2016 at 09:10, Eric Nelson wrote:
>
>
>
Hi Qianyu,
[...]
@@ -308,6 +307,11 @@ int spi_get_bus_and_cs(int busnum, int cs, int
>>> speed, int
>>>
mode,
>>>
slave->dev = dev;
>>>
}
>>>
>>>
+ plat = dev_get_parent_platdata(dev);
>>>
+ if (!speed) {
Hi Simon,
On 20.4.2016 16:41, Simon Glass wrote:
> Hi Michal,
>
> On 14 April 2016 at 07:02, Michal Simek wrote:
>> Fix fdtdec_get_alias_seq() which is not checking full path to certain
>> node and it incorrectly provides incorrect seq number.
>> Checking full path ensure that if alias is presen
Hi Muganthan,
On 4 April 2016 at 05:58, Mugunthan V N wrote:
> Add request gpio for CD and WP gpios, so that the gpio can be
> used for the respective purposes.
>
> Signed-off-by: Mugunthan V N
> ---
> drivers/mmc/omap_hsmmc.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/driver
Hi Simon,
> -Original Message-
> From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
> Sent: Wednesday, April 20, 2016 10:41 PM
> To: Qianyu Gong
> Cc: u-boot@lists.denx.de; Mingkai Hu ; Yao Yuan
> ; jt...@openedev.com
> Subject: Re: A problem about 'sf probe' using DM
Hi Vignesh,
> -Original Message-
> From: Vignesh R [mailto:vigne...@ti.com]
> Sent: Wednesday, April 20, 2016 6:47 PM
> To: Qianyu Gong ; jt...@openedev.com;
> tr...@konsulko.com
> Cc: u-boot@lists.denx.de; s...@denx.de; Mingkai Hu
> Subject: Re: [U-Boot] [PATCH v3] dm: spi: Read default
Any comments?
Thanks.
Best regards,
Yangbo Lu
> -Original Message-
> From: Yangbo Lu [mailto:yangbo...@nxp.com]
> Sent: Wednesday, March 09, 2016 11:00 AM
> To: u-boot@lists.denx.de
> Cc: Pantelis Antoniou; Yangbo Lu
> Subject: [PATCH] mmc: send CMD0 before CMD1 for some MMC cards
>
> W
On 04/21/2016 04:46 AM, Yang, Wenyou wrote:
> Hi,
Hi!
[...]
pile of unnecessary email headers redacted.
[...]
Hi!
I've been playing around with latest mainline u-boot on sama5d2
xplained ultra. I noticed that if I want to boot the board from
SD card (
For PH1-LD20 or later, per-pin input-enable control is supported,
that is, we need to set-up IECTRL registers for a group of pins.
This helper function will be useful for a bunch of register settings.
Signed-off-by: Masahiro Yamada
---
Changes in v3: None
Changes in v2: None
arch/arm/mach-unip
Copy the kernel image double-word-wise rather than byte-wise.
Signed-off-by: Masahiro Yamada
---
Changes in v3: None
Changes in v2: None
include/configs/uniphier.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
inde
The last 64 byte of each DDR channel of PH1-LD20 is periodically
used as a scratch area for the DDR PHY training.
Signed-off-by: Masahiro Yamada
---
Changes in v3: None
Changes in v2: None
include/configs/uniphier.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/uniphier
Currently, fdtgrep would not accept uniphier-ph1-ld20-ref.dtb
and uniphier-ph1-ld11-ref.dtb unless the aliases node comes
the first in the root node.
$ make -s uniphier_pxs2_ld6b_defconfig
$ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-ld20-ref
[snip]
LDS spl/u-boot-spl.l
PH1-LD20 does not support 1.8V signaling for SD card; only Default
Speed and High Speed (up to 50MHz) with 3.3V signaling is supported.
Signed-off-by: Masahiro Yamada
---
Changes in v3: None
Changes in v2: None
arch/arm/dts/uniphier-ph1-ld20.dtsi | 17 +
1 file changed, 17 inse
This is the first ARMv8 SoC from Socionext Inc.
Signed-off-by: Masahiro Yamada
---
Changes in v3:
- Implement spin-table
- Add timer_init
- Add cci-500 init
Changes in v2:
- Enable booti command
- add early_clk_init func()
arch/arm/mach-uniphier/Kconfig| 5 +
a
Because DT properties are 4-byte aligned, the pointer access
*(fdt64_t *) in this code causes unaligned access.
Signed-off-by: Masahiro Yamada
---
Changes in v3: None
Changes in v2: None
arch/arm/mach-uniphier/dram_init.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff -
This makes the EEPROM device on the Reference Daughter board
available.
Signed-off-by: Masahiro Yamada
---
Changes in v3: None
Changes in v2: None
arch/arm/dts/uniphier-ph1-ld20-ref.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/uniphier-ph1-ld20-ref.dts
b/arch/arm/dts/u
I found many mistakes in the initial version.
Fixes: 8a3328c209d0 ("pinctrl: uniphier: support UniPhier PH1-LD20 pinctrl
driver")
Signed-off-by: Masahiro Yamada
---
Changes in v3: None
Changes in v2: None
drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c | 8
1 file changed, 4 inserti
Make function/array names match the file names for consistency.
Signed-off-by: Masahiro Yamada
---
Changes in v3: None
Changes in v2: None
drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c | 34
drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c | 34 -
Masahiro Yamada (11):
pinctrl: uniphier: rename function/array names
pinctrl: uniphier: fix NAND and SD pin-mux settings for PH1-LD11/LD20
ARM: uniphier: avoid unaligned access to DT on 64bit SoC
ARM: dts: uniphier: use Ref Daughter board on PH1-LD20 Ref board
ARM: dts: uniphier: move ali
Hi,
> -Original Message-
> From: Marek Vasut [mailto:ma...@denx.de]
> Sent: 2016年4月21日 10:41
> To: Yang, Wenyou
> Cc: u-boot@lists.denx.de
> Subject: Re: SAMA5D2 xplained SD/eMMC boot
>
> On 04/21/2016 04:30 AM, Yang, Wenyou wrote:
> > Hi Marek,
>
> Hi!
>
> >> -Original Message
PH1-LD20 needs this for its SD card controller.
Signed-off-by: Masahiro Yamada
---
Changes in v3: None
Changes in v2: None
drivers/clk/uniphier/clk-uniphier-mio.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c
b/drivers/clk/uniphier/clk-uniphie
On 04/21/2016 04:30 AM, Yang, Wenyou wrote:
> Hi Marek,
Hi!
>> -Original Message-
>> From: Marek Vasut [mailto:ma...@denx.de]
>> Sent: 2016年4月20日 17:37
>> To: Yang, Wenyou
>> Cc: u-boot@lists.denx.de
>> Subject: Re: SAMA5D2 xplained SD/eMMC boot
Can you fix your mailer so it doesn't ins
Hi Marek,
> -Original Message-
> From: Marek Vasut [mailto:ma...@denx.de]
> Sent: 2016年4月20日 17:37
> To: Yang, Wenyou
> Cc: u-boot@lists.denx.de
> Subject: Re: SAMA5D2 xplained SD/eMMC boot
>
> On 04/20/2016 03:17 AM, Yang, Wenyou wrote:
> > Hi Marek,
> >
> >> -Original Message-
From: Fabio Estevam
The error message "spl: mmc block read error" may come from two
different functions, so we should better annotate the function name
where the error comes from to help debugging.
Signed-off-by: Fabio Estevam
---
common/spl/spl_mmc.c | 4 ++--
1 file changed, 2 insertions(+),
On Wed, Apr 20, 2016 at 11:17 AM, Tom Rini wrote:
> I just want to echo this. Perhaps you can make the non-SPL case fail by
> turning off some of the clock lines / similar in the preamble of the DCD
> script? Otherwise ROM is just doing some black magic enabling?
Ok, I sent a fix for the SPL c
From: Fabio Estevam
mx6ul_evk does not come with a eMMC populated, so we should not
define CONFIG_SUPPORT_EMMC_BOOT as it causes SPL to not be able
to boot some brands of SD cards, such as SanDisk microSD HC - 8GB:
U-Boot SPL 2016.05-rc1-28384-g108f841 (Apr 19 2016 - 11:19:11)
T
hi guys
is threr anyone who can help me on Memtest FOR DIMM?
it alway test with just one module on MOBO. then:
a. same fail information(address)found on different DIMM
b.same fail information on different componet on one DIMM
how can it happen with same fail on two different DIMM or componet?
Hi Simon,
On Wed, Apr 20, 2016 at 08:40:10AM -0600, Simon Glass wrote:
>Hi Peng,
>
>On 10 April 2016 at 23:34, Peng Fan wrote:
>> Hi Simon,
>>
>> On Sat, Apr 09, 2016 at 12:34:13PM -0600, Simon Glass wrote:
>>>Hi Peng,
>>>
>>>On 15 March 2016 at 19:32, Peng Fan wrote:
In device tree, there
Hi Simon,
On Wed, Apr 20, 2016 at 08:40:45AM -0600, Simon Glass wrote:
>Hi Peng,
>
>On 13 April 2016 at 01:18, Peng Fan wrote:
>> Introduce driver to support "fairchild,74hc595" devices.
>> 1. Take linux drivers/drivers/gpio/gpio-74x164.c as reference.
>> 2. Following the naming used in Linux dri
+Roy to comment on iNIC.
On 04/20/2016 06:05 PM, Qiang Zhao wrote:
> On 04/21/2016 12:58 AM, York Sun wrote:
>> -Original Message-
>> From: York Sun [mailto:york@nxp.com]
>> Sent: Thursday, April 21, 2016 12:58 AM
>> To: Qiang Zhao
>> Cc: Xiaobo Xie ; u-boot@lists.denx.de
>> Subject:
Hi Pablo,
On Thu, Apr 21, 2016 at 9:14 AM, Pablo Fonovich wrote:
> Hi:
> Thanks for your answer!
> So I must flash the u-boot.Rom in the spi flash, and boot from them, but I
> still can put the rest of the system in the ad and configure u-boot to load
> kernel and device-tree from sd, am I right?
On 04/21/2016 12:58 AM, York Sun wrote:
> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Thursday, April 21, 2016 12:58 AM
> To: Qiang Zhao
> Cc: Xiaobo Xie ; u-boot@lists.denx.de
> Subject: Re: [PATCH] Revert "T2080QDS/PCIe: Soft Reset PCIe on T2080QDS for
> down-tr
Hi Pablo,
On Thu, Apr 21, 2016 at 4:22 AM, Pablo Fonovich wrote:
> Hi:
>
> I previously worked with u-boot for beaglebone black for booting a custom
> linux system. Now the university got a donnation of some galileo boards, and
> we want to do something similar.
>
> The problem is that we don't k
On Wed, Apr 20, 2016 at 11:17 AM, Tom Rini wrote:
> I just want to echo this. Perhaps you can make the non-SPL case fail by
> turning off some of the clock lines / similar in the preamble of the DCD
> script? Otherwise ROM is just doing some black magic enabling?
The SPL code enables all the C
On Sat, Apr 16, 2016 at 04:23:27AM -0400, Robert P. J. Day wrote:
> just noticed, in common/dlmalloc.c, the sizable chunk:
>
> #if 0 /* Moved to malloc.h */
> /* -- To make a malloc.h, start cutting here */
>
> ... several hundred lines ...
>
> #ifdef __
From: Stephen Warren
Tegra186's GPIO controller register layout is significantly different from
previous chips, so add a new driver for it. In fact, there are two
different GPIO controllers in Tegra186 that share a similar register
layout, but very different port mapping. This driver covers both.
From: Stephen Warren
Currently, if multiple rtl8169 devices exist on the PCI bus, they all
get the same name, which prevents the user from selecting which to use
via the ethact environment variable. Port the auto-naming code from the
e1000 driver to solve this.
Signed-off-by: Stephen Warren
---
On Sat, Apr 16, 2016 at 01:30:00PM -0400, Robert P. J. Day wrote:
> more teeth-gnashing pedantry ... is Kconfig standard "help" or
> "---help---"?
Looking at Documentation/kbuild/kconfig-language.txt in the kernel:
- help text: "help" or "---help---"
This defines a help text. The end of the
On Mon, Apr 11, 2016 at 06:37:18PM -0500, Daniel Allred wrote:
> Adds new defconfig files for DRA7xx and AM57xx secure devices.
> These are the same as the non-secure parts, but with the addition
> of the CONFIG_TI_SECURE_DEVICE option set to 'y'.
>
> Signed-off-by: Daniel Allred
> Signed-off-by:
On Mon, Apr 11, 2016 at 06:37:15PM -0500, Daniel Allred wrote:
> Adds an fdt.c file in that defines the ft_cpu_setup() function,
> which should be called from a board-specific ft_board_setup()).
> This ft_cpu_setup() will currently do nothing for non-secure (GP)
> devices but contains pertine
On Mon, Apr 11, 2016 at 06:37:16PM -0500, Daniel Allred wrote:
> Adds the board specific ft_board_setup() functions that
> are called when CONFIG_OF_BOARD_SETUP is defined. These functions
> will currently just call the ft_cpu_setup() function.
>
> Signed-off-by: Daniel Allred
> Signed-off-by: Ma
1 - 100 of 189 matches
Mail list logo
