Re: [U-Boot] [PATCH v3 3/3] sunxi: add support for Lichee Pi Zero

On Thu, Feb 16, 2017 at 01:32:19AM +, André Przywara wrote: > Whether we need PSCI on an UP system is a separate question, I don't > know from the top of my head if ARM(32) uses it for suspend/resume. But > anyway this is not implemented in U-Boot's PSCI implementation, IIRC. Antoine (in CC)

Re: [U-Boot] [PATCH v2] armv7m: Add SysTick timer driver

Hi Vikas, On 15 February 2017 23:50, Vikas MANOCHA wrote: > Hi Phil, > > > -Original Message- > > From: Phil Edworthy [mailto:phil.edwor...@renesas.com] > > Sent: Monday, February 13, 2017 11:48 PM > > To: Albert Aribaud > > Cc: Tom Rini ;

[U-Boot] [PATCH] ARM: uniphier: remove dram_nr_ch from board parameters

This parameter is redundant because we can know the number of channels by checking if dram_ch[2].size is zero. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/boards.c| 12 arch/arm/mach-uniphier/dram/umc-ld11.c | 2 +-

[U-Boot] [PATCH v2 3/3] configs: am43xx_evm: Enable SPL_DM

Enable SPL_DM on all AM43xx based platforms Signed-off-by: Lokesh Vutla --- configs/am43xx_evm_defconfig | 8 +++- configs/am43xx_evm_usbhost_boot_defconfig | 8 +++- configs/am43xx_hs_evm_defconfig | 8 +++- include/configs/am43xx_evm.h

[U-Boot] [PATCH v2 2/3] config: am43xx_usbhost_boot: sync with am43xx_evm

am43xx_evm defconfig has been modified without making changes in am43xx_usbhost_boot defconfig. Synce here. Signed-off-by: Lokesh Vutla --- configs/am43xx_evm_usbhost_boot_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git

[U-Boot] [PATCH v2 0/3] ARM: AM43xx: Enable SPL_DM

Enable SPL_DM on all AM4xx based boards. This series depends on: - DRA7 SPL_DM series[1] - http://patchwork.ozlabs.org/patch/727106/ [1] https://www.mail-archive.com/u-boot@lists.denx.de/msg238751.html Changes since v1: - Fixed build error with non-SPL_DM defconfigs - Increased SYS_MALLOC_F_LEN

[U-Boot] [PATCH v2 1/3] ARM: dts: am43xx: Add u-boot specific dtsi

Add u-boot specific dtsi for am43xx-gp-evm so that it will be used for SPL. Signed-off-by: Lokesh Vutla --- arch/arm/dts/am437x-gp-evm-u-boot.dtsi | 38 ++ 1 file changed, 38 insertions(+) create mode 100644

Re: [U-Boot] [PATCH v2 4/4] configs: dra7x/am57x: Enable the SYSCON and REGMAP features

On Monday 13 February 2017 08:47 PM, Jean-Jacques Hiblot wrote: > This is required by the ti_qspi driver to get from the DTS the address of > the ctrl_mod_mmap register in SPL and in u-boot. > > Signed-off-by: Jean-Jacques Hiblot Tested-by: Lokesh Vutla

Re: [U-Boot] [PATCH v4 15/28] arm: socfpga: combine clrbits/setbits into a single clrsetbits

Hi Marek On Mon, Jan 23, 2017 at 11:58 AM, Marek Vasut wrote: > > On 01/10/2017 06:20 AM, Chee Tien Fong wrote: > > From: Tien Fong Chee > > > > There is no dependency on doing a separate clrbits first in the > > dwmac_deassert_reset function. Combine

Re: [U-Boot] [PATCH v2] arm: socfpga: fix issue with warm reset when CSEL is 0

On Wed, 2017-02-15 at 23:20 +0100, Marek Vasut wrote: > On 02/15/2017 10:48 PM, Dalon Westergreen wrote: > > > > On Wed, 2017-02-15 at 22:15 +0100, Marek Vasut wrote: > > > > > > On 02/14/2017 07:28 PM, Dalon Westergreen wrote: > > > > > > > > > > > > When CSEL=0x0 the socfpga bootrom does not

Re: [U-Boot] [linux-sunxi] Re: [PATCH v3 3/3] sunxi: add support for Lichee Pi Zero

On Thu, Feb 16, 2017 at 9:32 AM, André Przywara wrote: > On 14/02/17 07:36, Maxime Ripard wrote: >> On Mon, Feb 13, 2017 at 04:12:04PM +0800, Icenowy Zheng wrote: >>> >>> 2017年2月13日 15:17于 Maxime Ripard 写道： Hi, On Sat,

Re: [U-Boot] [PATCH 1/2] rsa: Fix build with OpenSSL 1.1.x

These version tests should be #if (OPENSSL_VERSION_NUMBER < 0x1010L) || defined(LIBRESSL_VERSION_NUMBER) or better yet have tests based on functionality rather than version. opensslv.h on OpenBSD-current/LibreSSL portable master has /* $OpenBSD: opensslv.h,v 1.39 2017/02/14 03:50:25 bcook

Re: [U-Boot] [PATCH v3 3/3] sunxi: add support for Lichee Pi Zero

On 14/02/17 07:36, Maxime Ripard wrote: > On Mon, Feb 13, 2017 at 04:12:04PM +0800, Icenowy Zheng wrote: >> >> 2017年2月13日 15:17于 Maxime Ripard 写道： >>> >>> Hi, >>> >>> On Sat, Feb 11, 2017 at 07:11:02PM +0800, Icenowy Zheng wrote: @@ -0,0 +1,13 @@

[U-Boot] [PATCH v4 12/13] sunxi: dts: add basic OrangePi PC 2 device tree file

The OrangePi PC 2 is a typical SBC with the 64-bit Allwinner H5 SoC. Create a new .dts file for it by including the (32-bit) H3 SoC .dtsi and changing the differing components accordingly. This is a preliminary device tree mostly for U-Boot's own sake, it is expected to be updated once the

[U-Boot] [PATCH v4 11/13] sunxi: introduce Allwinner H5 config option

The Allwinner H5 Soc is bascially an H3 with high SRAM and ARMv8 cores. As the peripherals and the pinmuxing are almost identical, we piggy back on the shared MACH_SUN8I_H3_H5 config symbol. Signed-off-by: Andre Przywara Acked-by: Maxime Ripard

[U-Boot] [PATCH v4 13/13] sunxi: configs: add basic OrangePi PC 2 defconfig

The OrangePi PC 2 is a typical SBC with the 64-bit Allwinner H5 SoC. Add a (64-bit only) defconfig defining the required options to build the U-Boot proper. Signed-off-by: Andre Przywara Acked-by: Maxime Ripard ---

[U-Boot] [PATCH v4 08/13] SPI: SPL: sunxi: fix 64-bit build

Addresses passed on to readl and writel are expected to be of the same size as a pointer. Change the parameter types of sunxi_spi0_read_data() to make the compiler happy and allow a warning-free aarch64 compile. Signed-off-by: Andre Przywara Reviewed-by: Simon Glass

[U-Boot] [PATCH v4 10/13] sunxi: prepare for sharing MACH_SUN8I_H3 config symbol

The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared

[U-Boot] [PATCH v4 09/13] sunxi: DRAM: add Allwinner H5 support

The DRAM controller in the Allwinner H5 SoC is again very similar to the one in the H3 and A64. Based on the existing socid parameter, add support for this controller by reusing the bulk of the code and only deviating where needed. These new bits set or cleared here and there have been mostly

[U-Boot] [PATCH v4 03/13] fsl: ls102x: remove redundant GENERIC_TIMER_CLK

Some Freescale boards used an extra version of the constant to hold the Generic Timer frequency. This can easily be covered by the now unified COUNTER_FREQUENCY constant, so remove this extra variable from those boards. Signed-off-by: Andre Przywara Reviewed-by: York Sun

[U-Boot] [PATCH v4 04/13] sunxi: simplify ACTLR.SMP bit set #ifdef

Instead of enumerating all SoC families that need that bit set, let's just express this more clearly: The SMP bits needs to be set on SMP capable ARMv7 CPUs. It's much easier in Kconfig to express it the other way round, so we use ! CPU_IS_UP and ! ARM64. Signed-off-by: Andre Przywara

[U-Boot] [PATCH v4 06/13] sunxi: Kconfig: introduce CONFIG_SUNXI_HIGH_SRAM

Traditionally Allwinner SoCs have their boot ROM mapped just below 4GB, while the first SRAM region is mapped at address 0. With the extended physical memory support of the A80 this was changed, so the BROM is now at address 0 and the SRAM region starts right behind this at 64KB. This

[U-Boot] [PATCH v4 05/13] sunxi: configs: merge sun9i and sun50i SPL memory definitions

For some reason we were pretty conservative when defining the maximum SPL size for the Allwinner A80(sun9i) SoC. According to the manual the SRAM A1 is even 40KB, but the BROM probably still has the 32 KiB load limit. For the sake of simplicity, merge the SPL memory definitions for the A64 and A80

[U-Boot] [PATCH v4 02/13] ARM: rename CONFIG_TIMER_CLK_FREQ to COUNTER_FREQUENCY

Many ARMv8 boards define a constant COUNTER_FREQUENCY to specify the frequency of the ARM Generic Timer (aka. arch timer). ARMv7 boards traditionally used CONFIG_TIMER_CLK_FREQ for the same purpose. It seems useful to unify them. Since there are less occurences of the latter version, lets convert

[U-Boot] [PATCH v4 07/13] sunxi: provide ARMv8 mem_map for every ARM64 board

Every armv8 board needs the memory map, so change the #ifdef to ARM64 to avoid enumerating every single board or SoC. Signed-off-by: Andre Przywara Acked-by: Maxime Ripard Reviewed-by: Jagan Teki ---

[U-Boot] [PATCH v4 00/13] sunxi: Allwinner H5 and OrangePi PC2 support

Hi, thanks for all the reviews and ACKs! Only minor changes this time, see the Changelog below. Cheers, Andre. -- This series introduces support for the Allwinner H5 SoC with four Cortex-A53 cores. The SoC's peripherals are very similar to the H3, although the cores and

[U-Boot] [PATCH v4 01/13] sunxi: fix ACTLR.SMP assembly routine

If we take the liberty to use register r0 to perform our bit set, we should be nice enough to tell the compiler about it. Add r0 to the clobber list to avoid potential mayhem. Signed-off-by: Andre Przywara Acked-by: Maxime Ripard

[U-Boot] Veyron-speedy u-boot

Hi Simon, I've tried porting u-boot to the veyron-speedy Chromebook, based upon the veyron-minnie patch. I've attached a patch with my changes to this email. However, when I boot, all I get is a black screen. So, I have some questions: 1. Does u-boot show output to the laptop's screen, or do I

Re: [U-Boot] [PATCH] sunxi: makes an invisible option for H3-like DRAM controllers

On 14/02/17 13:49, Icenowy Zheng wrote: > Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like > DesignWare DRAM controller, which do not have official free DRAM > initialization code, but can use modified dram_sun8i_h3.c. > > Add a invisible option for easier DRAM initialization code

Re: [U-Boot] [PATCH v5 2/6] spl: Add option to enable SPL Legacy image support

On Wed, Feb 15, 2017 at 01:45:47PM -0600, Andrew F. Davis wrote: > Add a Kconfig option that enables Legacy image support, this allows > boards to explicitly disable this, for instance when needed for > security reasons. > > Signed-off-by: Andrew F. Davis > Reviewed-by: Simon Glass

Re: [U-Boot] [PATCH v5 1/6] spl: Convert CONFIG_SPL_ABORT_ON_RAW_IMAGE into a positive option

On Wed, Feb 15, 2017 at 01:45:46PM -0600, Andrew F. Davis wrote: > CONFIG_SPL_ABORT_ON_RAW_IMAGE causes SPL to abort and move on when it > encounters RAW images, express this same functionality as a positive > option enabling support for RAW images: CONFIG_SPL_RAW_IMAGE_SUPPORT > > Also move

Re: [U-Boot] [PATCH v5 0/6] Allow disabling non-FIT image loading from SPL

On Wed, Feb 15, 2017 at 01:45:45PM -0600, Andrew F. Davis wrote: > Hello all, > > To address a needed feature brought up by Andreas[0], we need a way to > disable SPL from loading non-FIT images. > > The function spl_parse_image_header is common to all SPL loading paths >

Re: [U-Boot] [PATCH v2] driver: net: ldpaa: Update priv->phydev after free()

On Wed, Feb 15, 2017 at 9:26 AM, Ashish Kumar wrote: > From: Prabhakar Kushwaha > > Even after memory free of phydev, priv is still pointing to the > obsolete address. > So update priv->phydev as NULL after memory free. > > Signed-off-by:

Re: [U-Boot] [PATCH v2] armv7m: Add SysTick timer driver

Hi Phil, > -Original Message- > From: Phil Edworthy [mailto:phil.edwor...@renesas.com] > Sent: Monday, February 13, 2017 11:48 PM > To: Albert Aribaud > Cc: Tom Rini ; Vikas MANOCHA ; > Kamil Lulko

[U-Boot] [PATCH v2 10/10] armv8: layerscape: Update early MMU for DDR after initialization

In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun

[U-Boot] [PATCH v2 07/10] armv8: layerscape: Update MMU mapping with actual DDR size

Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun --- Changes in v2: None arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 42 +++-- 1 file changed, 40

[U-Boot] [PATCH v2 05/10] armv8: layerscape: Rewrite memory reservation

For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank

[U-Boot] [PATCH v2 00/10] Rewrite ARMv8 layerscape MMU

A recent debug revealed MMU for DDR shouldn't be enabled before DDR is initialized. Otherwise, a "normal memory" mapping may cause speculative access which may hang the system if accessing to DDR is not allowed at time. For Layerscape platforms, we have early MMU setup to speed up execution on

[U-Boot] [PATCH v2 09/10] armv8: mmu: Add a function to change mapping attributes

Function mmu_change_region_attr() is added to change existing mapping with updated PXN, UXN and memory type. This is a break-before-make process during which the mapping becomes fault (invalid) before final attributres are set. Signed-off-by: York Sun --- Changes in v2: None

[U-Boot] [PATCH v2 08/10] armv8: layerscape: Flush MMU tables after creattion

MMU tables should be flushed if current code runs with d-cache on. This applies to early MMU tables with SPL boot, and all final MMU tables. Signed-off-by: York Sun --- Changes in v2: None arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 9 + 1 file changed, 9 insertions(+)

[U-Boot] [PATCH v2 02/10] armv8: ls2080a: Move CONFIG_FSL_MC_ENET to Kconfig

Use Kconfig option instead of config macro in header file. Clean up existing usage. Signed-off-by: York Sun --- Changes in v2: None arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 8 include/configs/ls2080a_common.h | 1 - scripts/config_whitelist.txt

[U-Boot] [PATCH v2 04/10] efi: Add a hook to allow adding memory mapping

Instead of adding all memory banks, add a hook so individual SoC/board can has its own implementation. Signed-off-by: York Sun CC: Alexander Graf --- Changes in v2: Add change to efi mapping lib/efi_loader/efi_memory.c | 14 ++ 1 file changed,

[U-Boot] [PATCH v2 03/10] armv8: ls2080a: Move CONFIG_SYS_MC_RSV_MEM_ALIGN to Kconfig

Use Kconfig option instead of config macro in header file. Signed-off-by: York Sun --- Changes in v2: None arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 8 include/configs/ls2080a_common.h | 1 - scripts/config_whitelist.txt | 1 - 3 files

[U-Boot] [PATCH v2 06/10] driver: net: fsl-mc: Update calculation of MC RAM

Since the reserved RAM is tracked by gd->arch.resv_ram, calculation of MC memory blocks can be simplified. The MC RAM is guaranteed to be aligned by the reservation process. Signed-off-by: York Sun CC: Priyanka Jain --- Changes in v2: None

[U-Boot] [PATCH v2 01/10] armv8: Add global variable resv_ram

Use gd->arch.resv_ram to track reserved memory allocation. Signed-off-by: York Sun --- Changes in v2: None arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 ++ arch/arm/include/asm/global_data.h| 3 +++ cmd/bdinfo.c | 4 3 files

Re: [U-Boot] [PATCH v2] arm: socfpga: fix issue with warm reset when CSEL is 0

On 02/15/2017 10:48 PM, Dalon Westergreen wrote: > On Wed, 2017-02-15 at 22:15 +0100, Marek Vasut wrote: >> On 02/14/2017 07:28 PM, Dalon Westergreen wrote: >>> >>> When CSEL=0x0 the socfpga bootrom does not touch the clock >>> configuration for the device. This can lead to a boot failure >>> on

Re: [U-Boot] [PATCH 13/13] mips: jz47xx: Add Creator CI20 platform

On 02/15/2017 10:50 PM, Tom Rini wrote: > On Wed, Feb 15, 2017 at 09:46:38PM +0100, Marek Vasut wrote: >> On 02/15/2017 12:11 AM, Tom Rini wrote: >>> On Wed, Feb 15, 2017 at 12:03:32AM +0100, Marek Vasut wrote: On 02/14/2017 11:58 PM, Tom Rini wrote: > On Sun, Feb 12, 2017 at 12:52:45PM

Re: [U-Boot] [PATCH 4/9] armv8: layerscape: Rewrite memory reservation

On 15/02/2017 19:52, york sun wrote: Reduce CC list. On 02/14/2017 11:56 AM, Alexander Graf wrote: On 14/02/2017 18:38, york sun wrote: On 02/14/2017 09:00 AM, york@nxp.com wrote: On 02/14/2017 07:31 AM, Alexander Graf wrote: On 14/02/2017 04:45, York Sun wrote: For ARMv8

Re: [U-Boot] [PATCH 13/13] mips: jz47xx: Add Creator CI20 platform

On Wed, Feb 15, 2017 at 09:46:38PM +0100, Marek Vasut wrote: > On 02/15/2017 12:11 AM, Tom Rini wrote: > > On Wed, Feb 15, 2017 at 12:03:32AM +0100, Marek Vasut wrote: > >> On 02/14/2017 11:58 PM, Tom Rini wrote: > >>> On Sun, Feb 12, 2017 at 12:52:45PM +0100, Andreas Färber wrote: > Hi

Re: [U-Boot] [PATCH v2] arm: socfpga: fix issue with warm reset when CSEL is 0

On Wed, 2017-02-15 at 22:15 +0100, Marek Vasut wrote: > On 02/14/2017 07:28 PM, Dalon Westergreen wrote: > > > > When CSEL=0x0 the socfpga bootrom does not touch the clock > > configuration for the device.  This can lead to a boot failure > > on warm resets.  To address this, the bootrom is

Re: [U-Boot] [PATCH v2] arm: socfpga: fix issue with warm reset when CSEL is 0

On 02/14/2017 07:28 PM, Dalon Westergreen wrote: > When CSEL=0x0 the socfpga bootrom does not touch the clock > configuration for the device. This can lead to a boot failure > on warm resets. To address this, the bootrom is configured to > run a bit of code in the last 4KB of onchip ram on a

Re: [U-Boot] [PATCH 13/13] mips: jz47xx: Add Creator CI20 platform

On 02/15/2017 12:11 AM, Tom Rini wrote: > On Wed, Feb 15, 2017 at 12:03:32AM +0100, Marek Vasut wrote: >> On 02/14/2017 11:58 PM, Tom Rini wrote: >>> On Sun, Feb 12, 2017 at 12:52:45PM +0100, Andreas Färber wrote: Hi Marek, Am 01.12.2016 um 02:06 schrieb Marek Vasut: > From:

Re: [U-Boot] [PATCH v2] arm: socfpga: fix issue with warm reset when CSEL is 0

On 02/15/2017 07:56 AM, Chin Liang See wrote: > On Sel, 2017-02-14 at 10:28 -0800, Dalon Westergreen wrote: >> When CSEL=0x0 the socfpga bootrom does not touch the clock >> configuration for the device. This can lead to a boot failure >> on warm resets. To address this, the bootrom is configured

Re: [U-Boot] [PATCH 1/1] Secure Boot: Set NPSWA_EN bit for SNVS state transition to happen in EL2.

On 02/15/2017 04:23 AM, Udit Agarwal wrote: > For Layerscape chasis Gen 3 based platforms, during PPA execution > exception level transition happens from EL3 to EL2. While in EL2 state > SNVS state doesnot changes from secure to non secure state in > case of ESBC failure. > > So to enable the SNVS

Re: [U-Boot] [PATCH 4/9] armv8: layerscape: Rewrite memory reservation

Reduce CC list. On 02/14/2017 11:56 AM, Alexander Graf wrote: > > > On 14/02/2017 18:38, york sun wrote: >> On 02/14/2017 09:00 AM, york@nxp.com wrote: >>> On 02/14/2017 07:31 AM, Alexander Graf wrote: On 14/02/2017 04:45, York Sun wrote: > For ARMv8 Layerscape SoCs, secure

[U-Boot] [PATCH v5 3/6] ARM: AM335x: Disable non-FIT based image loading for HS devices

Disable support for loading non-FIT images for AM335x platforms using the high-security (HS) device variant. Signed-off-by: Andrew F. Davis Reviewed-by: Simon Glass --- configs/am335x_hs_evm_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git

[U-Boot] [PATCH v5 2/6] spl: Add option to enable SPL Legacy image support

Add a Kconfig option that enables Legacy image support, this allows boards to explicitly disable this, for instance when needed for security reasons. Signed-off-by: Andrew F. Davis Reviewed-by: Simon Glass --- Kconfig | 8 common/spl/spl.c |

[U-Boot] [PATCH v5 0/6] Allow disabling non-FIT image loading from SPL

Hello all, To address a needed feature brought up by Andreas[0], we need a way to disable SPL from loading non-FIT images. The function spl_parse_image_header is common to all SPL loading paths (common/spl/spl_(nand|net|nor|etc..)) so we add the check here. This version of the series is a bit

[U-Boot] [PATCH v5 5/6] ARM: AM57xx: Disable non-FIT based image loading for HS devices

Disable support for loading non-FIT images for AM57xx platforms using the high-security (HS) device variant. Signed-off-by: Andrew F. Davis Reviewed-by: Simon Glass --- configs/am57xx_hs_evm_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git

[U-Boot] [PATCH v5 1/6] spl: Convert CONFIG_SPL_ABORT_ON_RAW_IMAGE into a positive option

CONFIG_SPL_ABORT_ON_RAW_IMAGE causes SPL to abort and move on when it encounters RAW images, express this same functionality as a positive option enabling support for RAW images: CONFIG_SPL_RAW_IMAGE_SUPPORT Also move uses of this to defconfigs. Signed-off-by: Andrew F. Davis ---

[U-Boot] [PATCH v5 4/6] ARM: AM43xx: Disable non-FIT based image loading for HS devices

Disable support for loading non-FIT images for AM43xx platforms using the high-security (HS) device variant. Signed-off-by: Andrew F. Davis Reviewed-by: Simon Glass --- configs/am43xx_hs_evm_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git

[U-Boot] [PATCH v5 6/6] ARM: DRA7xx: Disable non-FIT based image loading for HS devices

Disable support for loading non-FIT images for DRA7xx platforms using the high-security (HS) device variant. Signed-off-by: Andrew F. Davis Reviewed-by: Simon Glass --- configs/dra7xx_hs_evm_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git

Re: [U-Boot] [PATCH v4 1/6] spl: Convert CONFIG_SPL_ABORT_ON_RAW_IMAGE into a positive option

On 02/14/2017 03:04 PM, Tom Rini wrote: > On Tue, Feb 14, 2017 at 02:32:42PM -0600, Andrew F. Davis wrote: >> On 02/14/2017 02:15 PM, Tom Rini wrote: >>> On Mon, Feb 13, 2017 at 12:47:36PM -0600, Andrew F. Davis wrote: >>> CONFIG_SPL_ABORT_ON_RAW_IMAGE causes SPL to abort and move on when it

Re: [U-Boot] [PATCH] ARM: DRA7xx: Fix memory allocation overflow

On Wed, Feb 15, 2017 at 09:16:53AM -0600, Andrew F. Davis wrote: > When using early malloc the allocated memory can overflow into the SRAM > scratch space, move NON_SECURE_SRAM_IMG_END down a bit to allow more > dynamic allocation at the expense of a slightly smaller maximum image > size. > >

Re: [U-Boot] [PATCH 07/10] mvebu: a37xx: Add init for ESPRESSBin Topaz switch

On Wed, Feb 15, 2017 at 9:32 AM, Konstantin Porotchkin wrote: > > > On 02/15/2017 11:07 AM, Konstantin Porotchkin wrote: >> >> Hi, Joe, >> >> On 02/14/2017 07:17 PM, Joe Hershberger wrote: >>> >>> On Tue, Feb 14, 2017 at 6:32 AM, Stefan Roese wrote: >>> > (added

Re: [U-Boot] arm: cache: misaligned operation with fastboot

On Wed, Feb 15, 2017 at 2:04 PM, Gary Bisson wrote: > Hi, > > I've been testing fastboot to flash a sparse image on a i.MX6Q platform > (Nitrogen6x) with U-Boot v2017.01. > > This test shows a lot of "misaligned operation" traces: > => fastboot 0 > Starting

Re: [U-Boot] [PATCH 1/3] mx6sx: udoo_neo: Define the default serial console

Hi Peter, 2017-02-14 11:10 GMT-02:00 Peter Robinson : > From: Peter Robinson > Date: Tue, Feb 14, 2017 at 11:10 AM > Subject: [U-Boot] [PATCH 1/3] mx6sx: udoo_neo: Define the default serial > console > To: Breno Lima , Francesco

[U-Boot] [PATCH] sunxi: Add defconfig for Allwinner A23 EVB

This enables the support for the Allwinner A23 Evaluation Board (EVB), that already had a device tree (from Linux) but no defconfig. This board has an AXP223 PMIC, some NAND, Audio out and in plugs, an accelerometer and light sensor, as well as a USB HSIC hub and a USB OTG mini-USB connector. It

[U-Boot] a question about the source of uboot(for armv8).

Hi Haikun Wang, I have a question about the source of uboot. http://lists.denx.de/pipermail/u-boot/2015-June/217446.html >u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; >val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4); The question is this, why does DCFG_RCWSR13 device by 4.

[U-Boot] arm: cache: misaligned operation with fastboot

Hi, I've been testing fastboot to flash a sparse image on a i.MX6Q platform (Nitrogen6x) with U-Boot v2017.01. This test shows a lot of "misaligned operation" traces: => fastboot 0 Starting download of 415679660 bytes ... downloading of 415679660 bytes finished Flashing sparse image at offset

Re: [U-Boot] [PATCH 07/10] mvebu: a37xx: Add init for ESPRESSBin Topaz switch

On 02/15/2017 11:07 AM, Konstantin Porotchkin wrote: Hi, Joe, On 02/14/2017 07:17 PM, Joe Hershberger wrote: On Tue, Feb 14, 2017 at 6:32 AM, Stefan Roese wrote: > (added Joe to Cc as network custodian) > > > On 14.02.2017 13:13, Konstantin Porotchkin wrote: >> >> Hi, Stefan,

[U-Boot] [PATCH 2/3] armv8: ls1088ardb: Add support for LS1088ARDB platform

LS1088A is an ARMv8 implementation. The LS1088ARDB is an evaluatoin platform that supports the LS1088A family SoCs. This patch add basic support of the platform. Signed-off-by: Alison Wang Signed-off-by: Prabhakar Kushwaha Signed-off-by: Ashish

[U-Boot] [PATCH] driver: net: ldpaa: Update priv->phydev after free()

From: Prabhakar Kushwaha Even after memory free of phydev, priv is still pointing to the obsolete address. So update priv->phydev as NULL after memory free. Signed-off-by: Prabhakar Kushwaha --- drivers/net/ldpaa_eth/ldpaa_eth.c | 4 +++-

[U-Boot] [PATCH 1/3] armv8: ls1088a: Add NXP LS1088A SoC support

The QorIQ LS1088A processor is built on the Layerscape architecture combining eight ARM A53 processor cores with advanced, high-performance datapath acceleration and networks, peripheral interfaces required for networking, wireless infrastructure, and general-purpose

[U-Boot] [PATCH 3/3] armv8: ls1088aqds: Add support of LS1088AQDS

This patch add support of LS1088AQDS platform. The LS1088A QorIQTM Development System (QDS) is a high-performance computing, evaluation, and development platform that supports the LS1088A QorIQ Architecture processor. Signed-off-by: Prabhakar Kushwaha Signed-off-by:

[U-Boot] [PATCH v2] armv8:fsl-layerscape: Avoid RCWSR28 register hard-coding

From: Prabhakar Kushwaha SerDes information is not necessary to be present in RCWSR29 register. It may vary from SoC to SoC. So Avoid RCWSR28 register hard-coding. Signed-off-by: Prabhakar Kushwaha Signed-off-by: Ashish Kumar

[U-Boot] [PATCH v2] driver: net: ldpaa: Update priv->phydev after free()

From: Prabhakar Kushwaha Even after memory free of phydev, priv is still pointing to the obsolete address. So update priv->phydev as NULL after memory free. Signed-off-by: Prabhakar Kushwaha Signed-off-by: Ashish Kumar

[U-Boot] [PATCH] ARM: DRA7xx: Fix memory allocation overflow

When using early malloc the allocated memory can overflow into the SRAM scratch space, move NON_SECURE_SRAM_IMG_END down a bit to allow more dynamic allocation at the expense of a slightly smaller maximum image size. Signed-off-by: Andrew F. Davis Reviewed-by: Lokesh Vutla

[U-Boot] [PATCH v2] arm: fsl-layerscape: Move QSGMII wriop_init to SoC file

From: Prabhakar Kushwaha MAC number used per QSGMII is not fixed. It may wary from SoC to SoC. So move QSGMII wriop_init_dpmac() to SoC file. Signed-off-by: Prabhakar Kushwaha Signed-off-by: Ashish Kumar --- v2:

[U-Boot] [PATCH 1/1] Secure Boot: Set NPSWA_EN bit for SNVS state transition to happen in EL2.

For Layerscape chasis Gen 3 based platforms, during PPA execution exception level transition happens from EL3 to EL2. While in EL2 state SNVS state doesnot changes from secure to non secure state in case of ESBC failure. So to enable the SNVS transition in EL2 state, NPSWA_EN bit has to be set

Re: [U-Boot] [PATCH v2 1/6] arm: am57xx: reintroduce the CONFIG_AM57XX symbol

On 02/15/2017 01:30 PM, Roger Quadros wrote: On 15/02/17 10:24, Roger Quadros wrote: On 14/02/17 22:12, Tom Rini wrote: On Tue, Feb 14, 2017 at 01:26:24PM -0600, Nishanth Menon wrote: On 02/14/2017 01:20 PM, Tom Rini wrote: On Tue, Feb 14, 2017 at 01:18:20PM -0600, menon.nisha...@gmail.com

Re: [U-Boot] Simple Malloc Breaks omap3_logic

On Tue, Feb 14, 2017 at 4:07 PM, Tom Rini wrote: > On Tue, Feb 14, 2017 at 03:56:43PM -0600, Adam Ford wrote: >> On Feb 14, 2017 3:10 PM, "Tom Rini" wrote: >> >> On Tue, Feb 14, 2017 at 03:03:44PM -0600, Adam Ford wrote: >> >> > Tom, >> > >> > I noticed

[U-Boot] [PATCH v4] tools: omapimage: Fix size in header

The size field in GP header that is expected by ROM is size of the image + size of the header. But omapimage generates a gp header only with size of the image as size field. Fix it Signed-off-by: Lokesh Vutla --- tools/omapimage.c | 2 +- 1 file changed, 1 insertion(+), 1

Re: [U-Boot] [PATCH v3 1/5] tools: omapimage: Fix size in header

On Wed, Feb 15, 2017 at 06:02:37PM +0530, Lokesh Vutla wrote: > Hi Tom, > > On Friday 10 February 2017 08:37 PM, Lokesh Vutla wrote: > > The size field in GP header that is expected by ROM is size of the > > image + size of the header. But omapimage generates a gp header > > only with size of the

Re: [U-Boot] [PATCH v3 1/5] tools: omapimage: Fix size in header

Hi Tom, On Friday 10 February 2017 08:37 PM, Lokesh Vutla wrote: > The size field in GP header that is expected by ROM is size of the > image + size of the header. But omapimage generates a gp header > only with size of the image as size field. Fix it Unfortunately this is not ture for

Re: [U-Boot] [PATCH v2] splash: fix splash source flags check

Hi, On 01/16/2017 08:36 PM, Michael Nazzareno Trimarchi wrote: > Hi > > > > On 14 Jan 2017 3:54 a.m., "Anatolij Gustschin" wrote: > > From: "tomas.me...@vaisala.com" > > SPLASH_STORAGE_RAW is defined as 0, so a check against & will > never be true.

Re: [U-Boot] [PATCH v2 1/6] arm: am57xx: reintroduce the CONFIG_AM57XX symbol

On 15/02/17 10:24, Roger Quadros wrote: > On 14/02/17 22:12, Tom Rini wrote: >> On Tue, Feb 14, 2017 at 01:26:24PM -0600, Nishanth Menon wrote: >>> On 02/14/2017 01:20 PM, Tom Rini wrote: On Tue, Feb 14, 2017 at 01:18:20PM -0600, menon.nisha...@gmail.com wrote: > On Mon, Feb 13, 2017 at

Re: [U-Boot] [PATCH v2] spl: net: Add FIT image support over network boot

Hi, On Wednesday 08 February 2017 11:21 PM, Davis, Andrew wrote: > FIT support in the net boot case is much like the RAM boot case in that > we load our image to "load_addr" and pass a dummy read function into > "spl_load_simple_fit()". As the load address is no longer hard-coded to > the final

Re: [U-Boot] [PATCH v1 1/3] x86: Introduce INTEL_MID quirk option

On Wed, 2017-02-15 at 18:09 +0800, Bin Meng wrote: > Hi Andy, > > On Wed, Feb 15, 2017 at 5:50 PM, Andy Shevchenko > wrote: > > On Wed, 2017-02-15 at 11:00 +0800, Bin Meng wrote: > > > On Tue, Feb 14, 2017 at 10:47 PM, Andy Shevchenko > > >

Re: [U-Boot] [PATCH v1 1/3] x86: Introduce INTEL_MID quirk option

Hi Andy, On Wed, Feb 15, 2017 at 5:50 PM, Andy Shevchenko wrote: > On Wed, 2017-02-15 at 11:00 +0800, Bin Meng wrote: >> Hi Andy, >> >> On Tue, Feb 14, 2017 at 10:47 PM, Andy Shevchenko >> wrote: >> > Intel Mobile Internet

Re: [U-Boot] [PATCH v1 3/3] x86: Intel MID platforms has no microcode update

On Wed, 2017-02-15 at 11:10 +0800, Bin Meng wrote: > Hi Andy, > > On Tue, Feb 14, 2017 at 10:47 PM, Andy Shevchenko > wrote: > > There is no microcode update available for SoCs used on Intel MID > > platforms. > > > > Use conditional to bypass it. > > > >

Re: [U-Boot] [PATCH v1 1/3] x86: Introduce INTEL_MID quirk option

On Wed, 2017-02-15 at 11:00 +0800, Bin Meng wrote: > Hi Andy, > > On Tue, Feb 14, 2017 at 10:47 PM, Andy Shevchenko > wrote: > > Intel Mobile Internet Device (MID) platforms have special treatment > > in > > some cases, such as CPU enumeration or boot

Re: [U-Boot] [PATCH 04/10] arm64: a37xx: Handle pin controls in early board init

On 02/14/2017 02:25 PM, Konstantin Porotchkin wrote: On 2/14/2017 14:21, Stefan Roese wrote: On 14.02.2017 13:07, Konstantin Porotchkin wrote: Hi, Stefan, On 2/14/2017 13:43, Stefan Roese wrote: Hi Kosta, On 13.02.2017 14:38, kos...@marvell.com wrote: From: Konstantin Porotchkin

Re: [U-Boot] [PATCH] env_mmc: Allow SPL to use any MMC device to load/save the environment

On 14/02/2017 19:52, Tom Rini wrote: On Tue, Feb 14, 2017 at 02:16:13PM +0100, Jean-Jacques Hiblot wrote: Hi Tom, Have you had a chance to look at the patch below? It looks fine but was too close to the release window (given the potential impact) to merge. Thanks! Ok Thank you for the

Re: [U-Boot] [PATCH 07/10] mvebu: a37xx: Add init for ESPRESSBin Topaz switch

Hi, Joe, On 02/14/2017 07:17 PM, Joe Hershberger wrote: On Tue, Feb 14, 2017 at 6:32 AM, Stefan Roese wrote: > (added Joe to Cc as network custodian) > > > On 14.02.2017 13:13, Konstantin Porotchkin wrote: >> >> Hi, Stefan, >> >> On 2/14/2017 13:49, Stefan Roese wrote: >>> >>> Hi

Re: [U-Boot] Assigning u-boot environment variables from memory

On Tue, 14 Feb 2017 14:27:30 -0700 (MST) brendan wrote: > I am storing some information regarding my board within EEPROM (in > memory after I use the >eeprom read command) and I was wondering if > it was possible for me to somehow read from memory and store the >

Re: [U-Boot] [PATCH v2 1/6] arm: am57xx: reintroduce the CONFIG_AM57XX symbol

On 14/02/17 22:12, Tom Rini wrote: > On Tue, Feb 14, 2017 at 01:26:24PM -0600, Nishanth Menon wrote: >> On 02/14/2017 01:20 PM, Tom Rini wrote: >>> On Tue, Feb 14, 2017 at 01:18:20PM -0600, menon.nisha...@gmail.com wrote: On Mon, Feb 13, 2017 at 7:27 AM, Tom Rini wrote: