On 12/07/21 9:53 pm, Paul Barker wrote:
> On Thu, 17 Jun 2021 12:27:55 +
> Tom Rini wrote:
>
>> On Thu, Jun 17, 2021 at 11:31:56AM +0100, Paul Barker wrote:
>>> On Thu, 17 Jun 2021 11:05:46 +0100
>>> Peter Robinson wrote:
>>>
On Thu, Jun 17, 2021 at 10:03 AM Paul Barker
wrote:
Hi Fabio,
On 12.07.21 23:31, Fabio Estevam wrote:
Hi Patrick,
On Mon, Jul 12, 2021 at 11:27 AM Patrick Wildt wrote:
Am Sun, Feb 21, 2021 at 08:26:21AM -0800 schrieb Ye Li:
Add the USB PHY driver for i.MX8MQ to work with DWC3 USB controller.
Signed-off-by: Ye Li
Reviewed-by: Patrick
Hi Simon,
> > >
[...]
> > > Yes, but I hope you see my point, that you have added a new interface.
> > > It is definitely better than adding a new driver and duplicating all
> > > the code, but it is still one more copy and in fact, the code is
> > > duplicated.
> > >
> >
> > I get the point but
Hi,
On 7/12/21 7:40 PM, Jorge Ramirez-Ortiz, Foundries wrote:
> hi Michal,
>
> Would you have some sample/reference code to generate a SPL boot image
> using zynqmpbif instead of zynqmpimage? I cant find any documentation
> and I see no option to enable it (I was expecting to find some config
>
Dear Tom,
The following changes since commit 490101a5e5df65238b900b21b81361bc4b13da2e:
Merge branch 'master' of
https://source.denx.de/u-boot/custodians/u-boot-sunxi (2021-07-09
21:08:52 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-efi.git
Hi Jaehoon,
Indeed! I did run the test using the u-boot-master (2021.07 version) source
tree.
Thanks,
Tony
On Mon, Jul 12, 2021 at 4:59 PM Jaehoon Chung
wrote:
> On 7/12/21 2:11 PM, Tony Dinh wrote:
> > In reference to:
> >
>
On Tue, Jul 13, 2021 at 12:01 AM Alex G. wrote:
>
> On 7/12/21 10:15 AM, Tom Rini wrote:
> > On Mon, Jul 12, 2021 at 01:36:14PM +0800, Bin Meng wrote:
> >> On Mon, Jul 12, 2021 at 1:21 PM Reuben Dowle wrote:
> >>>
> >>> I submitted an almost identical patch. See
> >>>
On Mon, Jul 12, 2021 at 11:15 PM Tom Rini wrote:
>
> On Mon, Jul 12, 2021 at 01:36:14PM +0800, Bin Meng wrote:
> > On Mon, Jul 12, 2021 at 1:21 PM Reuben Dowle wrote:
> > >
> > > I submitted an almost identical patch. See
> > >
Am Donnerstag, den 17.06.2021, 18:09 +0200 schrieb Reto Schneider:
> From: Reto Schneider
>
> This commit updates the default config with the values that will
> be used soon on the MediaTek MT7688 based GARDENA smart gateway.
>
> CONFIG_SPL_SYS_MALLOC_F_LEN had to be increased due to the more
>
Hi Simon,
Am Samstag, den 10.07.2021, 18:00 -0600 schrieb Simon Glass:
> () Hi Daniel,
>
> On Tue, 6 Jul 2021 at 08:22, Daniel Schwierzeck
> wrote:
> > As almost all peripherals are connected via PCI dependent on the
> > used core card, PCI setup is always required. Thus run pci_init()
> >
Hi all,
Sorry if this is the wrong list for this.
I have 2 custom images (elf or bin) stored in predefined addresses in flash
that are to be loaded based on some criteria I can test for on bootup.
Can someone please suggest a method to programmatically launch either image
using uboot's tools
On 7/12/21 2:11 PM, Tony Dinh wrote:
> In reference to:
> https://protect2.fireeye.com/v1/url?k=1452a2ce-4bc99bdf-14532981-0cc47a31cdbc-34fa0f17adf3f490=1=2aa912e1-bdc3-418f-872f-8870c46bcb15=https%3A%2F%2Flists.denx.de%2Fpipermail%2Fu-boot%2F2021-April%2F446664.html
>
AFAIK, Those patchset had
Am 12. Juli 2021 21:43:53 MESZ schrieb Simon Glass :
>Hi Heinrich,
>
>On Mon, 12 Jul 2021 at 13:19, Heinrich Schuchardt
>wrote:
>>
>> On 7/12/21 8:22 PM, Ilias Apalodimas wrote:
>> > Hi Simon,
>> > On Sat, Jul 10, 2021 at 06:00:59PM -0600, Simon Glass wrote:
>> >> Hi Ilias,
>> >>
>> >> On Wed, 7
Hi Patrick,
On Mon, Jul 12, 2021 at 11:27 AM Patrick Wildt wrote:
>
> Am Sun, Feb 21, 2021 at 08:26:21AM -0800 schrieb Ye Li:
> > Add the USB PHY driver for i.MX8MQ to work with DWC3 USB controller.
> >
> > Signed-off-by: Ye Li
>
> Reviewed-by: Patrick Wildt
> Tested-by: Patrick Wildt
It
On Mon, Jul 12, 2021 at 12:44 PM Simon Glass wrote:
>
> Hi Tim,
>
> On Mon, 12 Jul 2021 at 10:42, Tim Harvey wrote:
> >
> > On Sat, Jul 10, 2021 at 5:23 AM Heiko Schocher wrote:
> > >
> > > Hello Tim,
> > >
> > > On 09.07.21 16:47, Tim Harvey wrote:
> > > > On Wed, Jul 7, 2021 at 5:58 AM Teresa
These device trees are updated to match the versions in Linux 5.13.1.
The tick-timer entry in am335x-bone-common.dtsi is preserved.
Signed-off-by: Paul Barker
---
arch/arm/dts/am335x-bone-common.dtsi | 185 +-
arch/arm/dts/am335x-bone.dts | 7 +-
This device tree is imported from Linux 5.13.1 and enabled via the
am335x board file and the am335x evm defconfig.
Signed-off-by: Paul Barker
---
arch/arm/dts/Makefile| 1 +
arch/arm/dts/am335x-sancloud-bbe.dts | 137 +++
board/ti/am335x/board.c
The SanCloud BeagleBone Enhanced (BBE) includes a Gigabit Ethernet PHY.
Signed-off-by: Paul Barker
---
configs/am335x_evm_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index dcda15e6bf..1c8093ae6a 100644
---
The function board_is_bone_lt() returns true for the BeagleBone Green,
the BeagleBone Enhanced and the BeagleBone Black. Therefore when
selecting which devicetree to use we must ensure that the more specific
functions board_is_bbg1() and board_is_bben() are checked first
otherwise all three
These headers are updated to match the versions in Linux 5.13.1.
Signed-off-by: Paul Barker
---
include/dt-bindings/pinctrl/am33xx.h | 131 ++-
include/dt-bindings/pinctrl/omap.h | 11 +--
2 files changed, 135 insertions(+), 7 deletions(-)
diff --git
This updated patch series takes the approach of copying the device trees
for the BeagleBone Black, BeagleBone Green & BeagleBone enhanced from
the latest stable Linux kernel (v5.13.1). To support this we also need
to port over a couple of changes to the relevant dt-bindings headers.
I considered
Hi Alex,
On Mon, 12 Jul 2021 at 10:01, Alex G. wrote:
>
> On 7/12/21 10:15 AM, Tom Rini wrote:
> > On Mon, Jul 12, 2021 at 01:36:14PM +0800, Bin Meng wrote:
> >> On Mon, Jul 12, 2021 at 1:21 PM Reuben Dowle wrote:
> >>>
> >>> I submitted an almost identical patch. See
> >>>
Hi Heinrich,
On Mon, 12 Jul 2021 at 13:19, Heinrich Schuchardt wrote:
>
> On 7/12/21 8:22 PM, Ilias Apalodimas wrote:
> > Hi Simon,
> > On Sat, Jul 10, 2021 at 06:00:59PM -0600, Simon Glass wrote:
> >> Hi Ilias,
> >>
> >> On Wed, 7 Jul 2021 at 10:26, Ilias Apalodimas
> >> wrote:
> >>>
> >>> Add
Hi Tim,
On Mon, 12 Jul 2021 at 10:42, Tim Harvey wrote:
>
> On Sat, Jul 10, 2021 at 5:23 AM Heiko Schocher wrote:
> >
> > Hello Tim,
> >
> > On 09.07.21 16:47, Tim Harvey wrote:
> > > On Wed, Jul 7, 2021 at 5:58 AM Teresa Remmet wrote:
> > >>
> > >> Factor out the common node settings for
Hi Ilias,
On Mon, 12 Jul 2021 at 08:03, Ilias Apalodimas
wrote:
>
> > > > > TPM_STS_SELF_TEST_DONE = 1 << 2,
>
> [...]
>
> > > > > TPM_STS_RESPONSE_RETRY = 1 << 1,
> > > > > + TPM_STS_READ_ZERO = 0x23
> > > >
> > > > Does this below in
Hi Ilias,
On Mon, 12 Jul 2021 at 12:22, Ilias Apalodimas
wrote:
>
> Hi Simon,
> On Sat, Jul 10, 2021 at 06:00:59PM -0600, Simon Glass wrote:
> > Hi Ilias,
> >
> > On Wed, 7 Jul 2021 at 10:26, Ilias Apalodimas
> > wrote:
> > >
> > > Add support for devices that expose a TPMv2 though MMIO.
> > >
On 7/12/21 8:22 PM, Ilias Apalodimas wrote:
Hi Simon,
On Sat, Jul 10, 2021 at 06:00:59PM -0600, Simon Glass wrote:
Hi Ilias,
On Wed, 7 Jul 2021 at 10:26, Ilias Apalodimas
wrote:
Add support for devices that expose a TPMv2 though MMIO.
Apart from those devices, we can use the driver in our
Hi Simon,
On Sat, Jul 10, 2021 at 06:00:59PM -0600, Simon Glass wrote:
> Hi Ilias,
>
> On Wed, 7 Jul 2021 at 10:26, Ilias Apalodimas
> wrote:
> >
> > Add support for devices that expose a TPMv2 though MMIO.
> > Apart from those devices, we can use the driver in our QEMU setups and
> > test TPM
Acked-by: Ilias Apalodimas
On Mon, 12 Jul 2021 at 20:40, Heinrich Schuchardt wrote:
>
> On 7/12/21 11:05 AM, Masami Hiramatsu wrote:
> > Fix find_boot_device() to set bootdev_root if it finds the
> > bootdev from BootNext. Currently it sets the bootdev_root only
> > when it finds bootdev from
hi Michal,
Would you have some sample/reference code to generate a SPL boot image
using zynqmpbif instead of zynqmpimage? I cant find any documentation
and I see no option to enable it (I was expecting to find some config
in Makefile.spl but I see none).
What is the expected way of building
On 7/12/21 11:05 AM, Masami Hiramatsu wrote:
Fix find_boot_device() to set bootdev_root if it finds the
bootdev from BootNext. Currently it sets the bootdev_root only
when it finds bootdev from BootOrder.
Fixes: c74cd8bd08d1 ("efi_loader: capsule: add capsule_on_disk support")
Signed-off-by:
On Sat, Jul 10, 2021 at 5:23 AM Heiko Schocher wrote:
>
> Hello Tim,
>
> On 09.07.21 16:47, Tim Harvey wrote:
> > On Wed, Jul 7, 2021 at 5:58 AM Teresa Remmet wrote:
> >>
> >> Factor out the common node settings for dm-spl and dm-pre-reloc
> >> and move them to imx8mp-u-boot.dtsi
> >>
> >>
This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it. As this is also the last in family remove the related
support as well.
Cc: Angelo Durgehello
Signed-off-by: Tom Rini
---
arch/m68k/Kconfig | 15 -
arch/m68k/Makefile
This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it. As this is also the last in family remove the related
support as well.
Cc: Angelo Durgehello
Cc: TsiChung Liew
Signed-off-by: Tom Rini
---
arch/m68k/Kconfig | 9 -
arch/m68k/dts/M52277EVB.dts
This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.
Cc: Angelo Durgehello
Signed-off-by: Tom Rini
---
arch/m68k/Kconfig | 5 -
arch/m68k/dts/M54418TWR.dts | 34 ---
arch/m68k/dts/M54418TWR_nand_mii.dts | 34
This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.
Cc: Angelo Durgehello
Cc: TsiChung Liew
Signed-off-by: Tom Rini
---
arch/m68k/Kconfig | 9 -
arch/m68k/cpu/mcf5445x/speed.c| 19 -
arch/m68k/dts/M54455EVB.dts |
As this platform already enables CONFIG_DM and CONFIG_OF_CONTROL,
migrating to DM_USB and DM_SPI_FLASH is just a matter of enabling the
correct options.
Cc: Gregory CLEMENT
u-boot@lists.denx.de (open list)
Reported-by: Marek Behun
Signed-off-by: Tom Rini
---
Aside, the MAINTAINERS entry still
On Thu, 17 Jun 2021 12:27:55 +
Tom Rini wrote:
> On Thu, Jun 17, 2021 at 11:31:56AM +0100, Paul Barker wrote:
> > On Thu, 17 Jun 2021 11:05:46 +0100
> > Peter Robinson wrote:
> >
> > > On Thu, Jun 17, 2021 at 10:03 AM Paul Barker
> > > wrote:
> > > >
> > > > Configuration which is shared
On 7/12/21 6:02 PM, Tom Rini wrote:
On Mon, Jul 12, 2021 at 05:51:29PM +0200, Marek Vasut wrote:
On 7/12/21 5:43 PM, Tom Rini wrote:
On Mon, Jul 12, 2021 at 05:38:33PM +0200, Marek Vasut wrote:
On 7/12/21 5:15 PM, Tom Rini wrote:
On Mon, Jul 12, 2021 at 01:36:14PM +0800, Bin Meng wrote:
On
On Mon 2021-07-12 @ 07:54:44 AM, Peter Robinson wrote:
> On Tue, Jul 6, 2021 at 8:03 AM Trevor Woerner wrote:
> >
> > Hi,
> >
> > I was hoping that one day support would be added for the rockchip rock960c
> > board (from the 96boards series,
> > https://www.96boards.org/product/rock960c/).
> >
On Sat, Jul 10, 2021 at 5:24 AM Heiko Schocher wrote:
>
> Hi Tim, Stefano,
>
> On 10.07.21 11:14, Stefano Babic wrote:
> > Hi Tim,
> >
> > On 10.07.21 02:05, Tim Harvey wrote:
> >> Greetings,
> >>
> >> Has anyone successfully used secure boot with IMX8M Mini or other
> >> IMX8M? Peng's recent
On Mon, Jul 12, 2021 at 05:51:29PM +0200, Marek Vasut wrote:
> On 7/12/21 5:43 PM, Tom Rini wrote:
> > On Mon, Jul 12, 2021 at 05:38:33PM +0200, Marek Vasut wrote:
> > > On 7/12/21 5:15 PM, Tom Rini wrote:
> > > > On Mon, Jul 12, 2021 at 01:36:14PM +0800, Bin Meng wrote:
> > > > > On Mon, Jul 12,
On 7/12/21 10:15 AM, Tom Rini wrote:
On Mon, Jul 12, 2021 at 01:36:14PM +0800, Bin Meng wrote:
On Mon, Jul 12, 2021 at 1:21 PM Reuben Dowle wrote:
I submitted an almost identical patch. See
https://github.com/u-boot/u-boot/commit/eb39d8ba5f0d1468b01b89a2a464d18612d3ea76
This patch
On 7/12/21 5:43 PM, Tom Rini wrote:
On Mon, Jul 12, 2021 at 05:38:33PM +0200, Marek Vasut wrote:
On 7/12/21 5:15 PM, Tom Rini wrote:
On Mon, Jul 12, 2021 at 01:36:14PM +0800, Bin Meng wrote:
On Mon, Jul 12, 2021 at 1:21 PM Reuben Dowle wrote:
I submitted an almost identical patch. See
On Mon, Jul 12, 2021 at 05:38:33PM +0200, Marek Vasut wrote:
> On 7/12/21 5:15 PM, Tom Rini wrote:
> > On Mon, Jul 12, 2021 at 01:36:14PM +0800, Bin Meng wrote:
> > > On Mon, Jul 12, 2021 at 1:21 PM Reuben Dowle wrote:
> > > >
> > > > I submitted an almost identical patch. See
> > > >
On 7/12/21 5:15 PM, Tom Rini wrote:
On Mon, Jul 12, 2021 at 01:36:14PM +0800, Bin Meng wrote:
On Mon, Jul 12, 2021 at 1:21 PM Reuben Dowle wrote:
I submitted an almost identical patch. See
https://github.com/u-boot/u-boot/commit/eb39d8ba5f0d1468b01b89a2a464d18612d3ea76
This patch
On Mon, Jul 12, 2021 at 01:36:14PM +0800, Bin Meng wrote:
> On Mon, Jul 12, 2021 at 1:21 PM Reuben Dowle wrote:
> >
> > I submitted an almost identical patch. See
> > https://github.com/u-boot/u-boot/commit/eb39d8ba5f0d1468b01b89a2a464d18612d3ea76
> >
> > This patch eventually had to be reverted
Am Sun, Feb 21, 2021 at 08:26:24AM -0800 schrieb Ye Li:
> Setup USB clock in board codes, and enable the DWC3 XHCI and
> PHY drivers to make USB3.0 host port working on i.MX8MQ EVK.
>
> Signed-off-by: Ye Li
The same change works on the MNT Reform 2 as well.
Reviewed-by: Patrick Wildt
>
Am Sun, Feb 21, 2021 at 08:26:23AM -0800 schrieb Ye Li:
> Add clock function to setup relevant clocks for USB3.0 controllers and
> PHYs on i.MX8MQ
>
> Signed-off-by: Ye Li
Reviewed-by: Patrick Wildt
Tested-by: Patrick Wildt
> ---
> arch/arm/include/asm/arch-imx8m/clock.h | 1 +
>
Am Sun, Feb 21, 2021 at 08:26:22AM -0800 schrieb Ye Li:
> Add alias for two DWC3 usb controllers to fix the seq index.
>
> Signed-off-by: Ye Li
> ---
> arch/arm/dts/imx8mq.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi
>
Am Sun, Feb 21, 2021 at 08:26:21AM -0800 schrieb Ye Li:
> Add the USB PHY driver for i.MX8MQ to work with DWC3 USB controller.
>
> Signed-off-by: Ye Li
Reviewed-by: Patrick Wildt
Tested-by: Patrick Wildt
> ---
> drivers/phy/Kconfig | 7 ++
> drivers/phy/Makefile | 1 +
>
On Mon, Jul 12, 2021 at 04:15:10PM +0200, Marek Behun wrote:
> On Mon, 12 Jul 2021 10:10:14 -0400
> Tom Rini wrote:
>
> > On Mon, Jul 12, 2021 at 04:01:13PM +0200, Marek Behun wrote:
> >
> > > Tom,
> > >
> > > there are 16 boards left with CONFIG_SPI_FLASH
> > > (git grep CONFIG_SPI_FLASH=y)
>
Am Mon, Jul 12, 2021 at 10:28:25AM -0300 schrieb Fabio Estevam:
> Hi Patrick,
>
> On Sat, Jul 10, 2021 at 8:35 PM Patrick Wildt wrote:
>
> > is this patchset still being reviewed? I think the discussion has moved
> > to some SD card problem, which is fixed now? Would be nice if USB 3.0
>
> I
On Mon, 12 Jul 2021 10:10:14 -0400
Tom Rini wrote:
> On Mon, Jul 12, 2021 at 04:01:13PM +0200, Marek Behun wrote:
>
> > Tom,
> >
> > there are 16 boards left with CONFIG_SPI_FLASH
> > (git grep CONFIG_SPI_FLASH=y)
> > and Makefile says this was supposed to be deprecated in v2019.07.
> >
> >
On Mon, 12 Jul 2021 16:01:13 +0200
Marek Behun wrote:
> Tom,
>
> there are 16 boards left with CONFIG_SPI_FLASH
> (git grep CONFIG_SPI_FLASH=y)
> and Makefile says this was supposed to be deprecated in v2019.07.
>
> Are we going to remove them so that we can simplify the SPI subsystem?
>
>
On Mon, Jul 12, 2021 at 04:01:13PM +0200, Marek Behun wrote:
> Tom,
>
> there are 16 boards left with CONFIG_SPI_FLASH
> (git grep CONFIG_SPI_FLASH=y)
> and Makefile says this was supposed to be deprecated in v2019.07.
>
> Are we going to remove them so that we can simplify the SPI subsystem?
From: Peter Hoyes
CNTFRQ_EL0 is only writable from the highest supported exception
level on the platform. For Armv8-A, this is typically EL3, but
technically EL2 and EL3 are optional so it may need to be
initialized at EL2 or EL1. For Armv8-R, the highest exception
level is always EL2.
This
> > > > TPM_STS_SELF_TEST_DONE = 1 << 2,
[...]
> > > > TPM_STS_RESPONSE_RETRY = 1 << 1,
> > > > + TPM_STS_READ_ZERO = 0x23
> > >
> > > Does this below in another patch?
> > >
> >
> > It's a general tpm2 update. I can move it to the driver
Tom,
there are 16 boards left with CONFIG_SPI_FLASH
(git grep CONFIG_SPI_FLASH=y)
and Makefile says this was supposed to be deprecated in v2019.07.
Are we going to remove them so that we can simplify the SPI subsystem?
Marek
Hi Patrick,
On Sat, Jul 10, 2021 at 8:35 PM Patrick Wildt wrote:
> is this patchset still being reviewed? I think the discussion has moved
> to some SD card problem, which is fixed now? Would be nice if USB 3.0
I think you are referring to
On Fri, Jul 09, 2021 at 04:26:35PM +0800, Zong Li wrote:
> We wouldn't like to allow user to change the serial number, so remove
> the command for changing serial number in EEPROM.
>
> Signed-off-by: Zong Li
> Suggested-by: David Abdurachmanov
> ---
> .../unmatched/hifive-platform-i2c-eeprom.c
On Fri, Jul 09, 2021 at 04:06:01PM +0800, Zong Li wrote:
> This patch reverts the following commits:
> - 4b4159d0f3 ("riscv: dts: add dts for unmatched rev1")
> - ffe9a394df ("board: sifive: support spl multi-dtb on unmatched board")
>
> We won't plan to support unmatched that the revision
On 08.07.21 20:19, Pali Rohár wrote:
Signed-off-by: Pali Rohár
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
drivers/pci/pci-aardvark.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index
On 08.07.21 20:18, Pali Rohár wrote:
If fixup offset is zero then there is nothing to fix. All calculation in
this case just increase addresses by value zero which results in identity.
So in this case skip whole fixup re-calculation as it is not needed.
This is just an optimization for special
On 08.07.21 20:18, Pali Rohár wrote:
Remapped address of PCIe outbound window may have set only bits from the
mask. Add additional check that remapped address which is calculated from
PCIe bus address specified in DTS file is valid.
Remove also useless clearing of low 16 bits in win_mask. As
On 09.07.21 17:40, Marek Behún wrote:
The config option CONFIG_DEBUG_UART_CLOCK is not used by Armada 3720's
serial driver (it wasn't even before the recent update of that driver).
Even if it was used, the value was incorrect (the frequency of the clock
is 25 MHz, not 25.8048 MHz).
Remove it
On 10.07.21 16:51, Stefano Babic wrote:
> Following warnings (unused variables) are raised:
>
> drivers/spi/mxc_spi.c: In function 'mxc_spi_probe':
> drivers/spi/mxc_spi.c:595:14: error: unused variable 'blob'
> [-Werror=unused-variable]
> 595 | const void *blob = gd->fdt_blob;
> |
From: Chen Guanqiao
Fixed a defect of a null pointer being discovered by Coverity Scan:
CID 331544: Null pointer dereferences (REVERSE_INULL)
Null-checking "size" suggests that it may be null, but it has already been
dereferenced on all paths leading to the check.
Signed-off-by: Chen
On Mon, 12 Jul 2021 19:57:04 +0900
Jaehoon Chung wrote:
> Hi Andre,
>
> On 7/12/21 7:06 PM, Andre Przywara wrote:
> > When the Allwinner BROM loads the SPL from an eMMC boot partition, it
> > sets the boot source byte to the same value as when booting from the
> > user data partition. This
Hi Ilias,
On Mon, 12 Jul 2021 at 00:24, Ilias Apalodimas
wrote:
>
> On Sat, Jul 10, 2021 at 06:00:57PM -0600, Simon Glass wrote:
> > Hi Ilias,
> >
> > On Wed, 7 Jul 2021 at 10:26, Ilias Apalodimas
> > wrote:
> > >
> > > There's a lot of code duplication in U-Boot right now. All the TPM TIS
> >
On 7/9/21 1:53 PM, Ashok Reddy Soma wrote:
> This patch set fixes below issues in zynq_sdhc driver
> - Fix issues in tap delay functions where it returns uninitialized values
> - Allow configuring zero tap delay values
> - Split tapdelay functions to set input and output tap delay's
st 7. 7. 2021 v 8:45 odesílatel Michal Simek napsal:
>
> lpd_lsbus is clock which is used by many IPs like dmas, gems, gpio, sdhcis,
> spis, ttcs, uarts, watchdog that's why make sense to also enable access to
> change this clock. For this clock you already get the rate.
>
> Signed-off-by: Michal
st 7. 7. 2021 v 8:21 odesílatel Michal Simek napsal:
>
> From: Piyush Mehta
>
> The board zynqmp-zc1751-xm016-dc2 support only USB2.0.
> This patch removes USB3.0 DT configuration for DC2 board.
>
> Signed-off-by: Piyush Mehta
> Signed-off-by: Michal Simek
> ---
>
>
Hi,
just for the note because there is an open comment and I applied it:
On 16.06.21 05:17, Tom Rini wrote:
On Tue, Jun 15, 2021 at 08:38:38PM -0300, Fabio Estevam wrote:
On the Yocto image there is a single partition and the kernel
and dtb are present in the 'boot' directory.
Change it
Hi Andre,
On 7/12/21 7:06 PM, Andre Przywara wrote:
> When the Allwinner BROM loads the SPL from an eMMC boot partition, it
> sets the boot source byte to the same value as when booting from the
> user data partition. This prevents us from determining the boot source
> to load U-Boot proper from
Since we can not set OsIndications from Runtime Services
SetVariables at this moment, it is better to ignore the
OsIndications if there is any capsule file in the
correct place.
Signed-off-by: Masami Hiramatsu
---
configs/synquacer_developerbox_defconfig |1 +
1 file changed, 1 insertion(+)
Since the recent commit;
commit b891ff18f899 ("efi_loader: Force a single FMP instance per hardware
store")
forces a single FMP instances for a storage, we can not
enable both RAW and FIT capsule image support at once.
Since RAW capsule image support is simpler than FIT,
enable RAW capsule
Enable UEFI secure boot on synquacer. Note that unless user
setup their keys, the secure boot will not work.
Signed-off-by: Masami Hiramatsu
---
Changes in v3:
- Fix configs with savedefconfig.
---
configs/synquacer_developerbox_defconfig |1 +
1 file changed, 1 insertion(+)
diff --git
Since the U-Boot for the SynQuacer DeveloperBox is designed for
compatible with EDK2 boot, we don't need to support Ext2/4 fs
support by default. Drop it.
Signed-off-by: Masami Hiramatsu
---
Changes in v3:
- Fix configs with savedefconfig.
---
configs/synquacer_developerbox_defconfig |2
Since MTD partitions are based on the devicetree name,
remove unneeded mtdparts settings and update DFU setting.
Signed-off-by: Masami Hiramatsu
---
Changes in v3:
- Fix configs with savedefconfig.
---
configs/synquacer_developerbox_defconfig |2 --
include/configs/synquacer.h
Add partition information to the spi-nor flash.
This is required for accessing NOR flash via mtdparts.
Signed-off-by: Masami Hiramatsu
Reviewed-by: Marek Behún
---
Changes in v3:
- Add Marek's Reviewed-by.
Changes in v2:
- Add new lines to separate the partitions.
---
Make the U-Boot binary for SynQuacer position independent so
that the previous bootloader (SCP firmware or BL2) can load
the U-Boot anywhere.
Signed-off-by: Masami Hiramatsu
---
Changes in v3:
- Fix configs with savedefconfig.
Changes in v2:
- Fix a typo in the changelog.
---
Since the SCBM SMMU is not only connected to the NETSEC
but also shared with the F_SDH30 (eMMC controller), that
should be initialized at board level instead of NETSEC.
Move the SMMU initialization code into board support
and call it from board_init().
Without this fix, if the NETSEC is
Hi,
Here is the 3rd version of the series to update the DeveloperBox support.
I found that the latest master branch update defconfigs with
savedefconfig by;
commit 2bba78076b03 ("configs: Resync with savedefconfig")
So I decided to update the patches for the defconfig so that
those can be
Hi,
I found that the latest master had defconfig cleanup by
commit 2bba78076b03 ("configs: Resync with savedefconfig")
including configs/synquacer_developerbox_defconfig.
So the configs patch must be updated.
Also, when testing capsule update on U-Boot, I need to change
some options, so I will
Now that the SPL can safely detect whether it was loaded from an eMMC
boot partition or the normal user data partition, let's enable this
feature on some boards that feature eMMC storage.
That covers the boards where I could test this on, and allows the same
build to be written to an SD card,
When the Allwinner BROM loads the SPL from an eMMC boot partition, it
sets the boot source byte to the same value as when booting from the
user data partition. This prevents us from determining the boot source
to load U-Boot proper from the proper partition for sure.
The generic SPL MMC code
Platforms can overwrite the weak definition of spl_mmc_boot_mode() to
determine where to load U-Boot proper from.
For most of them this is a trivial decision based on Kconfig variables,
but it might be desirable the probe the actual device to answer this
question.
Pass the pointer to the mmc
(resent to also include forgotten U-Boot list)
The Allwinner BootROM supports loading the SPL from eMMC boot partitions,
but so far the SPL support for this case was a bit lacking, as it was a
compile time decision, and even required a manual config change.
This actually got accidentally fixed in
Add defconfig for N5X to support legacy, ATF and VAB boot flow.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Kconfig | 21 +++-
arch/arm/mach-socfpga/Makefile | 28 ++
...lex_vab_defconfig =>
Add CONFIGs for N5X.
Signed-off-by: Siew Chin Lim
---
include/configs/socfpga_n5x_socdk.h | 45 +
1 file changed, 45 insertions(+)
create mode 100644 include/configs/socfpga_n5x_socdk.h
diff --git a/include/configs/socfpga_n5x_socdk.h
Add device tree for N5X.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
v4:
- Reuse socfpga_n5x_socdk.dts from Linux and add U-boot specifc dts
to u-boot.dtsi. Linux socfpga_n5x_socdk.dts:
From: Tien Fong Chee
The DDR subsystem in Diamond Mesa is consisted of controller, PHY,
memory reset manager and memory clock manager.
Configuration settings of controller, PHY and memory reset manager
is come from DDR handoff data in bitstream, which contain the register
base addresses and
Add N5X SoC devkit board.
Signed-off-by: Siew Chin Lim
---
board/intel/n5x-socdk/MAINTAINERS | 7 +++
board/{altera/stratix10-socdk => intel/n5x-socdk}/Makefile | 2 +-
board/{altera/stratix10-socdk => intel/n5x-socdk}/socfpga.c | 2 +-
3 files changed, 9
Add SPL for N5X.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/{spl_agilex.c => spl_n5x.c} | 37 ++-
1 file changed, 22 insertions(+), 15 deletions(-)
copy arch/arm/mach-socfpga/{spl_agilex.c => spl_n5x.c} (83%)
diff --git a/arch/arm/mach-socfpga/spl_agilex.c
From: Tien Fong Chee
Minimum 1GB memory size is required in current memory test, so this patch
improves the memory test for processing memory size less than 1GB, and
the size in power of two.
Signed-off-by: Tien Fong Chee
---
drivers/ddr/altera/sdram_soc64.c | 24 +---
1
Add clock manager for N5X.
Signed-off-by: Siew Chin Lim
---
...{clock_manager_agilex.c => clock_manager_n5x.c} | 32 ++
arch/arm/mach-socfpga/include/mach/clock_manager.h | 2 ++
.../mach-socfpga/include/mach/clock_manager_n5x.h | 12
3 files changed, 29
Rename to common file name to used by all SOC64 devices.
No functionality change.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 4 ++--
arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} | 12 ++--
2 files changed, 8 insertions(+), 8 deletions(-)
Move cm_get_mpu_clk_hz function declaration from individual device's
clock manager header file to common clock_manager.h.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/clock_manager.h | 1 +
arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h | 2 --
Add memory clock manager driver for N5X. Provides memory clock
initialization and enable functions.
Signed-off-by: Siew Chin Lim
---
drivers/clk/altera/Makefile | 1 +
drivers/clk/altera/clk-mem-n5x.c | 136 +++
drivers/clk/altera/clk-mem-n5x.h | 84
1 - 100 of 138 matches
Mail list logo
