Fix typo and whitespace in the document.
Signed-off-by: Yu Chien Peter Lin
---
doc/develop/devicetree/dt_qemu.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/doc/develop/devicetree/dt_qemu.rst
b/doc/develop/devicetree/dt_qemu.rst
index c25c4fb053..8ba2b22559 100644
This patch adds a brief introduction to the RISC-V architecture and
the typical boot process used on a variety of RISC-V platforms.
Signed-off-by: Yu Chien Peter Lin
---
Hi RISC-V community,
Please leave a comment if there is anything I've missed that should
be mentioned in the document.
On Sun, Jan 8, 2023, at 08:57, Simon Glass wrote:
> This board is useful for benchmarking overall U-Boot performance. Enable
> the bootstage feature so we get a report.
>
> Since this returns to the boot rom before finishing executing
> board_init_r() in SPL, add a few bootstage calls so that we
The PHY nodes may be activated via DTO in case another SoM variant
is populated into the development kit. Do not delete the nodes.
Signed-off-by: Marek Vasut
---
Cc: "NXP i.MX U-Boot Team"
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
Cc: u-boot@lists.denx.de
---
V2: No change
---
The i.MX8MP DHCOM SoM may come with either external RGMII PHY or
LAN8740Ai RMII PHY on the SoM attached to FEC MAC. Add pin mux
settings for both options, so that DT overlay can override these
settings on SoM variant with the LAN8740Ai PHY.
Signed-off-by: Marek Vasut
---
Cc: "NXP i.MX U-Boot
The i.MX8MP DHCOM SoM may come with either KSZ9131RNXI RGMII PHY
or LAN8740Ai RMII PHY on the SoM attached to EQoS MAC. Add pin
mux settings for both options, so that DT overlay can override
these settings on SoM variant with the LAN8740Ai PHY.
Signed-off-by: Marek Vasut
---
Cc: "NXP i.MX U-Boot
The current variant of the SoM has LAN8740Ai PHY connected to EQoS
strapped to MDIO address 0 , adjust the MDIO address to match the
hardware.
Signed-off-by: Marek Vasut
---
Cc: "NXP i.MX U-Boot Team"
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
Cc: u-boot@lists.denx.de
---
V2: This is
The i.MX8MP DHCOM SoM may be populated with either KSZ9131RNXI RGMII PHY
or LAN8740Ai RMII PHY attached to EQoS MAC, and either external RGMII PHY
or LAN8740Ai RMII PHY attached to FEC MAC. The SoM configuration can be
detected for each MAC by reading RX_CTL pull resistor state early on boot.
Make
The PHY nodes may be activated via DTO in case another SoM variant
is populated into the development kit. Do not delete the nodes.
Signed-off-by: Marek Vasut
---
Cc: "NXP i.MX U-Boot Team"
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
Cc: u-boot@lists.denx.de
---
The i.MX8MP DHCOM SoM may come with either external RGMII PHY or
LAN8740Ai RMII PHY on the SoM attached to FEC MAC. Add pin mux
settings for both options, so that DT overlay can override these
settings on SoM variant with the LAN8740Ai PHY.
Signed-off-by: Marek Vasut
---
Cc: "NXP i.MX U-Boot
The i.MX8MP DHCOM SoM may come with either KSZ9131RNXI RGMII PHY
or LAN8740Ai RMII PHY on the SoM attached to EQoS MAC. Add pin
mux settings for both options, so that DT overlay can override
these settings on SoM variant with the LAN8740Ai PHY.
Signed-off-by: Marek Vasut
---
Cc: "NXP i.MX U-Boot
The current variant of the SoM has LAN8740Ai PHY connected to FEC
strapped to MDIO address 0 , adjust the MDIO address to match the
hardware.
Signed-off-by: Marek Vasut
---
Cc: "NXP i.MX U-Boot Team"
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
Cc: u-boot@lists.denx.de
---
The DH electronics i.MX8M Plus DHCOM SoM currently supports only 4 GiB
of DRAM population option. Add another population option with 2 GiB of
DRAM. The chips used on the 2 GiB option are 2x K4F6E3S4HM-MGCJ .
Signed-off-by: Marek Vasut
---
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
---
Enable LTO to reduce the size of SPL, which with multiple DRAM
calibration tables may be close to the limit.
Signed-off-by: Marek Vasut
---
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
---
configs/imx8mp_dhcom_pdk2_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git
The FEC interface mode is now configured in common board_interface_eth_init()
and called by FEC MAC driver when appropriate. Drop the board side duplicates
if the same functionality.
Signed-off-by: Marek Vasut
---
Cc: "Ariel D'Alessandro"
Cc: "NXP i.MX U-Boot Team"
Cc: Andrey Zhizhikin
Cc:
The EQoS interface mode is now configured in common board_interface_eth_init()
and called by EQoS MAC driver when appropriate. Drop the board side duplicates
if the same functionality.
Signed-off-by: Marek Vasut
---
Cc: "Ariel D'Alessandro"
Cc: "NXP i.MX U-Boot Team"
Cc: Andrey Zhizhikin
Cc:
The assigned-clock no longer have to be dropped, the clock are now
defined in clk-imx8mp.c and used by DWMAC driver to configure the
DWMAC clock. Drop the workarounds from U-Boot specific DT extras.
Signed-off-by: Marek Vasut
---
Cc: "Ariel D'Alessandro"
Cc: "NXP i.MX U-Boot Team"
Cc: Andrey
Implement common board_interface_eth_init() and call it from the FEC
driver to configure IOMUXC GPR[1] register according to the PHY mode
obtained from DT. This supports all three interface modes supported by
the i.MX8M Mini/Nano/Plus FEC and supersedes the current board-side
configuration of the
The FEC ref clock frequency on i.MX8M Mini/Nano/Plus was so far configured
via ad-hoc board code. Replace that with DM clock clk_set_rate() instead.
This way, the driver claims all its required clock and sets the ref clock
rate, without any need of architecture specific register fiddling.
Implement common board_interface_eth_init() and call it from the DWMAC
driver to configure IOMUXC GPR[1] register according to the PHY mode
obtained from DT. This supports all three interface modes supported by
the i.MX8M Plus DWMAC and supersedes current board-side configuration
of the same IOMUX
With DM clock support in place, it is easy to add RMII support into the
MAC driver. The RMII cannot operate at 1000 Mbps and at 100 and 10 Mbps
the clock frequency is 50 MHz and 5 MHz instead of 25 MHz and 2.5 MHz.
The board DT requires the following adjustments to EQoS node:
phy-mode = "rmii";
The DWMAC clock in i.MX8M Plus were so far configured via ad-hoc
architecture code. Replace that with DM clock instead. This way,
the driver claims all its required clock, enables and disables
them, and even gets the CSR clock rate and sets the TX clock rate,
without any need of architecture
The driver currently only waits for DMA_MODE SWR bit to clear itself.
This is insufficient e.g. on i.MX8M Plus, where the MAC must be reset
before IOMUX GPR[1] content is latched into the MAC and used. Without
the proper reset, the i.MX8M Plus MAC variant does not take the value
in IOMUX GPR[1]
This function is only used within the driver, staticize it.
Fixes: 149e80f74b6 ("net: dwc_eth_qos: public some functions")
Signed-off-by: Marek Vasut
---
Cc: "Ariel D'Alessandro"
Cc: "NXP i.MX U-Boot Team"
Cc: Andrey Zhizhikin
Cc: Fabio Estevam
Cc: Joe Hershberger
Cc: Lukasz Majewski
Cc:
The dm_gpio_free() is never called, because for stm32, the phy_reset_gpio
pointer is never valid. This is because only tegra186 ever claims the
phy_reset_gpio, all other platforms use the PHY framework to reset the
PHY instead. Drop the dm_gpio_free() and dm_gpio_is_valid().
Reviewed-by: Ramon
The return is never triggered due to the goto just above it.
Drop it. No functional change.
Reviewed-by: Ramon Fried
Signed-off-by: Marek Vasut
---
Cc: "Ariel D'Alessandro"
Cc: "NXP i.MX U-Boot Team"
Cc: Andrey Zhizhikin
Cc: Fabio Estevam
Cc: Joe Hershberger
Cc: Lukasz Majewski
Cc: Marcel
Move the board_interface_eth_init() into common ethernet uclass code,
since this function could be shared by multiple drivers.
Signed-off-by: Marek Vasut
---
Cc: "Ariel D'Alessandro"
Cc: "NXP i.MX U-Boot Team"
Cc: Andrey Zhizhikin
Cc: Fabio Estevam
Cc: Joe Hershberger
Cc: Lukasz Majewski
Add clock for the DWMAC EQoS block. This is used among other things
to configure the MII clock via DM CLK.
Acked-by: Sean Anderson
Signed-off-by: Marek Vasut
---
Cc: "Ariel D'Alessandro"
Cc: "NXP i.MX U-Boot Team"
Cc: Andrey Zhizhikin
Cc: Fabio Estevam
Cc: Joe Hershberger
Cc: Lukasz
From: Álvaro Fernández Rojas
Hamming ECC doesn't cover the OOB data, so reading or writing OOB shall
always be done without ECC enabled.
This is a problem when adding JFFS2 cleanmarkers to erased blocks. If JFFS2
clenmarkers are added to the OOB with ECC enabled, OOB bytes will be changed
from
From: Álvaro Fernández Rojas
v2.1: tested on Netgear DGND3700v1 (BCM6368)
v2.2: tested on Netgear DGND3700v2 (BCM6362)
Signed-off-by: Álvaro Fernández Rojas
Acked-by: Florian Fainelli
Signed-off-by: Miquel Raynal
Link:
From: Álvaro Fernández Rojas
Only v3.3-v5.0 have a different CS0 layout.
Controllers before v3.3 use the same layout for every CS.
Fixes: 27c5b17cd1b1 ("mtd: nand: add NAND driver "library" for Broadcom STB
NAND controller")
Signed-off-by: Álvaro Fernández Rojas
Acked-by: Florian Fainelli
From: Álvaro Fernández Rojas
Current pages sizes apply to controllers after v3.4
Signed-off-by: Álvaro Fernández Rojas
Acked-by: Florian Fainelli
Signed-off-by: Miquel Raynal
Link:
https://lore.kernel.org/linux-mtd/20200522121524.4161539-4-nolt...@gmail.com
[Ported to U-Boot from the Linux
From: Álvaro Fernández Rojas
These registers are also used on v3.3.
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Miquel Raynal
Acked-by: Florian Fainelli
Signed-off-by: Miquel Raynal
Link:
https://lore.kernel.org/linux-mtd/20200522121524.4161539-2-nolt...@gmail.com
[Ported to U-Boot
From: Álvaro Fernández Rojas
The current code checks that the whole OOB area is erased.
This is a problem when JFFS2 cleanmarkers are added to the OOB, since it will
fail due to the usable OOB bytes not being 0xff.
Correct this by only checking that data and ECC bytes aren't 0xff.
Fixes:
From: Kamal Dasu
This change adds support for flash dma v0.0.
Signed-off-by: Kamal Dasu
Signed-off-by: Miquel Raynal
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 21 +++--
1 file changed, 19
From: Claire Lin
In brcmstb_nand_verify_erased_page(), the ECC chunk pointer calculation
while correcting erased page bitflips is wrong, fix it.
Fixes: 02b88eea9f9c ("mtd: brcmnand: Add check for erased page bitflips")
Signed-off-by: Claire Lin
Reviewed-by: Ray Jui
Signed-off-by: Kamal Dasu
From: Kamal Dasu
This change adds support for brcm NAND v7.3 controller. This controller
uses a newer version of flash_dma engine and change mostly implements
these differences.
Signed-off-by: Kamal Dasu
Signed-off-by: Miquel Raynal
[Ported to U-Boot from the Linux kernel]
Signed-off-by:
From: Kamal Dasu
Refactored NAND ECC and CMD address configuration code to use helper
functions.
Signed-off-by: Kamal Dasu
Signed-off-by: Miquel Raynal
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 100
Hunting down a bug on my system I took to back-porting
all reasonable changes from the Linux brcmnand driver that
were not yet in the U-Boot derivative.
I noticed that a simple diff -ur between brcmnand.c
between the file in Linux and U-Boot was possible to see
what differs. Combining this with
在 2023-02-10星期五的 07:25 +，Leo Liang写道：
> Hi Xiang,
>
> On Fri, Feb 03, 2023 at 03:24:37PM +0100, David Abdurachmanov wrote:
> > On Mon, Jan 3, 2022 at 1:13 PM Leo Liang wrote:
> > >
> > > On Thu, Dec 30, 2021 at 01:55:15AM +0800, Xiang W wrote:
> > > > 在 2021-12-29星期三的 17:23 +0800，Leo
-length/20230110-185915
patch link:
https://lore.kernel.org/r/20230110105425.13188-1-zajec5%40gmail.com
patch subject: [PATCH 1/6] nvmem: core: add nvmem_dev_size() helper
config: m68k-allyesconfig
(https://download.01.org/0day-ci/archive/20230211/202302112138.xodxy4yf-...@intel.com/config
TLDR: In the configuration SPL_MXC_OCOTP, the dependency on SPL_MISC
should be replaced by SPL_DRIVERS_MISC.
Hi folks,
I was creating a new imx6 board with an SPL and without enabling the
"driver model for SPL" to keep a pretty simple SPL.
Then I wanted to enable the secure boot, and so the
Previously, the TX LED would flash but nothing would appear on the
serial port, and the board would appear dead with a build of the
socfpga_cyclone5_defconfig. I have verified that adding the frequency to
the uart will fix the serial console on my board.
Thanks to @ehoffman on the Rocketboards
Convert the documentation for the Broadcom BCM7445 and BCM7260 boards
to reStructuredText format and add the new filename to
doc/board/broadcom/index.rst.
---
doc/README.bcm7xxx | 156 ---
doc/board/broadcom/bcm7xxx.rst | 186 +
From: Ulf Samuelsson
Signed-off-by: Ulf Samuelsson
---
drivers/mtd/fpga/Kconfig | 47 ++
drivers/mtd/fpga/Makefile | 6 +
drivers/mtd/fpga/cyclone_10.c | 278 ++
3 files changed, 331 insertions(+)
create mode 100644 drivers/mtd/fpga/Kconfig
From: Ulf Samuelsson
Signed-off-by: Ulf Samuelsson
---
drivers/mtd/Kconfig | 2 ++
drivers/mtd/Makefile | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index af45ef00da..495211e314 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@
From: Ulf Samuelsson
Signed-off-by: Ulf Samuelsson
---
include/mtd/mtd-abi.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/mtd/mtd-abi.h b/include/mtd/mtd-abi.h
index ea244fbaeb..cd826b64dd 100644
--- a/include/mtd/mtd-abi.h
+++ b/include/mtd/mtd-abi.h
@@ -89,6 +89,7 @@ struct
From: Ulf Samuelsson
Signed-off-by: Ulf Samuelsson
---
cmd/mtd.c | 8
1 file changed, 8 insertions(+)
diff --git a/cmd/mtd.c b/cmd/mtd.c
index eb6e2d6892..09d5fdaa11 100644
--- a/cmd/mtd.c
+++ b/cmd/mtd.c
@@ -158,6 +158,9 @@ static void mtd_show_device(struct mtd_info *mtd)
As shown at a presentation in the recent OpenEmbedded Workshop,
it is possible to configure an FPGA in Passive Serial mode
using a standard SPI controller, each FPGA getting its own chipselect.
https://pretalx.com/openembedded-workshop-2023/talk/D3AQ3R/
This allows you to add the FPGA to the
Hi Linus
On Fri, Feb 3, 2023 at 6:23 PM William Zhang wrote:
>
> Hi Linus and Michael,
>
> On 02/03/2023 03:10 AM, Linus Walleij wrote:
> > On Fri, Feb 3, 2023 at 9:48 AM Michael Nazzareno Trimarchi
> > wrote:
> >> On Thu, Jan 26, 2023 at 6:39 PM William Zhang
> >> wrote:
> >>>
> >>>
> >>>
>
This adds a new board from CS GROUP. The board is called
MCR3000_2G, and has a CPU board called CMPC885.
That CPU board is shared with another equipment that will
be added in a later patch.
That board stores Ethernet MAC addresses in an EEPROM which
is accessed using SPI bus.
This patch was
This adds support for the MIAE and VGoIP devices.
Those devices have the same CPU board that the MCR3000_2G board.
The devices are very modular, they are provided with
interchangeable front and back panels.
Linux kernel is shipped with a device tree which contains all
possible setups, and U-boot
Ports A, C and D are 16 bits ports.
Ports B and E are 32 bits ports.
The "compatible" is used to determine each port type.
This patch was originally written by Charles Frey who's
email address is not valid anymore as he left the company.
Signed-off-by: Christophe Leroy
Reviewed-by: FRANJOU
We can move all of the environment changes to come
from CONFIG_EXTRA_ENV_TEXT.
Suggested-by: Tom Rini
Signed-off-by: Christophe Leroy
---
board/cssi/mcr3000/mcr3000.env | 14 +++
include/configs/mcr3000.h | 43 --
2 files changed, 14 insertions(+),
Both U-boot and Linux kernel have grown over the last releases
and don't fit anymore in the 2M EPROM of the board.
So, rework the setup to allow storing the Linux kernel image
on the UBIFS NAND Flash.
Also add support to FIT images as this is what the Linux kernel
look like nowadays.
Also
Rename MCR3000.* to mcr3000.* to be more in line with
other boards.
Signed-off-by: Christophe Leroy
---
arch/powerpc/cpu/mpc8xx/Kconfig | 2 +-
board/cssi/MAINTAINERS | 2 +-
board/cssi/{MCR3000 => mcr3000}/Kconfig | 4 ++--
This series adds a new CPU board called CMPC885 which
is used on two equipments called MCR3000 second generation
and MIAE/VGoIP devices, manufactured by former CSSI company
now called CS GROUP France.
This new board has a mpc 885 cpu.
The four first patches of the series update the already
This patch fixes the mpc8xx SPI driver:
- A stub callbacks for mode and speed,
- Use chip selects defined as GPIOs,
- Write proper value to disable relocation, other it fails on mpc885,
- Don't modify ports setup, ports can be different from one board to
another and are already set by
e1-wan device-tree node doesn't exist. Remove related update
to avoid following warning at startup:
Loading Device Tree to 007fa000, end 007ff951 ... OK
Unable to update property /localbus/e1-wan:data-rate,
err=FDT_ERR_NOTFOUND
Unable to update property
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