Am 29. März 2023 22:02:11 MESZ schrieb Simon Glass :
>Hi Heinrich,
>
>On Wed, 29 Mar 2023 at 05:43, Heinrich Schuchardt wrote:
>>
>> On 3/27/23 21:34, Simon Glass wrote:
>> > The second call to cli_ch_process() is in the wrong place, meaning that
>> > the one of the characters of an invalid
On 3/27/23 15:22, Nuno Sá wrote:
flash_get_size() will get the flash size from the device itself and go
through all erase regions to read protection status. However, the device
mappable region (eg: devicetree reg property) might be lower than the
device full size which means that the above cycle
On 3/27/23 23:11, Pali Rohár wrote:
Show correct information in debug() output and use correct names for variables.
No functional change.
Signed-off-by: Pali Rohár
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
arch/arm/mach-mvebu/cpu.c | 15 ++-
1 file changed, 10
On 3/27/23 13:24, Martin Rowe wrote:
[upstream of vendor commit 19a96f7c40a8fc1d0a6546ac2418d966e5840a99]
The Clearfog devices have only one SDHC device. This is either eMMC if
it is populated on the SOM or SDHC if not. The Linux device tree assumes
the SDHC case. Detect if the device is an
On 3/29/23 21:03, Pali Rohár wrote:
Definitions are according to the MV78460 Hardware Specifications.
Signed-off-by: Pali Rohár
Tested-by: Tony Dinh
Tested-by: Martin Rowe
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
arch/arm/mach-mvebu/include/mach/soc.h | 4
1 file changed, 4
On 3/29/23 21:03, Pali Rohár wrote:
A385 BootROM fills into bits [31:28] of register 0x182d0 tracing value,
which represents in which state BootROM currently is. BootROM fills one
of the possible values: 0x2 (CPU initialization), 0x3 (UART detection),
0x6 (UART booting), 0x8 (PCI Express
On 3/29/23 21:03, Pali Rohár wrote:
Disassembling A385 BootROM binary reveal how BootROM interprets strapping
pins for Boot Device Mode. All possible options are:
0x00..0x07 -> Parallel NOR
0x08..0x15 -> Parallel NAND
0x16..0x17 -> Parallel NOR
0x18..0x25 -> Parallel NAND
0x26..0x27 -> SPI NAND
On 3/29/23 21:03, Pali Rohár wrote:
This allows to merge BOOT_FROM_MMC and BOOT_FROM_MMC_ALT constants to one
macro. And also allows to extend other BOOT_FROM_* macros for other
variants.
Signed-off-by: Pali Rohár
Tested-by: Tony Dinh
Tested-by: Martin Rowe
Reviewed-by: Stefan Roese
On 3/29/23 21:03, Pali Rohár wrote:
A385 BootROM treats strapping configuration 0x22 as SPI-NAND. So remove
incorrect definition 0x22 as SATA. SATA on A385 has configuration 0x2A.
Signed-off-by: Pali Rohár
Tested-by: Tony Dinh
Tested-by: Martin Rowe
Reviewed-by: Stefan Roese
Thanks,
On 3/29/23 21:03, Pali Rohár wrote:
A385 BootROM treats strapping configuration 0x3f as invalid. When booting
fails (e.g. because of invalid configuration) then BootROM fallbacks to
UART booting.
Detecting BootROM fallback to UART booting is implemented in U-Boot since
commit 2fd4284051e3
Hi,
I think this line:
https://source.denx.de/u-boot/u-boot/-/blob/master/drivers/ram/rockchip/sdram_rk3399.c#L2957
should be
#if defined(CONFIG_RAM_ROCKCHIP_DEBUG)
instead of
#if defined(CONFIG_RAM_RK3399_LPDDR4)
The condition now evaluates to false on the RockPro64 board in the latest
U-Boot
On 2023/3/30 4:02, Simon Glass wrote:
> Hi Yanhong,
>
> On Wed, 29 Mar 2023 at 23:29, Yanhong Wang
> wrote:
>>
>> The StarFive ETHQOS hardware has its own clock and reset,so add a
>> corresponding glue driver to configure them.
>>
>> Signed-off-by: Yanhong Wang
>> ---
>> drivers/net/Kconfig
On Tue, Mar 14, 2023 at 11:24:45PM +0100, Christophe Leroy wrote:
> Last use of CONFIG_SYS_GPIO1_PRELIM was removed by
> commit fae2ea5951 ("ppc: Remove MPC8349EMDS board and ARCH_MPC8349
> support").
>
> Last use of CONFIG_SYS_GPIO2_PRELIM was removed even before by
> commit 6843862342 ("ppc:
On Tue, Mar 14, 2023 at 11:24:44PM +0100, Christophe Leroy wrote:
> Last (incorrect) use of those CONFIG items was removed by
> commit 9fd9abedcc ("TQM834x: remove defines causing gcc4.4 warnings")
>
> Those items are invalid and should have been removed at the
> same time because lblaw[] has
On Mon, Mar 13, 2023 at 02:54:32PM +0100, Janne Grunau wrote:
> Apple silicon SoCs have numerous embedded co-processors with pre-loaded
> firmware. The co-processors text and data sections need to be mapped via
> DART iommus controlled by the main processor. Those sections are
> exported as
On Mon, Mar 13, 2023 at 02:46:11PM +0100, Janne Grunau wrote:
> The Linux devicetrees for Apple silicon devices are after review
> feedback switching from deleting unused PCIe ports to disabling them.
>
> Link:
> https://lore.kernel.org/asahi/1ea2107a-bb86-8c22-0bbc-82c453ab0...@linaro.org/
>
On Mon, Mar 20, 2023 at 10:53:56PM +0530, Nikhil M Jain wrote:
> Include ti_armv7_common.env and ti/mmc.env, which includes' K3 common
> environment variables used across different K3 boards.
>
> This patch depends on
> https://lore.kernel.org/all/20230315052745.110502-1-n-fran...@ti.com/
>
>
On Tue, Mar 21, 2023 at 06:23:30PM +0530, Nikhil M Jain wrote:
> Move to using .env file for setting up environment variables for am65x.
>
> Signed-off-by: Nikhil M Jain
> Reviewed-by: Tom Rini
Applied to u-boot/next, thanks!
--
Tom
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Description: PGP signature
On Mon, Mar 20, 2023 at 10:32:08PM +0530, Nikhil M Jain wrote:
> Move to using .env file for setting up environment variables for am62ax.
>
> This patch depends on
> https://lore.kernel.org/all/20230315052745.110502-1-n-fran...@ti.com/
>
> Signed-off-by: Nikhil M Jain
> Reviewed-by: Tom Rini
On Fri, Mar 17, 2023 at 06:37:11PM -0500, Bryan Brattlof wrote:
> TI's security enforcing SoCs will authenticate each binary it loads by
> comparing it's signature with keys etched into the SoC during the boot
> up process. The am62ax family of SoCs by default will have some level of
> security
On Wed, Mar 15, 2023 at 10:57:45AM +0530, Neha Malcom Francis wrote:
> Move to using .env file for setting up environment variables for J721E
> and J7200.
>
> Signed-off-by: Neha Malcom Francis
> Reviewed-by: Tom Rini
Applied to u-boot/next, thanks!
--
Tom
signature.asc
Description: PGP
On Wed, Mar 15, 2023 at 10:57:44AM +0530, Neha Malcom Francis wrote:
> Move to using .env file for setting up environment variables for J721S2.
>
> Signed-off-by: Neha Malcom Francis
> Reviewed-by: Tom Rini
Applied to u-boot/next, thanks!
--
Tom
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Description: PGP signature
On Wed, Mar 15, 2023 at 10:57:43AM +0530, Neha Malcom Francis wrote:
> Add K3 common environment variables to .env. We retain the old-style C
> environment .h files to maintain compatibility with other K3 boards that
> have not moved to using .env yet.
>
> Signed-off-by: Neha Malcom Francis
>
On Mon, Mar 13, 2023 at 06:12:23PM +0530, Sinthu Raja wrote:
> From: Sinthu Raja
>
> It's possible that the Type-C plug orientation on the DIR line will be
> implemented through hardware design. In that situation, there won't be
> an external GPIO line available, but the driver still needs to
On Fri, Mar 03, 2023 at 08:16:28PM +0100, Christian Gmeiner wrote:
> For non TI boards it is not possible to enable the do_board_detect()
> call as TI_I2C_BOARD_DETECT is defined in board/ti/common/Kconfig.
>
> I want to use do_board_detect() to dectect boards and properties based
> on some SPI
On Fri, Mar 03, 2023 at 01:51:24PM +0530, Neha Malcom Francis wrote:
> Kconfig does not support using 'select' to select a 'choice'. A choice
> can be configured by either setting the choice symbol to 'y' in a
> configuration file or by setting a 'default' of the choice.
>
> In
On Mon, Mar 13, 2023 at 06:12:24PM +0530, Sinthu Raja wrote:
> From: Sinthu Raja
>
> The WIZ acts as a wrapper for SerDes and has Lanes 0 and 2 reserved
> for USB for type-C lane swap if Lane 1 and Lane 3 are linked to the
> USB PHY that is integrated into the SerDes IP. The WIZ control
On Tue, Feb 28, 2023 at 07:19:09PM +0100, Jan Kiszka wrote:
> From: Su Baocheng
>
> Due to different signature keys, the PG1 and the PG2 boards can no
> longer use the same FSBL (tiboot3). This makes it impossible anyway to
> maintaine a single flash.bin for both variants, so we can also split
> The usage of DM_PMIC is preferred, so convert to it.
> This also brings the benefit of causing a significant amount
> of code removal.
> Signed-off-by: Fabio Estevam
> Reviewed-by: Peng Fan
Applied to u-boot-imx, next, thanks !
Best regards,
Stefano Babic
--
> Before moving the lifecycle to OEM closed, confirm the lifecycle is
> OEM open, otherwise cancel to move forward the lifecycle.
> Signed-off-by: Ye Li
> Reviewed-by: Peng Fan
Applied to u-boot-imx, next, thanks !
Best regards,
Stefano Babic
--
> The conversion to DM_SERIAL is mandatory, so add support
> for it.
> Signed-off-by: Fabio Estevam
Applied to u-boot-imx, next, thanks !
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH,Managing
> The conversion to DM_SERIAL is mandatory, so add support
> for it.
> Signed-off-by: Fabio Estevam
Applied to u-boot-imx, next, thanks !
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH,Managing
> The conversion to DM_SERIAL is mandatory, so add support
> for it.
> Signed-off-by: Fabio Estevam
Applied to u-boot-imx, next, thanks !
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH,Managing
> The usage of DM_PMIC is preferred, so convert to it.
> This also brings the benefit of causing a significant amount
> of code removal.
> Signed-off-by: Fabio Estevam
> Reviewed-by: Peng Fan
Applied to u-boot-imx, next, thanks !
Best regards,
Stefano Babic
--
> The conversion to DM_SERIAL is mandatory, so add support
> for it.
> Signed-off-by: Fabio Estevam
Applied to u-boot-imx, next, thanks !
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH,Managing
> Remove legacy command definitions, change to use new ELE_xxx command
> request.
> Signed-off-by: Ye Li
> Reviewed-by: Peng Fan
Applied to u-boot-imx, next, thanks !
Best regards,
Stefano Babic
--
=
DENX Software Engineering
> The conversion to DM_I2C is mandatory, so add support
> for it.
> Signed-off-by: Fabio Estevam
Applied to u-boot-imx, next, thanks !
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH,Managing Director:
> The OEM Secure World Closed is not a valid lifecycle on iMX8ULP/iMX9.
> So remove it from lifecycle print.
> Signed-off-by: Ye Li
> Reviewed-by: Peng Fan
Applied to u-boot-imx, next, thanks !
Best regards,
Stefano Babic
--
> The conversion to DM_SERIAL is mandatory, so add support
> for it.
> Signed-off-by: Fabio Estevam
Applied to u-boot-imx, next, thanks !
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH,Managing
> Add get_events API to retrieve any singular events that has occurred
> since the FW has started from sentinel
> Signed-off-by: Ye Li
> Reviewed-by: Peng Fan
Applied to u-boot-imx, next, thanks !
Best regards,
Stefano Babic
--
> Use common file ele_ahab.c for i.MX9 and iMX8ULP AHAB support, since
> both of them use same sentinel ELE APIs
> Signed-off-by: Ye Li
> Reviewed-by: Peng Fan
Applied to u-boot-imx, next, thanks !
Best regards,
Stefano Babic
--
> Originally, the mmc aliases node was present in imx6qdl-pico.dtsi.
>
> After the sync with Linux in commit d0399a46e7cd ("imx6dl/imx6qdl:
> synchronise device trees with linux"), the aliases node is gone as
> the upstream version does not have it.
>
> This causes a boot regression in
> For ahab_status command, support to get and decode AHAB events
> Signed-off-by: Ye Li
> Reviewed-by: Peng Fan
Applied to u-boot-imx, next, thanks !
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH,
> I don't have access to the mx6sxsabreauto board, so remove myself
> from the MAINTAINERS entry and add Peng instead.
> Signed-off-by: Fabio Estevam
> Acked-by: Peng Fan
Applied to u-boot-imx, next, thanks !
Best regards,
Stefano Babic
--
On Tue, Mar 28, 2023 at 11:54 AM Tom Rini wrote:
>
> Per the GCC bug listed below, the way we do linker lists is relying on
> undefined behavior that seems to work in gcc, but doesn't always work in
> clang. Andrew suggests rewriting our start/end macros in a different way
> (as implemented here,
> In both SPL and u-boot, after probing the S400 MU, get the chip revision,
> lifecycle and UID from Sentinel.
> Update get_cpu_rev to use the chip revision not hard coded it for A0
> Signed-off-by: Ye Li
> Reviewed-by: Peng Fan
Applied to u-boot-imx, -next, thanks !
Best regards,
Stefano Babic
> From: Jacky Bai
> Update the dram timing to support PLL bypass mode
> for F1.
> Signed-off-by: Jacky Bai
> Reviewed-by: Ye Li
Applied to u-boot-imx, -next, thanks !
Best regards,
Stefano Babic
--
=
DENX Software
> From: Peng Fan
> To clean the upower codes by aligning codes format, check err_code
> and add detail bits list for the memory magic number
> Reviewed-by: Ye Li
> Signed-off-by: Peng Fan
Applied to u-boot-imx, -next, thanks !
Best regards,
Stefano Babic
--
> From: Peng Fan
> The swton indicates the logic switch, magic number 0xfff80 is hard
> to understand, so use macro.
> Some board design may not have MIPI_CSI voltage input connected per
> data sheet. In that case, the upower power on API may dead loop mu to wait
> response, however there is no
> At present, in cgc1_pll3_init we don't set the pll3pfd div values,
> just use the default 0. But on A1 part, ROM will set PLL3 pfd1div2
> to 1 and pfd2div1 to 3.
> This finally causes some clocks' rate decreased, for example USDHC.
> So clear the PLL3DIV_PFD dividers to get correct rate.
>
> To fit the DBD_EN fused part, we re-design the TRDC and XRDC assignment.
> M33 will be the TRDC owner and needs to configure TRDC. A35 is the
> XRDC owner, ATF will configure XRDC.
> The handshake between U-boot and M33 image is used to sync TRDC and
> XRDC configuration completion. Once the
> When using dual boot mode, the DDR won't be reset when APD power off
> or reboot. It has possibility that obsolete fdt data existing on
> fdt_addr_r address. Then even nothing in EFI partitions, the distro boot
> still continue to parse fdt and get uboot crashed.
> Clear the data at fdt_addr_r,
> To resolve DCNANO underrun issue, change the DDR Port 0 arbitration
> from round robin fashion to fixed priority level 1, while other ports
> are not assigned any priority, so they will be serviced in round robin
> fashion if there is no active request from Port 0.
> Signed-off-by: Ye Li
>
> Need to add DRAM access permission for S400, as S400 needs to access
> it When SPL calls image authentication
> Signed-off-by: Ye Li
> Reviewed-by: Peng Fan
Applied to u-boot-imx, -next, thanks !
Best regards,
Stefano Babic
--
> From Sentinel FW v0.0.9-9df0f503, the response message of get info API
> is changed to add OEM SRK and some states (IMEM, CSAL, TRNG).
> With old structure, we get failure from sentinel due to the buffer
> size can't fit with new response message. So update the API structure
> to fix the issue.
> From: Jacky Bai
> Update the ddr init flow to support LPDDR3 and PLL bypass mode.
> Signed-off-by: Jacky Bai
> Reviewed-by: Ye Li
Applied to u-boot-imx, -next, thanks !
Best regards,
Stefano Babic
--
=
DENX Software
> Since A1 ROM has fixed the ROM API eMMC issue, we should only use
> the workaround for A0.1 part. Add a SOC revision check.
> Signed-off-by: Ye Li
> Reviewed-by: Peng Fan
Applied to u-boot-imx, -next, thanks !
Best regards,
Stefano Babic
--
> To align with ARM trusted firmware's change, adjust DRAM timing
> save area to new position 0x20055000. So we can release the space
> since 0x2006c000 for the NOBITS region of ARM trusted firmware
> Signed-off-by: Ye Li
> Reviewed-by: Jacky Bai
Applied to u-boot-imx, -next, thanks !
Best
> iMX8ULP A1 S400 ROM removes the setting for MRC4/5. So we have to set
> them in SPL to allow access to DDR from A35 and APD PER masters
> Signed-off-by: Ye Li
> Reviewed-by: Peng Fan
Applied to u-boot-imx, -next, thanks !
Best regards,
Stefano Babic
--
> Update PLL3/PLL4 PFD and USDHC clocks to meet maximum frequency
> restrictions. Detail clock rate changes in the patch:
> PLL3 PFD2: 389M -> 324M
> PLL3 PFD3: 336M -> 389M
> PLL3 PFD3: DIV1 336M -> 389M (OD), 194M (ND/LD)
> PLL3 PFD3: DIV2 336M -> 194M (OD), 97M (ND/LD)
> PLL4 PFD0: 792M -> 594M
> Since latest DTS has added multiple MU nodes, using compatible
> string to find the device node is not proper. It finds the first
> node with the compatible string matched even the node is disabled.
> Signed-off-by: Ye Li
Applied to u-boot-imx, -next, thanks !
Best regards,
Stefano Babic
--
> This patch is used to support DBD owner fuse changed to S400 only.
> The XRDC PDAC2 for LPAV pbridge5 and MSC1/2/3 for GPIO and LPAV are not
> configured by S400 default setting. So these PDAC and MSC are invalid,
> only DBD owner can access the corresponding resources.
> We have to configure
> Some space in SRAM0 will be protected by S400 to allow RX SecPriv mode
> access only for boot purpose. Since SW will reuse the SRAM0 as SCMI
> buffer and SPL container loading buffer, need to reconfigure MRC3.
> Signed-off-by: Ye Li
> Reviewed-by: Peng Fan
Applied to u-boot-imx, -next, thanks
> Since new 8ULP A1 S400 FW (v0.0.8-e329b760) can support to read
> more fuses: like PMU trim, Test flow/USB, GP1-5, GP8-10. Update
> the u-boot driver for the new mapping.
> Signed-off-by: Ye Li
> Reviewed-by: Peng Fan
> Reviewed-by: Alice Guo
Applied to u-boot-imx, -next, thanks !
Best
> As M33 is responsible for TRDC configuration, the settings for A35
> nonsecure world access and DMA0 access are moved to M33 image.
> So remove the codes to release TRDC and configure it. Just keep
> the configurations for reference.
> Signed-off-by: Ye Li
> Reviewed-by: Jacky Bai
Applied to
> From: Peng Fan
> Bit0: Port 0 behavior when bandwidth maximized. Set to 1 to allow overflow
> With overflow set, we see some issue that A35 may not able to get enough
> bandwidth and A35 will report hrtimer takes too much time, workqueue
> lockup. With overflow cleared, the issues are gone.
>
> Remove the DDR initialization codes from board and enable the iMX8ULP
> DDR driver.
> Signed-off-by: Ye Li
Applied to u-boot-imx, -next, thanks !
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH, Managing
> The ECC fuse on 8ULP can't be written twice. If any user did it, the
> ECC value would be wrong then cause accessing problem to the fuse.
> The patch will lock the ECC fuse word to avoid this problem.
> For iMX9, the OTP controller automatically prevents an ECC fuse word to
> be written twice.
On Wed, 29 Mar 2023 at 05:12, Abdellatif El Khlifi
wrote:
>
> add support for x0-x17 registers used by the SMC calls
>
> In SMCCC v1.2 [1] arguments are passed in registers x1-x17.
> Results are returned in x0-x17.
>
> This work is inspired from the following kernel commit:
>
> arm64: smccc: Add
Hi Stefan,
On Tue, 28 Mar 2023 at 20:29, Stefan Herbrechtsmeier
wrote:
>
> Hi,
>
> what is the correct way to clear a local variable in the hush shell? The
> "c=" doesn't work because the commit "common: cli_hush: avoid dead code"
> (aa722529635c16c52d9d609122fecc96ec8d03e4) explicitly change
Hi Eugen,
On Wed, 29 Mar 2023 at 02:01, Eugen Hristev wrote:
>
> Some devices share a regulator supply, when the first one will request
> regulator disable, the second device will have it's supply cut off before
> graciously shutting down. Hence there will be timeouts and other failed
>
Hi Pali,
On Thu, 30 Mar 2023 at 08:32, Pali Rohár wrote:
>
> PING? Are we going to celebrate anniversary of this patch as it stay without
> comment?
>
Who is the maintainer for PowerPC? It should have been picked a long time ago?
Regards,
Simon
> On Monday 16 May 2022 11:01:19 Pali Rohár
On Wed, 29 Mar 2023 at 07:55, Tom Rini wrote:
>
> Per the GCC bug listed below, the way we do linker lists is relying on
> undefined behavior that seems to work in gcc, but doesn't always work in
> clang. Andrew suggests rewriting our start/end macros in a different way
> (as implemented here,
Hi Yanhong,
On Wed, 29 Mar 2023 at 23:29, Yanhong Wang
wrote:
>
> The StarFive ETHQOS hardware has its own clock and reset,so add a
> corresponding glue driver to configure them.
>
> Signed-off-by: Yanhong Wang
> ---
> drivers/net/Kconfig| 7 +
> drivers/net/Makefile
Hi,
On Wed, 29 Mar 2023 at 23:40, Devarsh Thakkar wrote:
>
> Hi Nikhil,
>
> Thanks for the series.
> On 29/03/23 16:00, Nikhil M Jain wrote:
> > To enable splash screen at SPL stage move video driver and splash screen
> > framework at SPL, which will bring up image on display very quickly and
>
Hi,
On Tue, 28 Mar 2023 at 10:16, wrote:
>
> From: Masami Hiramatsu
>
> Add 'mkfwumdata' tool to generate FWU metadata image for the meta-data
> partition to be used in A/B Update imeplementation.
>
> Signed-off-by: Masami Hiramatsu
> Signed-off-by: Sughosh Ganu
> Signed-off-by: Jassi Brar
>
On Wed, 29 Mar 2023 at 05:12, Abdellatif El Khlifi
wrote:
>
> provide a test case
>
> Signed-off-by: Abdellatif El Khlifi
> Cc: Simon Glass
> ---
> MAINTAINERS | 5 +
> test/lib/Makefile | 1 +
> test/lib/uuid.c | 44
> 3 files
Hi Heinrich,
On Wed, 29 Mar 2023 at 05:43, Heinrich Schuchardt wrote:
>
> On 3/27/23 21:34, Simon Glass wrote:
> > The second call to cli_ch_process() is in the wrong place, meaning that
> > the one of the characters of an invalid escape sequence is swallowed
> > instead of being returned.
> >
>
PING? Are we going to celebrate anniversary of this patch as it stay without
comment?
On Monday 16 May 2022 11:01:19 Pali Rohár wrote:
> CZ.NIC Turris 1.0 and 1.1 are open source routers, they have dual-core
> PowerPC Freescale P2020 CPU and are based on Freescale P2020RDB-PC-A board.
>
>
This allows image type print_header() callback to access struct
image_tool_params *params.
Signed-off-by: Pali Rohár
---
tools/aisimage.c | 2 +-
tools/atmelimage.c| 2 +-
tools/default_image.c | 7 ++-
tools/fit_common.c| 5 +
tools/fit_common.h| 2 ++
SATA kwbimage contains offsets in block size unit, not in bytes.
Until now kwbimage expected that SATA disk always have block size of 512
bytes. But there are 4K Native SATA disks with block size of 4096 bytes.
New SATA_BLKSZ command allows to specify different block size than 512
bytes and
Currently kwboot expected that sector size for SATA image is always 512
bytes. If SATA image cannot be parsed with sector size of 512 bytes, try
larger sector sizes which are power of two and up to the 32 kB. Maximal
theoretical value is 32 kB because ATA IDENTIFY command returns sector size
as
Add a new config option CONFIG_MVEBU_SPL_SATA_BLKSZ for specifying block
size of SATA disk. This information is used during building of SATA
kwbimage and must be correctly set, otherwise BootROM does not load SPL.
For 4K Native disks CONFIG_MVEBU_SPL_SATA_BLKSZ must be set to 4096.
Replace repeated code patterns by generic code.
Signed-off-by: Pali Rohár
---
tools/kwbimage.c | 48
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index 8e573d9eea37..360feddad195 100644
---
Find SATA block device by blk_get_devnum_by_uclass_id() function and read
from it the real block size of the SATA disk.
Signed-off-by: Pali Rohár
---
arch/arm/mach-mvebu/spl.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-mvebu/spl.c
This patch series allows to build SATA kwbimage for disks which do not
have sector size 512 bytes long. For example 4K Native disks.
SATA kwbimage differs from other kwbimage types in that way, that offset
in its header is stored in SATA sectors units instead of byte units.
Therefore image
Find SATA block device by blk_get_devnum_by_uclass_id() function and read
from it the real block size of the SATA disk.
Signed-off-by: Pali Rohár
---
cmd/mvebu/bubt.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/cmd/mvebu/bubt.c b/cmd/mvebu/bubt.c
index
Disassembling A385 BootROM binary reveal how BootROM interprets strapping
pins for Boot Device Mode. All possible options are:
0x00..0x07 -> Parallel NOR
0x08..0x15 -> Parallel NAND
0x16..0x17 -> Parallel NOR
0x18..0x25 -> Parallel NAND
0x26..0x27 -> SPI NAND
0x28..0x29 -> UART xmodem
0x2a..0x2b
A385 BootROM treats strapping configuration 0x22 as SPI-NAND. So remove
incorrect definition 0x22 as SATA. SATA on A385 has configuration 0x2A.
Signed-off-by: Pali Rohár
Tested-by: Tony Dinh
Tested-by: Martin Rowe
---
arch/arm/mach-mvebu/cpu.c | 1 -
A385 BootROM fills into bits [31:28] of register 0x182d0 tracing value,
which represents in which state BootROM currently is. BootROM fills one
of the possible values: 0x2 (CPU initialization), 0x3 (UART detection),
0x6 (UART booting), 0x8 (PCI Express booting), 0x9 (parallel or SPI NOR
booting),
A385 BootROM treats strapping configuration 0x3f as invalid. When booting
fails (e.g. because of invalid configuration) then BootROM fallbacks to
UART booting.
Detecting BootROM fallback to UART booting is implemented in U-Boot since
commit 2fd4284051e3 ("ARM: mach-mvebu: handle fall-back to UART
Definitions are according to the MV78460 Hardware Specifications.
Signed-off-by: Pali Rohár
Tested-by: Tony Dinh
Tested-by: Martin Rowe
---
arch/arm/mach-mvebu/include/mach/soc.h | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h
This allows to merge BOOT_FROM_MMC and BOOT_FROM_MMC_ALT constants to one
macro. And also allows to extend other BOOT_FROM_* macros for other
variants.
Signed-off-by: Pali Rohár
Tested-by: Tony Dinh
Tested-by: Martin Rowe
---
arch/arm/mach-mvebu/cpu.c | 20 ++--
Improve code for checking strapping pins which specifies boot mode source.
v2 is same as v1 with compile fix and rebased on top of next branch.
Pali Rohár (6):
arm: mvebu: Remove A38x BOOT_FROM_UART_ALT 0x3f constant
arm: mvebu: Remove A38x BOOT_FROM_SATA 0x22 constant
arm: mvebu: Convert
On Tue, Mar 21, 2023 at 10:13:09PM +0100, Linus Walleij wrote:
> For BRCMNAND with 1-bit BCH ECC (BCH-1) such as used on the
> D-Link DIR-885L and DIR-890L routers, we need to explicitly
> select the ECC like this in the device tree:
>
> nand-ecc-algo = "bch";
> nand-ecc-strength = <1>;
>
Hello!
On Wednesday 29 March 2023 18:01:41 Minda Chen wrote:
> From: Mason Huo
>
> Add pcie driver for StarFive JH7110, the driver depends on
> starfive gpio, pinctrl, clk and reset driver to do init.
>
> Several devices are tested:
> a) M.2 NVMe SSD
> b) Realtek 8169 Ethernet adapter.
>
>
to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url:
https://github.com/intel-lab-lkp/linux/commits/Torsha-Banerjee/Series-to-Fred-Bloggs-f-blogs-napier-co-nz-Series-cc-Sean-O-Brien-seobrien-chromium-org-HID-input-Restore-missing-cursor/20230329
On Mon, Mar 27, 2023 at 06:50:41PM +0100, Peter Robinson wrote:
> On Mon, Mar 27, 2023 at 5:02 AM Simon Glass wrote:
> >
> > Hi Tom,
> >
> > On Sat, 25 Mar 2023 at 09:58, Tom Rini wrote:
> > >
> > > Hey all,
> > >
> > > I took a look at Simon's v3 series to fix the rk3399 bootstd migration,
> >
From: Will Deacon
In preparation for bouncing virtio data for devices advertising the
VIRTIO_F_IOMMU_PLATFORM feature, allocate an array of bounce buffer
structures in the vring, one per descriptor.
Signed-off-by: Will Deacon
[ Paul: pick from the Android tree. Rebase to the upstream ]
From: Will Deacon
Devices advertising the VIRTIO_F_IOMMU_PLATFORM feature require
platform-specific handling to configure their DMA transactions.
When handling virtio descriptors for such a device, use bounce
buffers to ensure that the underlying buffers are always aligned
to and padded to
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