On Tue, Dec 6, 2011 at 11:35 AM, Wolfgang Denk w...@denx.de wrote:
Dear Anton Staaf,
In message
caf6fioweof1rwckrfwusobcybwu4g4xp84proirb5hcbfjk...@mail.gmail.com you
wrote:
Whimper whimper. This is silly, what happened was that two different
patches collided when committed. Mine had
On Fri, Dec 2, 2011 at 1:59 PM, Simon Glass s...@chromium.org wrote:
Hi Graeme,
On Fri, Dec 2, 2011 at 1:28 PM, Graeme Russ graeme.r...@gmail.com wrote:
Hi Anton,
On 30/11/11 10:39, Gabe Black wrote:
The ALLOC_CACHE_ALIGN_BUFFER macro allocates a pointer to a buffer, and the
address of the
Tested-by: Anton Staaf robot...@chromium.org
Mike, do you think you could pull this into staging as per Wolfgang's
recent request for help?
Thanks,
Anton
On Sun, Oct 30, 2011 at 8:44 AM, Mike Frysinger vap...@gentoo.org wrote:
Acked-by: Mike Frysinger vap...@gentoo.org
-mike
On Mon, Nov 14, 2011 at 7:19 AM, Sanjeev Premi pr...@ti.com wrote:
Fix errors noticed after enabling CONFIG_EFI_PARTITION
for the OMAP3 EVM board:
There is already a patch for this waiting to be committed.
Thanks,
Anton
part_efi.c: In function 'print_part_efi':
part_efi.c:133:5:
On Thu, Nov 10, 2011 at 8:28 AM, Tom Warren twar...@nvidia.com wrote:
Anton,
-Original Message-
From: Anton Staaf [mailto:robot...@chromium.org]
Sent: Wednesday, November 09, 2011 12:46 PM
To: u-boot@lists.denx.de
Cc: Anton Staaf; Andy Fleming; Tom Warren; Stephen Warren; Albert
the next address that would have
been read/written when a boundary is hit. So we can read that
and write it back. The write triggers the resumption of the
transfer.
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Andy Fleming aflem...@gmail.com
Cc: Tom Warren twar...@nvidia.com
Cc: Stephen
values
- Remove patches for bounce buffer implementation
Changes in v3:
- Added back comments about register values
- Shortened #defined macro names
Anton Staaf (4):
Tegra2: mmc: define register field values in tegra2_mmc.h
Tegra2: mmc: Support DMA restarts at buffer boundaries
Tegra2: mmc
This moves the magic numbers sprinkled about the MMC driver
to a single location in the header file and gives them
meaningful names.
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Andy Fleming aflem...@gmail.com
Cc: Tom Warren twar...@nvidia.com
Cc: Stephen Warren swar...@nvidia.com
Cc
This is a well encapsulated section of mmc_send_cmd, by moving
it to it's own function it increases the readability of mmc_send_cmd.
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Andy Fleming aflem...@gmail.com
Cc: Tom Warren twar...@nvidia.com
Cc: Stephen Warren swar...@nvidia.com
Cc
and we fail out.
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Andy Fleming aflem...@gmail.com
Cc: Tom Warren twar...@nvidia.com
Cc: Stephen Warren swar...@nvidia.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
---
drivers/mmc/tegra2_mmc.c | 14 ++
1 files changed, 14
values
- Remove patches for bounce buffer implementation
Anton Staaf (4):
Tegra2: mmc: define register field values in tegra2_mmc.h
Tegra2: mmc: Support DMA restarts at buffer boundaries
Tegra2: mmc: Add data transfer completion timeout
Tegra2: mmc: Factor out mmc_wait_inhibit functionality
This is a well encapsulated section of mmc_send_cmd, by moving
it to it's own function it increases the readability of mmc_send_cmd.
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Andy Fleming aflem...@gmail.com
Cc: Tom Warren twar...@nvidia.com
Cc: Stephen Warren swar...@nvidia.com
Cc
and we fail out.
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Andy Fleming aflem...@gmail.com
Cc: Tom Warren twar...@nvidia.com
Cc: Stephen Warren swar...@nvidia.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
---
drivers/mmc/tegra2_mmc.c | 14 ++
1 files changed, 14
the next address that would have
been read/written when a boundary is hit. So we can read that
and write it back. The write triggers the resumption of the
transfer.
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Andy Fleming aflem...@gmail.com
Cc: Tom Warren twar...@nvidia.com
Cc: Stephen
This moves the magic numbers sprinkled about the MMC driver
to a single location in the header file and gives them
meaningful names.
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Andy Fleming aflem...@gmail.com
Cc: Tom Warren twar...@nvidia.com
Cc: Stephen Warren swar...@nvidia.com
Cc
On Wed, Nov 2, 2011 at 6:08 PM, Andy Fleming aflem...@gmail.com wrote:
On Thu, Oct 13, 2011 at 4:57 PM, Anton Staaf robot...@chromium.org wrote:
diff --git a/drivers/mmc/tegra2_mmc.c b/drivers/mmc/tegra2_mmc.c
index 8b6f829..195f89d 100644
--- a/drivers/mmc/tegra2_mmc.c
+++ b/drivers/mmc
I'm new to patchwork, and am wondering.
Who should change the state of patches there? Should I mark patches
that have been applied as Accepted? Or should the tree maintainer do
that?
Also, should I delegate patches to custodians that I believe should be
looking at them? Or should custodians
On Fri, Oct 28, 2011 at 10:16 AM, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Hi Anton,
Le 28/10/2011 18:52, Anton Staaf a écrit :
I'm new to patchwork, and am wondering.
Who should change the state of patches there? Should I mark patches
that have been applied as Accepted? Or should
On Thu, Oct 13, 2011 at 2:57 PM, Anton Staaf robot...@chromium.org wrote:
Currently when no expected completion condition occures in the
mmc_send_cmd while loop that is waiting for a data transfer to
complete the MMC driver just hangs.
This patch adds an arbitrary 2 second timeout
On Thu, Oct 13, 2011 at 2:57 PM, Anton Staaf robot...@chromium.org wrote:
Currently if a DMA buffer straddles a buffer alignment boundary
(512KiB) then the DMA engine will pause and generate a DMA
interrupt. Since the DMA interrupt is not enabled it will hang
the MMC driver.
This patch adds
On Thu, Oct 13, 2011 at 2:57 PM, Anton Staaf robot...@chromium.org wrote:
This is a well encapsulated section of mmc_send_cmd, by moving
it to it's own function it increases the readability of mmc_send_cmd.
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Tom Warren twar...@nvidia.com
Cc
Thanks Stephen, sorry Doug. :)
-Anton
On Fri, Oct 28, 2011 at 12:43 PM, Doug Anderson diand...@chromium.org wrote:
Acked-by: Doug Anderson diand...@chromium.org
...to be fair though, the regression appears to be caused by a mid-air
collision of Anton's change
Just realized that I broke the sandbox build by requiring an
asm/cache.h file in common.h. I'll send a patch to fix it.
-Anton
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
This file is required by the new DMA buffer alignment macro.
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Simon Glass s...@chromium.org
---
arch/sandbox/include/asm/cache.h | 33 +
1 files changed, 33 insertions(+), 0 deletions(-)
create mode 100644
On Mon, Oct 24, 2011 at 2:46 AM, Macpaul Lin macp...@andestech.com wrote:
Add ARCH_DMA_MINALIGN definition to asm/cache.h
Signed-off-by: Macpaul Lin macp...@andestech.com
Acked-by: Anton Staaf robot...@chromium.org
---
arch/nds32/include/asm/cache.h | 11 +++
1 files changed, 11
On Mon, Oct 17, 2011 at 4:46 PM, Anton Staaf robot...@chromium.org wrote:
ARCH_DMA_MINALIGN is a new define borrowed from the Linux kernel. It is
used to define the minimum alignement requirement for a DMA buffer. This
series of patches ensures that it will always be defined in the arch
On Mon, Oct 24, 2011 at 12:45 PM, Wolfgang Denk w...@denx.de wrote:
Dear Anton Staaf,
In message
CAF6FioXuWF5ar4G9x6JsHw0n6VyWE=6o5zj0m8deposot7h...@mail.gmail.com you
wrote:
I have now run MAKEALL for both ARMv7a and PowerPC successfully.
There were a number of
build failures
On Wed, Oct 12, 2011 at 4:55 PM, Anton Staaf robot...@chromium.org wrote:
The cache line alignment issue has gone around a couple of times now. This
patch set implements all of the details that we have discussed about the
implementation of ALLOC_CACHE_ALIGN_BUFFER. It also includes patches
On Tue, Oct 18, 2011 at 7:05 AM, Simon Glass s...@chromium.org wrote:
Hi,
On Tue, Oct 18, 2011 at 2:44 AM, Wolfgang Denk w...@denx.de wrote:
Dear Andreas,
In message 4e9d4552.5040...@gmail.com you wrote:
We should first get a state of all boards build clean for a sort of
toolchains (I
On Mon, Oct 17, 2011 at 11:23 PM, Wolfgang Denk w...@denx.de wrote:
Hi all,
the patches that have been submitted for this release turn out to of
of shockingly bad quality. About every other batch of patches I apply
will break building not only for a single board r a few boards, but
for
On Tue, Oct 18, 2011 at 10:44 AM, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Le 18/10/2011 19:16, Anton Staaf a écrit :
I would like to start a thread addressing this question. I don't think
the people submitting are running MAKEALL because it has a very high
barrier to entry
On Mon, Oct 17, 2011 at 4:42 AM, Lukasz Majewski l.majew...@samsung.com wrote:
Define the D-cache line size for S5PC110 GONI reference target.
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Acked-by: Anton Staaf robot
On Mon, Oct 17, 2011 at 4:42 AM, Lukasz Majewski l.majew...@samsung.com wrote:
Define the D-cache line size for S5PC210 UNIVERSAL reference target.
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Acked-by: Anton Staaf robot
blackfin patches in favor of Mike's import of the Linux kernel cache.h
- Remove all Gerrit Change-ID tags
Anton Staaf (11):
arm: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
m68k: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
nios2: cache: define ARCH_DMA_MINALIGN for DMA
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Mike Frysinger vap...@gentoo.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Michal Simek mon...@monstr.eu
---
arch/microblaze/include/asm/cache.h | 37 +++
1 files changed, 37 insertions(+), 0 deletions
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Mike Frysinger vap...@gentoo.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Jason Jin jason@freescale.com
---
arch/m68k/include/asm/cache.h | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/m68k
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Mike Frysinger vap...@gentoo.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Albert ARIBAUD albert.u.b...@aribaud.net
---
arch/arm/include/asm/cache.h | 11 +++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/arch
Signed-off-by: Anton Staaf robot...@chromium.org
Acked-by: Stefan Roese s...@denx.de
Cc: Mike Frysinger vap...@gentoo.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Wolfgang Denk w...@denx.de
Cc: Stefan Roese s...@denx.de
---
arch/powerpc/include/asm/cache.h |6 ++
1 files changed, 6
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Mike Frysinger vap...@gentoo.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Nobuhiro Iwamatsu iwama...@nigauri.org
---
arch/sh/include/asm/cache.h | 17 +
1 files changed, 17 insertions(+), 0 deletions(-)
diff --git
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Mike Frysinger vap...@gentoo.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Shinya Kuribayashi skuri...@pobox.com
---
arch/mips/include/asm/cache.h | 36
1 files changed, 36 insertions(+), 0 deletions
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Mike Frysinger vap...@gentoo.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Daniel Hellstrom dan...@gaisler.com
---
arch/sparc/include/asm/cache.h | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/sparc
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Mike Frysinger vap...@gentoo.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Graeme Russ graeme.r...@gmail.com
---
arch/x86/include/asm/cache.h | 35 +++
1 files changed, 35 insertions(+), 0 deletions
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Mike Frysinger vap...@gentoo.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Reinhard Meyer u-b...@emk-elektronik.de
---
arch/avr32/include/asm/cache.h | 40
1 files changed, 40 insertions(+), 0
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Mike Frysinger vap...@gentoo.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Scott McNutt smcn...@psyent.com
---
arch/nios2/include/asm/cache.h | 11 +++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/arch/nios2
cache line size then the
maximum line size of the architecture is used to align DMA buffers.
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Mike Frysinger vap...@gentoo.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Wolfgang Denk w...@denx.de
Cc: Stefano Babic sba...@denx.de
Cc: Ilya
On Fri, Oct 14, 2011 at 9:26 AM, Simon Glass s...@chromium.org wrote:
Hi Tom Stephen,
On Fri, Oct 14, 2011 at 9:02 AM, Stephen Warren swar...@nvidia.com wrote:
Tom Warren wrote at Friday, October 14, 2011 9:56 AM:
Stephen Warren wrote at Friday, October 14, 2011 8:04 AM:
Simon Glass wrote
On Wed, Oct 12, 2011 at 8:47 PM, Kumar Gala ga...@kernel.crashing.org wrote:
On Oct 12, 2011, at 4:01 PM, Anton Staaf wrote:
ARCH_DMA_MINALIGN is a new define borrowed from the Linux kernel. It is
used to define the minimum alignement requirement for a DMA buffer. This
series of patches
On Wed, Oct 12, 2011 at 5:55 PM, Mike Frysinger vap...@gentoo.org wrote:
On Wednesday 12 October 2011 19:55:59 Anton Staaf wrote:
doc/README.arm-caches | 2 +
seems like most of the advice in this is arch independent
Agreed. It probably makes sense to change the name of the file. I'm
On Thu, Oct 13, 2011 at 11:15 AM, Mike Frysinger vap...@gentoo.org wrote:
On Thursday 13 October 2011 14:06:41 Anton Staaf wrote:
On Wed, Oct 12, 2011 at 5:55 PM, Mike Frysinger wrote:
On Wednesday 12 October 2011 19:55:59 Anton Staaf wrote:
doc/README.arm-caches | 2 +
seems like
On Thu, Oct 13, 2011 at 1:03 PM, Wolfgang Denk w...@denx.de wrote:
Dear Anton Staaf,
In message
caf6fiowhpea8_npa85e3spc17zdckzqkv2ros_eaab_9wv9...@mail.gmail.com you
wrote:
Would you be OK with a build warning for the lack of definition of
CONFIG_SYS_CACHELINE_SIZE like I have now
On Thu, Oct 13, 2011 at 1:31 PM, Wolfgang Denk w...@denx.de wrote:
Dear Anton Staaf,
In message
CAF6FioWnYJNBz0+4Af3-0vLCoGrgGgcN10z=k0df8yv87gu...@mail.gmail.com you
wrote:
Turns out I was able to define ARCH_DMA_MINALIGN for all U-Boot
architectures and use that
instead of the actual
On Thu, Oct 13, 2011 at 1:36 PM, Mike Frysinger vap...@gentoo.org wrote:
On Thursday 13 October 2011 16:03:37 Wolfgang Denk wrote:
Anton Staaf wrote:
... I could move it from common.h to a c file that is always
built. Perhaps I could add a checks.c file to libgeneric? I'm
and we fail out.
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Tom Warren twar...@nvidia.com
Cc: Stephen Warren swar...@nvidia.com
---
drivers/mmc/tegra2_mmc.c | 14 ++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/tegra2_mmc.c b/drivers/mmc
of this patch. :)
Anton Staaf (5):
mmc: Tegra2: Support DMA restarts at buffer boundaries
mmc: Tegra2: Add data transfer completion timeout
mmc: Tegra2: Factor out mmc_wait_inhibit functionality
mmc: Create dcache flush and invalidate convenience methods
mmc: Tegra2: Enable dcache support
This is a well encapsulated section of mmc_send_cmd, by moving
it to it's own function it increases the readability of mmc_send_cmd.
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Tom Warren twar...@nvidia.com
Cc: Stephen Warren swar...@nvidia.com
---
drivers/mmc/tegra2_mmc.c | 41
With the enabling of data caches in U-Boot flushing and invalidating MMC
buffers will need to be done in all MMC drivers. These utility functions
simplify that task slightly.
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Andy Fleming aflem...@gmail.com
---
drivers/mmc/mmc.c | 23
the bounce buffer and has a high water mark in memory
consumption.
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Tom Warren twar...@nvidia.com
Cc: Stephen Warren swar...@nvidia.com
---
drivers/mmc/tegra2_mmc.c | 132 -
drivers/mmc/tegra2_mmc.h
the next address that would have
been read/written when a boundary is hit. So we can read that
and write it back. The write triggers the resumption of the
transfer.
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Tom Warren twar...@nvidia.com
Cc: Stephen Warren swar...@nvidia.com
On Thu, Oct 13, 2011 at 2:57 PM, Anton Staaf robot...@chromium.org wrote:
When an unaligned buffer is used for DMA the first and last few
bytes of the buffer would be clobbered by the dcache invalidate
call that is required to make the contents of the buffer visible
to the CPU post DMA. The U
On Tue, Oct 11, 2011 at 5:35 PM, Simon Glass s...@chromium.org wrote:
This enables the data cache on Tegra2 boards.
As discussed on the list, this is better off in the Tegra2 cpu code than in a
particular vendor directory. We should be safe turning on the cache for all
Tegra2 boards.
I don't
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Mike Frysinger vap...@gentoo.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Scott McNutt smcn...@psyent.com
Change-Id: I2982360f1c2ad9e8549d5b9ecdbb423d34b75157
---
arch/nios2/include/asm/cache.h | 11 +++
1 files changed, 11
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Mike Frysinger vap...@gentoo.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Michal Simek mon...@monstr.eu
Change-Id: I8ee488ae0654cebac34f4d65771b4a8edbadf6fd
---
arch/microblaze/include/asm/cache.h | 37
-Os option if --enable-target-optspace is not set.
So Tested-by's would be greatly appreciated.
Thanks,
Anton
Anton Staaf (12):
arm: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
m68k: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
nios2: cache: define
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Mike Frysinger vap...@gentoo.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Shinya Kuribayashi skuri...@pobox.com
Change-Id: Ia6cc9a950e0452926abf39867a70ec3910fbd1dd
---
arch/mips/include/asm/cache.h | 36
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Mike Frysinger vap...@gentoo.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Jason Jin jason@freescale.com
Change-Id: Ica2b7459b7a61b521116eb23dc911451b4c2a9a5
---
arch/m68k/include/asm/cache.h | 10 ++
1 files changed, 10
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Mike Frysinger vap...@gentoo.org
Cc: Lukasz Majewski l.majew...@samsung.com
Change-Id: Ibdc2483c66c50d698108b790dd204fae38c7cb48
---
arch/blackfin/include/asm/cache.h | 36
1 files changed, 36 insertions
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Mike Frysinger vap...@gentoo.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Wolfgang Denk w...@denx.de
Cc: Stefan Roese s...@denx.de
Change-Id: I5a007a515ef16e77003aaa74f9295ecc5104aa36
---
arch/powerpc/include/asm/cache.h |6 ++
1
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Mike Frysinger vap...@gentoo.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Graeme Russ graeme.r...@gmail.com
Change-Id: Ib4b497910f674904f5fd0d9557a082d661c248bb
---
arch/x86/include/asm/cache.h | 35
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Mike Frysinger vap...@gentoo.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Daniel Hellstrom dan...@gaisler.com
Change-Id: If33383ff88e0555204c4ed1534d3961587fdee3a
---
arch/sparc/include/asm/cache.h | 10 ++
1 files changed, 10
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Mike Frysinger vap...@gentoo.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Nobuhiro Iwamatsu iwama...@nigauri.org
Change-Id: I7dc5fb442b0e9173e9acdaf7acce3014c5b37625
---
arch/sh/include/asm/cache.h | 17 +
1 files
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Mike Frysinger vap...@gentoo.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Reinhard Meyer u-b...@emk-elektronik.de
Change-Id: I5965f64804c3938823be716f45298f093871fe83
---
arch/avr32/include/asm/cache.h | 40
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Mike Frysinger vap...@gentoo.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Albert ARIBAUD albert.u.b...@aribaud.net
Change-Id: If1063f66775367266a370dd60a2c0b72d3e13eee
---
arch/arm/include/asm/cache.h | 11 +++
1 files changed
cache line size then the
maximum line size of the architecture is used to align DMA buffers.
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Mike Frysinger vap...@gentoo.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Wolfgang Denk w...@denx.de
Cc: Stefano Babic sba...@denx.de
Cc: Ilya
Shoot, I just noticed that I forgot to purge the Gerrit generated Change-Id:
tags from the commit messages. If and when I send a v2 series I'll
remove these.
Thanks,
Anton
On Wed, Oct 12, 2011 at 2:01 PM, Anton Staaf robot...@chromium.org wrote:
ARCH_DMA_MINALIGN is a new define borrowed
On Wed, Oct 12, 2011 at 4:23 PM, Mike Frysinger vap...@gentoo.org wrote:
i'm just going to import Blackfin's asm/cache.h from Linux and define
CONFIG_SYS_CACHELINE_SIZE in Blackfin's asm/config.h
OK, how would you like to deal with that with respect to this patch set?
Would you like to do that
size
- Remove Gerrit generated Change-Id: tags from commit messages
- Add additional buffer alignments for mmc and part_efi code
Changes for v3:
- Don't set a default value for CONFIG_SYS_CACHELINE_SIZE
- Use ARCH_DMA_MINALIGN to align DMA buffers
Anton Staaf (6):
cache: add
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Tom Warren twarren.nvi...@gmail.com
Cc: Simon Glass s...@chromium.org
Cc: Mike Frysinger vap...@gentoo.org
Cc: Albert ARIBAUD albert.u.b...@aribaud.net
---
include/configs/tegra2-common.h |2 ++
1 files changed, 2 insertions(+), 0 deletions
for reading the
scr register and switch status values from an MMC device.
Signed-off-by: Anton Staaf robot...@chromium.org
Acked-by: Mike Frysinger vap...@gentoo.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Mike Frysinger vap...@gentoo.org
Cc: Albert ARIBAUD albert.u.b...@aribaud.net
-by: Anton Staaf robot...@chromium.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Mike Frysinger vap...@gentoo.org
Cc: Albert ARIBAUD albert.u.b...@aribaud.net
---
disk/part_efi.c | 18 +-
1 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/disk/part_efi.c b/disk
the buffers used for reading the
ext_csd data from an MMC device.
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Mike Frysinger vap...@gentoo.org
Cc: Albert ARIBAUD albert.u.b...@aribaud.net
---
drivers/mmc/mmc.c |4 ++--
1 files changed, 2
will not be aligned to the dcache line size. This is a problem
when caches are enabled because unaligned cache invalidates are not
safe.
This patch uses ALLOC_CACHE_ALIGN_BUFFER to create a stack allocated
cache line size aligned bounce buffer.
Signed-off-by: Anton Staaf robot...@chromium.org
Acked
This macro is used to allocate cache line size aligned stack
buffers for use with DMA hardware.
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Kyungmin Park kyungmin.p...@samsung.com
Cc: Mike Frysinger vap...@gentoo.org
Cc: Aneesh V ane...@ti.com
-4) != CONFIG_SYS_GBL_DATA_ADDR)
# error CONFIG_SYS_GBL_DATA_ADDR: must be 4 byte aligned
--
1.7.6.1
Acked-by: Anton Staaf robot...@chromium.org
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
branch yet ...
There are actually three parts to this storey:
Thisi s the original patch series, which I applied to a local test
branch with the intention to pull into mainline:
10/04 Anton Staaf [U-Boot] [PATCH v2 0/7] Add cache line alignment
support
http://article.gmane.org
On Mon, Oct 10, 2011 at 11:31 AM, Wolfgang Denk w...@denx.de wrote:
Dear Anton Staaf,
In message
CAF6FioWbLz9JKBnj5sJGALtj=bjylnbfvunna6fe62y42t6...@mail.gmail.com you
wrote:
When PPC was building again, I tested it on ARM (which I assumed was
OK, given that this was Anton's primary
On Mon, Oct 10, 2011 at 11:45 AM, Anton Staaf robot...@chromium.org wrote:
On Mon, Oct 10, 2011 at 11:31 AM, Wolfgang Denk w...@denx.de wrote:
Dear Anton Staaf,
In message
CAF6FioWbLz9JKBnj5sJGALtj=bjylnbfvunna6fe62y42t6...@mail.gmail.com you
wrote:
When PPC was building again, I tested
On Sun, Oct 9, 2011 at 12:11 PM, Wolfgang Denk w...@denx.de wrote:
Dear Anton Staaf,
In message
CAF6FioV3YFk02Sgp0AasYGQJSNKv=cb-sszcqr8f3s2esya...@mail.gmail.com you
wrote:
This is needed for the patch cache: add default setting for
CONFIG_SYS_CACHELINE_SIZE from Anton Staaf
On Sun, Oct 9, 2011 at 2:22 PM, Wolfgang Denk w...@denx.de wrote:
Dear Anton Staaf,
In message 1317763491-7274-1-git-send-email-robot...@chromium.org you wrote:
The cache line alignment issue has gone around a couple of times now. This
patch set implements all of the details that we have
On Fri, Oct 7, 2011 at 4:05 AM, Stefan Roese s...@denx.de wrote:
This is needed for the patch cache: add default setting for
CONFIG_SYS_CACHELINE_SIZE from Anton Staaf. As cache.h defines
CONFIG_SYS_CACHELINE_SIZE for PPC targets.
This will remove the following warnings/errors:
include
On Tue, Oct 4, 2011 at 8:14 AM, Mike Frysinger vap...@gentoo.org wrote:
On Monday, October 03, 2011 19:54:57 Anton Staaf wrote:
--- a/include/common.h
+++ b/include/common.h
/*
+ *
+ */
no comment ? :)
Doh, I knew I was forgetting something. I'll fix this today with a v2.
Thanks
-by: Anton Staaf robot...@chromium.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Mike Frysinger vap...@gentoo.org
Cc: Albert ARIBAUD albert.u.b...@aribaud.net
---
disk/part_efi.c | 18 +-
1 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/disk/part_efi.c b/disk
the buffers used for reading the
ext_csd data from an MMC device.
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Mike Frysinger vap...@gentoo.org
Cc: Albert ARIBAUD albert.u.b...@aribaud.net
---
drivers/mmc/mmc.c |4 ++--
1 files changed, 2
will not be aligned to the dcache line size. This is a problem
when caches are enabled because unaligned cache invalidates are not
safe.
This patch uses ALLOC_CACHE_ALIGN_BUFFER to create a stack allocated
cache line size aligned bounce buffer.
Signed-off-by: Anton Staaf robot...@chromium.org
Acked
This macro is used to allocate cache line size aligned stack
buffers for use with DMA hardware.
Signed-off-by: Anton Staaf robot...@chromium.org
Acked-by: Mike Frysinger vap...@gentoo.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Kyungmin Park kyungmin.p...@samsung.com
Cc: Mike Frysinger vap
for reading the
scr register and switch status values from an MMC device.
Signed-off-by: Anton Staaf robot...@chromium.org
Acked-by: Mike Frysinger vap...@gentoo.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Mike Frysinger vap...@gentoo.org
Cc: Albert ARIBAUD albert.u.b...@aribaud.net
and part_efi code
Anton Staaf (7):
cache: add ALLOC_CACHE_ALIGN_BUFFER macro
cache: add default setting for CONFIG_SYS_CACHELINE_SIZE
tegra: define CONFIG_SYS_CACHELINE_SIZE for tegra
mmc: dcache: allocate cache aligned buffer for scr and switch_status
ext2: Cache line aligned partial
if the
default is used.
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Kyungmin Park kyungmin.p...@samsung.com
Cc: Mike Frysinger vap...@gentoo.org
Cc: Aneesh V ane...@ti.com
Cc: Albert ARIBAUD albert.u.b...@aribaud.net
---
Changes for v2:
- Add comment
Signed-off-by: Anton Staaf robot...@chromium.org
Acked-by: Mike Frysinger vap...@gentoo.org
Cc: Tom Warren twarren.nvi...@gmail.com
Cc: Simon Glass s...@chromium.org
Cc: Mike Frysinger vap...@gentoo.org
Cc: Albert ARIBAUD albert.u.b...@aribaud.net
---
include/configs/tegra2-common.h |2 ++
1
of the
implementation of this fix though, and I wanted to get this discussion going
again.
Thanks,
Anton
---
Anton Staaf (5):
cache: add ALLOC_CACHE_ALIGN_BUFFER macro
cache: add default setting for CONFIG_SYS_CACHELINE_SIZE
tegra: define CONFIG_SYS_CACHELINE_SIZE for tegra
mmc: dcache
This macro is used to allocate cache line size aligned stack
buffers for use with DMA hardware.
Signed-off-by: Anton Staaf robot...@chromium.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Kyungmin Park kyungmin.p...@samsung.com
Cc: Mike Frysinger vap...@gentoo.org
Cc: Aneesh V ane...@ti.com
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