Re: [U-Boot] [PATCH 2/7] arm: socfpga: Convert FPGA configuration to Kconfig method.

On Jum, 2017-05-05 at 13:11 +0200, Marek Vasut wrote: > On 05/05/2017 12:26 PM, tien.fong.c...@intel.com wrote: > > > > From: Tien Fong Chee > > > > Convert Macro #define configuration to Kconfig method. All FPGA > > devices > > enable configuration based on

Re: [U-Boot] [PATCH] ARM: socfpga: boot0 hook: remove macro from boot0 header file

On Rab, 2017-03-29 at 11:28 +0800, tien.fong.c...@intel.com wrote: > From: "Chee, Tien Fong" <tien.fong.c...@intel.com> > > Commit ce62e57fc571 ("ARM: boot0 hook: remove macro, include whole > header file") miss out cleaning macro in this header file

Re: [U-Boot] [PATCH] ARM: socfpga: Fix broken implementation and enhancing boot header

On Sel, 2017-03-28 at 11:38 +0200, Marek Vasut wrote: > On 03/28/2017 11:25 AM, tien.fong.c...@intel.com wrote: > > > > From: "Chee, Tien Fong" <tien.fong.c...@intel.com> > > > > Fixing the broken implementation caused by the patch > > commit:ce6

Re: [U-Boot] [PATCH 1/4] arm: socfpga: Removing unused passing parameter of socfpga_bridges_reset

On Sel, 2017-03-07 at 04:45 +0100, Marek Vasut wrote: > On 03/06/2017 05:45 AM, Chee, Tien Fong wrote: > > > > On Ahd, 2017-03-05 at 01:57 +0100, Marek Vasut wrote: > > > > > > On 03/03/2017 01:50 PM, Chee Tien Fong wrote: > > > > > > > >

Re: [U-Boot] [PATCH 1/4] arm: socfpga: Removing unused passing parameter of socfpga_bridges_reset

On Ahd, 2017-03-05 at 01:57 +0100, Marek Vasut wrote: > On 03/03/2017 01:50 PM, Chee Tien Fong wrote: > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > This patch removes the unused passing parameter of > > socfpga_bridges_reset > > func

Re: [U-Boot] [PATCH 0/4] Add Intel Arria 10 SoC FPGA driver

On Jum, 2017-03-03 at 20:50 +0800, Chee Tien Fong wrote: > From: Tien Fong Chee <tien.fong.c...@intel.com> > > This patchset adds FPGA driver to Intel Arria 10 SoC. > > This series is working on top of [1] initial patchset which enables > the basic > support for

[U-Boot] [PATCH 4/4] arm: socfpga: Add FPGA driver support for Arria 10

From: Tien Fong Chee Add FPGA driver support for Arria 10. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Ching Liang See Cc: Ley Foon

[U-Boot] [PATCH 3/4] arm: socfpga: Add Arria10 FPGA manager program assembly driver

From: Tien Fong Chee This patch adding the Arria10 FPGA manager program assembly driver which can be used for feeding bitstream to configure FPGA. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen

[U-Boot] [PATCH 2/4] arm: socfpga: Restructure FPGA driver in the preparation to support A10.

From: Tien Fong Chee Move the Gen5 specific code to gen5 files. No functional change. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Ching Liang See Cc: Ley

[U-Boot] [PATCH 1/4] arm: socfpga: Removing unused passing parameter of socfpga_bridges_reset

From: Tien Fong Chee This patch removes the unused passing parameter of socfpga_bridges_reset function in Arria10. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Ching Liang See

[U-Boot] [PATCH 0/4] Add Intel Arria 10 SoC FPGA driver

From: Tien Fong Chee This patchset adds FPGA driver to Intel Arria 10 SoC. This series is working on top of [1] initial patchset which enables the basic support for Arria 10 and other features. [1]: https://www.mail-archive.com/u-boot@lists.denx.de/msg240053.html

Re: [U-Boot] [PATCH 14/20] arm: socfpga: add SPL support for Arria 10

On Sab, 2017-02-25 at 22:43 +0100, Marek Vasut wrote: > On 02/22/2017 10:47 AM, Ley Foon Tan wrote: > > > > Add SPL support for Arria 10. > > > > Signed-off-by: Tien Fong Chee > > Signed-off-by: Ley Foon Tan > > --- > >  

Re: [U-Boot] [PATCH v4 00/28] *** SUBJECT HERE ***

On Sel, 2017-01-10 at 23:06 +0100, Marek Vasut wrote: > On 01/10/2017 06:20 AM, Chee Tien Fong wrote: > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > *** BLURB HERE *** > Please at least fill the blanks next time ... :) > By the way,

Re: [U-Boot] [PATCH v4 00/28] *** SUBJECT HERE ***

On Sel, 2017-01-10 at 23:06 +0100, Marek Vasut wrote: > On 01/10/2017 06:20 AM, Chee Tien Fong wrote: > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > *** BLURB HERE *** > Please at least fill the blanks next time ... :) > Oppss

[U-Boot] [PATCH v4 25/28] arm: socfpga: arria10: Added drivers for Arria10 clock manager

From: Tien Fong Chee The drivers is restructured such common functions, gen5 functions, and arria10 functions are moved to clock_manager.c, clock_manager_gen5 and clock_manager_arria10 respectively. Signed-off-by: Tien Fong Chee Cc: Marek

[U-Boot] [PATCH v4 25/28] arm: socfpga: arria10: Added drivers for Arria10 clock manager

From: Tien Fong Chee The drivers is restructured such common functions, gen5 functions, and arria10 functions are moved to clock_manager.c, clock_manager_gen5 and clock_manager_arria10 respectively. Signed-off-by: Tien Fong Chee Cc: Marek

[U-Boot] [PATCH v4 27/28] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl

From: Tien Fong Chee This patch adding the Arria10 critical hardware initialization before enabling console print out in spl. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang

[U-Boot] [PATCH v4 28/28] arm: socfpga: arria10: Enable fpga driver build for SPL.

From: Tien Fong Chee Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- drivers/Makefile | 2 +- 1 file

[U-Boot] [PATCH v4 26/28] arm: socfpga: arria10: Added drivers for Arria10 pinmux/pins configuration

From: Tien Fong Chee Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong ---

[U-Boot] [PATCH v4 22/28] arm: socfpga: arria10: Added support for Arria 10 socdk

From: Tien Fong Chee Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong ---

[U-Boot] [PATCH v4 25/28] arm: socfpga: arria10: Added drivers for Arria10 clock manager

From: Tien Fong Chee The drivers is restructured such common functions, gen5 functions, and arria10 functions are moved to clock_manager.c, clock_manager_gen5 and clock_manager_arria10 respectively. Signed-off-by: Tien Fong Chee Cc: Marek

[U-Boot] [PATCH v4 24/28] arm: socfpga: arria10: Added miscellaneous drivers for Arria 10

From: Tien Fong Chee The drivers is restructured such common functions, gen5 functions. and arria10 functions are moved to misc.c, misc_gen5 and misc_arria10 respectively. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh

[U-Boot] [PATCH v4 23/28] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

From: Tien Fong Chee Drivers for reset manager is restructured such that common functions, gen5 drivers and Arria10 drivers are moved to reset_manager.c, reset_manager_gen5.c and reset_manager_arria10.c respectively. Signed-off-by: Tien Fong Chee

[U-Boot] [PATCH v4 19/28] arm: socfpga: arria10: Enable SPL for Arria 10

From: Tien Fong Chee This patch enables SPL build and implementation for Arria 10. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong

[U-Boot] [PATCH v4 18/28] ARM:dts: Added device tree for socfpga arria10 development kit sdmmc

From: Tien Fong Chee This is initial version of device tree for the Intel socfpga arria10 development kit with sdmmc. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See

[U-Boot] [PATCH v4 21/28] arm: socfpga: arria10: Added some hardware base address for Arria 10

From: Tien Fong Chee Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong ---

[U-Boot] [PATCH v4 20/28] arm: socfpga: arria10: Added clock manager and pin mux compat macro

From: Tien Fong Chee These compat macros would be used by clock manager and pin mux drivers to look the required HW info from DTS for hardware initialization. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen

[U-Boot] [PATCH v4 17/28] arm: socfpga: arria10: update dwmac reset function to support Arria10

From: Tien Fong Chee On the Arria10, the EMAC phy mode configuration for each EMACs is located in separate registers versus being in 1 register for the GEN5 devices. The Arria10 also has 3 EMACs compared to 2 for the GEN5 devices. Update the dwmac_deassert_reset

[U-Boot] [PATCH v4 16/28] arm: socfpga: add reset manager defines for Arria10

From: Tien Fong Chee Add the Arria10 reset manager defines that is used in Linux. Change the license to SPDX. [commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel] Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong

[U-Boot] [PATCH v4 14/28] arm: socfpga: arria10: remove board_init and s_init

From: Tien Fong Chee These functions are already in arch/arm/mach-socfpga/board.c Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen

[U-Boot] [PATCH v4 15/28] arm: socfpga: combine clrbits/setbits into a single clrsetbits

From: Tien Fong Chee There is no dependency on doing a separate clrbits first in the dwmac_deassert_reset function. Combine them into a single clrsetbits call. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee

[U-Boot] [PATCH v4 13/28] arm: socfpga: arria10 fpga does not have bridges mapped

From: Tien Fong Chee On the Arria10 device, the bridges are not mapped through the interconnect. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen

[U-Boot] [PATCH v4 12/28] arm: socfpga: arria10: don't build GEN5 sdram for arria10

From: Tien Fong Chee The Arria10 device will not be able to re-use the GEN5 SDRAM controller, so we shouldn't build the driver. Move CONFIG_ALTERA_SDRAM to Kconfig option in drivers/ddr/altera/Kconfig. Signed-off-by: Dinh Nguyen

[U-Boot] [PATCH v4 09/28] arm: socfpga: add define for bootinfo bsel bit shift

From: Tien Fong Chee On arria5/cyclone5 parts, the bsel bits are at shift 0, while for arria10, the bsel bits are at shift 12. Add SYSMGR_BOOTINFO_BSEL_SHIFT define so that the reading the bsel can generic. Suggested-by: Marek Vasut Signed-off-by: Dinh

[U-Boot] [PATCH v4 11/28] arm: socfpga: wrap system manager functions for A5/C5 devices

From: Tien Fong Chee The system manager on Arria10 is not used for pin muxing duties, so wrap these functions for GEN5 devices only. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut

[U-Boot] [PATCH v4 08/28] arm: socfpga: arria10: add config option build for arria10

From: Tien Fong Chee Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong

[U-Boot] [PATCH v4 10/28] arm: socfpga: arria10: add reset manager for Arria10

From: Tien Fong Chee Add the defines for the reset manager and some basic reset functionality. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen

[U-Boot] [PATCH v4 06/28] arm: socfpga: arria10: add socfpga_arria10_socdk config

From: Tien Fong Chee Add config for the Arria10 SoC Development Kit. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Acked-by: Marek Vasut Cc: Marek Vasut Cc: Dinh

[U-Boot] [PATCH v4 07/28] arm: socfpga: arria10: add socfpga_arria10_defconfig

From: Tien Fong Chee Add a defconfig file for Arria10, which does not include enabling SPL. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Acked-by: Marek Vasut Cc: Marek Vasut

[U-Boot] [PATCH v4 04/28] arm: socfpga: arria10: add system manager defines

From: Tien Fong Chee Add system manager defines for Arria10. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See

[U-Boot] [PATCH v4 03/28] arm: socfpga: arria10: add board files for the Arria10 SoCDK

From: Tien Fong Chee Add minimal support for the Arria10 SoCDK. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See

[U-Boot] [PATCH v4 02/28] arm: socfpga: arria10: add sdram defines for Arria10

From: Tien Fong Chee Add the structures for the SDRAM controller on Arria10. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc:

[U-Boot] [PATCH v4 05/28] arm: socfpga: arria10: add misc functions for Arria10

From: Tien Fong Chee Add arch_early_init_r function. The Arria10 has a firewall protection around the SDRAM and OCRAM. These firewalls are to be disabled in order for U-Boot to function. Signed-off-by: Dinh Nguyen Signed-off-by: Tien

[U-Boot] [PATCH v4 01/28] arm: socfpga: arria10: add additional i2c nodes for Arria10

From: Tien Fong Chee Add remaining 3 I2C base addresses for the Arria10. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Reviewed-by: Stefan Roese Cc: Marek Vasut Cc:

[U-Boot] [PATCH v4 00/28] *** SUBJECT HERE ***

From: Tien Fong Chee *** BLURB HERE *** Tien Fong Chee (28): arm: socfpga: arria10: add additional i2c nodes for Arria10 arm: socfpga: arria10: add sdram defines for Arria10 arm: socfpga: arria10: add board files for the Arria10 SoCDK arm: socfpga: arria10: add

Re: [U-Boot] [v4 18/29] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address

On Isn, 2017-01-09 at 08:47 -0600, Dinh Nguyen wrote: > > On 01/09/2017 05:31 AM, Chee Tien Fong wrote: > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > Add base address header file for Stratix10 SoC > > > > Signed-off-by:

Re: [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10

On Isn, 2017-01-09 at 13:43 +0100, Marek Vasut wrote: > On 01/09/2017 12:25 PM, Chee Tien Fong wrote: > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > Add remaining 3 I2C base addresses for the Arria10. > > > > Signed-off-by

Re: [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10

On Isn, 2017-01-09 at 10:54 -0600, Dinh Nguyen wrote: > On Mon, Jan 9, 2017 at 6:43 AM, Marek Vasut <ma...@denx.de> wrote: > > > > On 01/09/2017 12:25 PM, Chee Tien Fong wrote: > > > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> &g

[U-Boot] [v4 29/29] arm: socfpga: arria10: Enable fpga driver build for SPL.

From: Tien Fong Chee Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- drivers/Makefile |2 +- 1

[U-Boot] [v4 28/29] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl

From: Tien Fong Chee This patch adding the Arria10 critical hardware initialization before enabling console print out in spl. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang

[U-Boot] [v4 27/29] arm: socfpga: arria10: Added drivers for Arria10 pinmux/pins configuration

From: Tien Fong Chee Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong ---

[U-Boot] [v4 26/29] arm: socfpga: arria10: Added drivers for Arria10 clock manager

From: Tien Fong Chee The drivers is restructured such common functions, gen5 functions, and arria10 functions are moved to clock_manager.c, clock_manager_gen5 and clock_manager_arria10 respectively. Signed-off-by: Tien Fong Chee Cc: Marek

[U-Boot] [v4 25/29] arm: socfpga: arria10: Added miscellaneous drivers for Arria 10

From: Tien Fong Chee The drivers is restructured such common functions, gen5 functions. and arria10 functions are moved to misc.c, misc_gen5 and misc_arria10 respectively. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh

[U-Boot] [v4 24/29] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

From: Tien Fong Chee Drivers for reset manager is restructured such that common functions, gen5 drivers and Arria10 drivers are moved to reset_manager.c, reset_manager_gen5.c and reset_manager_arria10.c respectively. Signed-off-by: Tien Fong Chee

[U-Boot] [v4 23/29] arm: socfpga: arria10: Added support for Arria 10 socdk

From: Tien Fong Chee Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong ---

[U-Boot] [v4 22/29] arm: socfpga: arria10: Added some hardware base address for Arria 10

From: Tien Fong Chee Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong ---

[U-Boot] [v4 20/29] arm: socfpga: arria10: Enable SPL for Arria 10

From: Tien Fong Chee This patch enables SPL build and implementation for Arria 10. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong

[U-Boot] [v4 21/29] arm: socfpga: arria10: Added clock manager and pin mux compat macro

From: Tien Fong Chee These compat macros would be used by clock manager and pin mux drivers to look the required HW info from DTS for hardware initialization. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen

[U-Boot] [v4 19/29] ARM:dts: Added device tree for socfpga arria10 development kit sdmmc

From: Tien Fong Chee This is initial version of device tree for the Intel socfpga arria10 development kit with sdmmc. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See

[U-Boot] [v4 18/29] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address

From: Tien Fong Chee Add base address header file for Stratix10 SoC Signed-off-by: Chin Liang See Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Ley Foon

[U-Boot] [v4 17/29] arm: socfpga: arria10: update dwmac reset function to support Arria10

From: Tien Fong Chee On the Arria10, the EMAC phy mode configuration for each EMACs is located in separate registers versus being in 1 register for the GEN5 devices. The Arria10 also has 3 EMACs compared to 2 for the GEN5 devices. Update the dwmac_deassert_reset

[U-Boot] [v4 13/29] arm: socfpga: arria10 fpga does not have bridges mapped

From: Tien Fong Chee On the Arria10 device, the bridges are not mapped through the interconnect. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen

[U-Boot] [v4 16/29] arm: socfpga: add reset manager defines for Arria10

From: Tien Fong Chee Add the Arria10 reset manager defines that is used in Linux. Change the license to SPDX. [commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel] Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong

[U-Boot] [v4 14/29] arm: socfpga: arria10: remove board_init and s_init

From: Tien Fong Chee These functions are already in arch/arm/mach-socfpga/board.c Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen

[U-Boot] [v4 12/29] arm: socfpga: arria10: don't build GEN5 sdram for arria10

From: Tien Fong Chee The Arria10 device will not be able to re-use the GEN5 SDRAM controller, so we shouldn't build the driver. Move CONFIG_ALTERA_SDRAM to Kconfig option in drivers/ddr/altera/Kconfig. Signed-off-by: Dinh Nguyen

[U-Boot] [v4 15/29] arm: socfpga: combine clrbits/setbits into a single clrsetbits

From: Tien Fong Chee There is no dependency on doing a separate clrbits first in the dwmac_deassert_reset function. Combine them into a single clrsetbits call. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee

[U-Boot] [v4 10/29] arm: socfpga: arria10: add reset manager for Arria10

From: Tien Fong Chee Add the defines for the reset manager and some basic reset functionality. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen

[U-Boot] [v4 11/29] arm: socfpga: wrap system manager functions for A5/C5 devices

From: Tien Fong Chee The system manager on Arria10 is not used for pin muxing duties, so wrap these functions for GEN5 devices only. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut

[U-Boot] [v4 08/29] arm: socfpga: arria10: add config option build for arria10

From: Tien Fong Chee Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong

[U-Boot] [v4 09/29] arm: socfpga: add define for bootinfo bsel bit shift

From: Tien Fong Chee On arria5/cyclone5 parts, the bsel bits are at shift 0, while for arria10, the bsel bits are at shift 12. Add SYSMGR_BOOTINFO_BSEL_SHIFT define so that the reading the bsel can generic. Suggested-by: Marek Vasut Signed-off-by: Dinh

[U-Boot] [v4 07/29] arm: socfpga: arria10: add socfpga_arria10_defconfig

From: Tien Fong Chee Add a defconfig file for Arria10, which does not include enabling SPL. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Acked-by: Marek Vasut Cc: Marek Vasut

[U-Boot] [v4 06/29] arm: socfpga: arria10: add socfpga_arria10_socdk config

From: Tien Fong Chee Add config for the Arria10 SoC Development Kit. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Acked-by: Marek Vasut Cc: Marek Vasut Cc: Dinh

[U-Boot] [v4 05/29] arm: socfpga: arria10: add misc functions for Arria10

From: Tien Fong Chee Add arch_early_init_r function. The Arria10 has a firewall protection around the SDRAM and OCRAM. These firewalls are to be disabled in order for U-Boot to function. Signed-off-by: Dinh Nguyen Signed-off-by: Tien

[U-Boot] [v4 03/29] arm: socfpga: arria10: add board files for the Arria10 SoCDK

From: Tien Fong Chee Add minimal support for the Arria10 SoCDK. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See

[U-Boot] [v4 04/29] arm: socfpga: arria10: add system manager defines

From: Tien Fong Chee Add system manager defines for Arria10. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See

[U-Boot] [v4 02/29] arm: socfpga: arria10: add sdram defines for Arria10

From: Tien Fong Chee Add the structures for the SDRAM controller on Arria10. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc:

[U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10

From: Tien Fong Chee Add remaining 3 I2C base addresses for the Arria10. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Reviewed-by: Stefan Roese Cc: Marek Vasut Cc:

Re: [U-Boot] [v3 25/30] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

On Jum, 2017-01-06 at 17:03 -0600, Dinh Nguyen wrote: > > On 01/06/2017 05:19 AM, Chee Tien Fong wrote: > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > Drivers for reset manager is restructured such that common > > functions, >

Re: [U-Boot] [v3 21/30] arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL

On Jum, 2017-01-06 at 12:12 -0600, Dinh Nguyen wrote: > > On 01/06/2017 05:19 AM, Chee Tien Fong wrote: > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > Enhanced defconfig file for Arria10 to enable SPL build and > > supporting > >

[U-Boot] [v3 30/30] arm: socfpga: arria10: Enable fpga driver build for SPL.

From: Tien Fong Chee Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- Changes for V3 - no changes Changes

[U-Boot] [v3 27/30] arm: socfpga: arria10: Added drivers for Arria10 clock manager

From: Tien Fong Chee The drivers is restructured such common functions, gen5 functions, and arria10 functions are moved to clock_manager.c, clock_manager_gen5 and clock_manager_arria10 respectively. Signed-off-by: Tien Fong Chee Cc: Marek

[U-Boot] [v3 29/30] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl

From: Tien Fong Chee This patch adding the Arria10 critical hardware initialization before enabling console print out in spl. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang

[U-Boot] [v3 28/30] arm: socfpga: arria10: Added drivers for Arria10 pinmux/pins configuration

From: Tien Fong Chee Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- Changes for V3 - no changes Changes

[U-Boot] [v3 24/30] arm: socfpga: arria10: Added support for Arria 10 socdk

From: Tien Fong Chee Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- Changes for V3 - no changes Changes

[U-Boot] [v3 26/30] arm: socfpga: arria10: Added miscellaneous drivers for Arria 10

From: Tien Fong Chee The drivers is restructured such common functions, gen5 functions. and arria10 functions are moved to misc.c, misc_gen5 and misc_arria10 respectively. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh

[U-Boot] [v3 23/30] arm: socfpga: arria10: Added some hardware base address for Arria 10

From: Tien Fong Chee Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- Changes for v3 - no changes changes

[U-Boot] [v3 25/30] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

From: Tien Fong Chee Drivers for reset manager is restructured such that common functions, gen5 drivers and Arria10 drivers are moved to reset_manager.c, reset_manager_gen5.c and reset_manager_arria10.c respectively. Signed-off-by: Tien Fong Chee

[U-Boot] [v3 21/30] arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL

From: Tien Fong Chee Enhanced defconfig file for Arria10 to enable SPL build and supporting device tree build for SDMMC. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See

[U-Boot] [v3 20/30] arm: socfpga: arria10: Enable SPL for Arria 10

From: Tien Fong Chee This patch enables SPL build and implementation for Arria 10. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong

[U-Boot] [v3 19/30] ARM:dts: Added device tree for socfpga arria10 development kit sdmmc

From: Tien Fong Chee This is initial version of device tree for the Intel socfpga arria10 development kit with sdmmc. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See

[U-Boot] [v3 22/30] arm: socfpga: arria10: Added clock manager and pin mux compat macro

From: Tien Fong Chee These compat macros would be used by clock manager and pin mux drivers to look the required HW info from DTS for hardware initialization. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen

[U-Boot] [v3 18/30] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address

From: Tien Fong Chee Add base address header file for Stratix10 SoC Signed-off-by: Chin Liang See Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Ley Foon

[U-Boot] [v3 17/30] arm: socfpga: arria10: update dwmac reset function to support Arria10

From: Tien Fong Chee On the Arria10, the EMAC phy mode configuration for each EMACs is located in separate registers versus being in 1 register for the GEN5 devices. The Arria10 also has 3 EMACs compared to 2 for the GEN5 devices. Update the dwmac_deassert_reset

[U-Boot] [v3 16/30] arm: socfpga: add reset manager defines for Arria10

From: Tien Fong Chee Add the Arria10 reset manager defines that is used in Linux. Change the license to SPDX. [commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel] Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong

[U-Boot] [v3 15/30] arm: socfpga: combine clrbits/setbits into a single clrsetbits

From: Tien Fong Chee There is no dependency on doing a separate clrbits first in the dwmac_deassert_reset function. Combine them into a single clrsetbits call. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee

[U-Boot] [v3 14/30] arm: socfpga: arria10: remove board_init and s_init

From: Tien Fong Chee These functions are already in arch/arm/mach-socfpga/board.c Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen

[U-Boot] [v3 13/30] arm: socfpga: arria10 fpga does not have bridges mapped

From: Tien Fong Chee On the Arria10 device, the bridges are not mapped through the interconnect. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen

[U-Boot] [v3 11/30] arm: socfpga: wrap system manager functions for A5/C5 devices

From: Tien Fong Chee The system manager on Arria10 is not used for pin muxing duties, so wrap these functions for GEN5 devices only. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut

[U-Boot] [v3 10/30] arm: socfpga: arria10: add reset manager for Arria10

From: Tien Fong Chee Add the defines for the reset manager and some basic reset functionality. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen

[U-Boot] [v3 12/30] arm: socfpga: arria10: don't build GEN5 sdram for arria10

From: Tien Fong Chee The Arria10 device will not be able to re-use the GEN5 SDRAM controller, so we shouldn't build the driver. Move CONFIG_ALTERA_SDRAM to Kconfig option in drivers/ddr/altera/Kconfig. Signed-off-by: Dinh Nguyen

<    1   2   3   4   5   6   7   >