clean up the wrong io_sel for PCI express according to latest manual.
Signed-off-by: Dave Liu dave...@freescale.com
---
arch/ppc/cpu/mpc8xxx/pci_cfg.c| 13 ++---
arch/ppc/include/asm/immap_85xx.h |5 +
2 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/arch/ppc
For P1022 SATA host controller, the data snoop bit of DW3 in PRDT
is moved to bit28.
Signed-off-by: Dave Liu dave...@freescale.com
---
* address Wolfgang's comments
drivers/block/fsl_sata.h |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/block/fsl_sata.h
After power on, the SATA host controller of P1022 Rev1 is configured
in legacy mode instead of the expected enterprise mode.
Software needs to clear bit[28] of HControl register to change to
enterprise mode after bringing the host offline.
Signed-off-by: Dave Liu dave...@freescale.com
up the order issue of DIU driver.
Signed-off-by: Dave Liu dave...@freescale.com
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
---
* address Timur's comments
board/freescale/common/fsl_diu_fb.c | 55 ++-
1 files changed, 28 insertions(+), 27 deletions
After power on, the SATA host controller of P1022 Rev1 is configured
in legacy mode instead of the expected enterprise mode.
software needs to clear bit[28] of HControl register to change to
enterprise mode after bringing the host offline.
Signed-off-by: Dave Liu dave...@freescale.com
For P1022 SATA host controller, the data snoop bit of DW3 in PRDT
is moved to bit28.
Signed-off-by: Dave Liu dave...@freescale.com
---
drivers/block/fsl_sata.h |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/drivers/block/fsl_sata.h b/drivers/block/fsl_sata.h
index
After power on, the SATA host controller of P1022 Rev1 is configured
in legacy mode instead of the expected enterprise mode.
Software needs to clear bit[28] of HControl register to change to
enterprise mode after bringing the host offline.
Signed-off-by: Dave Liu dave...@freescale.com
For P1022 SATA host controller, the data snoop bit of DW3 in PRDT
is moved to bit28.
Signed-off-by: Dave Liu dave...@freescale.com
---
* address Kumar's comments
drivers/block/fsl_sata.h |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/drivers/block/fsl_sata.h b
After power on, the SATA host controller of P1022 Rev1 is configured
in legacy mode instead of the expected enterprise mode.
Software needs to clear bit[28] of HControl register to change to
enterprise mode after bringing the host offline.
Signed-off-by: Dave Liu dave...@freescale.com
up the order issue of DIU driver.
Signed-off-by: Dave Liu dave...@freescale.com
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
---
board/freescale/common/fsl_diu_fb.c | 55 ++-
1 files changed, 28 insertions(+), 27 deletions(-)
diff --git a/board
Read-to-read/Write-to-write turnaround for same chip select
of DDR3 memory, BL/2+2 cycles is enough for them at BC4 and
OTF case, BL/2 cycles is enough for fixed BL8.
Cutting down the turnaround from BL/2+4 to BL/2+2 or BL/2
will improve the memory performance.
Signed-off-by: Dave Liu dave
For 64B cacheline SoC, set the fixed 8-beat burst len,
for 32B cacheline SoC, set the On-The-Fly as default.
Signed-off-by: Dave Liu dave...@freescale.com
---
should go to B2.0.3 release.
cpu/mpc8xxx/ddr/options.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/cpu
Read-to-read/Write-to-write turnaround for same chip select
of DDR3 memory, BL/2+2 cycles is enough for these turnarounds.
Cutting down the turnaround from BL/2+4 to BL/2+2 will improve
the memory performance.
Signed-off-by: Dave Liu dave...@freescale.com
---
cpu/mpc8xxx/ddr/ctrl_regs.c |6
add the override for write leveling sampling and
start time according to specific board.
Signed-off-by: Dave Liu dave...@freescale.com
---
cpu/mpc8xxx/ddr/ctrl_regs.c | 20 ++--
cpu/mpc8xxx/ddr/options.c |1 +
include/asm-ppc/fsl_ddr_sdram.h |5 +
3 files
It may be different settings of Rtt_nom and Rtt_WR
for different boards, adding the override provide the
capability.
Signed-off-by: Dave Liu dave...@freescale.com
---
cpu/mpc8xxx/ddr/ctrl_regs.c | 10 +++---
include/asm-ppc/fsl_ddr_sdram.h |1 +
2 files changed, 8 insertions(+), 3
The real clock divider is 4 times of the bits LCRR[CLKDIV],
according the latest RevF RM.
Signed-off-by: Dave Liu dave...@freescale.com
---
cpu/mpc85xx/speed.c |7 ++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index 7959082
[RODT_ON] should be set to WL-2
4. TIMING_CFG_5[RODT_OFF] should be set to WL-1
5. TIMING_CFG_5[WODT_ON] should be set to WL-2
6. TIMING_CFG_5[WODT_OFF] should be set to WL-1
ps: WL=TIMING_CFG_2[WR_LAT]
The original work was finished by Mazyar Razzaz and Travis Wheatley.
Signed-off-by: Dave Liu
commit 1542fbdeec0d1e2a6df13189df8dcb1ce8802be3
introduced one new bug to chip-select interleaving.
Single DDR controller also can do the chip-select
interleaving if there is dual-rank or qual-rank DIMMs.
Signed-off-by: Dave Liu dave...@freescale.com
---
The v1 also address the cs_per_ctrl == 1
commit 1542fbdeec0d1e2a6df13189df8dcb1ce8802be3
introduced one new bug to chip-select interleaving.
Single DDR controller also can do the chip-select
interleaving if there is dual-rank or qual-rank DIMMs.
Signed-off-by: Dave Liu dave...@freescale.com
---
cpu/mpc8xxx/ddr/options.c |4 +---
1
* The ELPIDA 2GB unbuffered DDR3 SDRAM DIMMs - EBJ21EE8BAFA-AE-E
600MT/s, 667MT/s and 800MT/s passed on P2020DS
* Micron 1GB unbuffered DDR3 SDRAM DIMMs - MT9JSF12872AY-1G4D1
600MT/s, 667MT/s and 800MT/s passed on P2020DS
Signed-off-by: Dave Liu dave...@freescale.com
Signed-off-by: Travis
The SYS_CLK_IN of MPC8569MDS is 66.66MHz,
The DDR_CLK_IN is same with SYS_CLK_IN in 8569 processor.
so, change the SYS_CLK_IN from 66MHz to 66.66MHz.
Signed-off-by: Dave Liu dave...@freescale.com
---
include/configs/MPC8569MDS.h |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff
The BCSR17[7] = 1 will unlock the write protect of FLASH.
The WP# pin only controls the write protect of top/bottom sector,
That is why we can save env, but we can't write the first sector
before the patch.
Signed-off-by: Dave Liu dave...@freescale.com
---
board/freescale/mpc8569mds/bcsr.c
Currently the clk_adj is 6 (3/4 cycle), The settings will cause
the DDR controller hang at the data init. Change the clk_adj
from 6 to 4 (1/2 cycle), make the memory system stable.
Signed-off-by: Dave Liu dave...@freescale.com
---
board/freescale/mpc8569mds/ddr.c |2 +-
1 files changed, 1
Give the MPC8569MDS board one default environment var.
Signed-off-by: Dave Liu dave...@freescale.com
---
include/configs/MPC8569MDS.h | 72 --
1 files changed, 41 insertions(+), 31 deletions(-)
diff --git a/include/configs/MPC8569MDS.h b/include/configs
Currently the clk_adj is 6 (3/4 cycle), The settings will cause
the DDR controller hang at the data init. Change the clk_adj
from 6 to 4 (1/2 cycle), make the memory system stable.
Signed-off-by: Dave Liu dave...@freescale.com
---
board/freescale/mpc8569mds/ddr.c |2 +-
1 files changed, 1
1. wr_lat
UM said the total write latency for DDR2 is equal to
WR_LAT + ADD_LAT, the write latency is CL + ADD_LAT - 1.
so, the WR_LAT = CL - 1;
2. rd_to_pre
we missed to add the ADD_LAT for DDR2 case.
Reported-by: Joakim Tjernlund joakim.tjernl...@transmode.se
Signed-off-by: Dave Liu
- support mirrored DIMMs, not support register DIMMs
- test passed on P2020DS board with MT9JSF12872AY-1G1D1
- test passed on MPC8569MDS board with MT8JSF12864HY-1G1D1
Signed-off-by: Dave Liu dave...@freescale.com
Signed-off-by: Travis Wheatley travis.wheat...@freescale.com
---
common/ddr_spd.c
...@transmode.se
Signed-off-by: Dave Liu dave...@freescale.com
---
cpu/mpc83xx/spd_sdram.c | 23 ---
1 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 42a4e67..ecbc70c 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b
DIMMs test passed on
MPC837xEMDS platform at 266MHz/333MHz/400MHz data rate.
Reported-by: Joakim Tjernlund joakim.tjernl...@transmode.se
Signed-off-by: Dave Liu dave...@freescale.com
---
cpu/mpc83xx/spd_sdram.c | 26 +++---
1 files changed, 23 insertions(+), 3 deletions
.
Reported-by: Joakim Tjernlund joakim.tjernl...@transmode.se
Signed-off-by: Dave Liu dave...@freescale.com
---
cpu/mpc8xxx/ddr/ctrl_regs.c | 11 ++-
1 files changed, 10 insertions(+), 1 deletions(-)
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index 292980d
---
The patch is to be done, It is only giving the context
why move the definition of fsl_law from .c to .h.
Makefile | 13 +-
board/freescale/mpc8572ds/config.mk |5 +
board/freescale/mpc8572ds/nand_boot.c | 75
- It is possible to miss flush/invalidate the last
cache line, we fix it at here.
- add the volatile and memory clobber.
the bugs is pointed by Scott Wood.
Signed-off-by: Dave Liu [EMAIL PROTECTED]
---
lib_ppc/cache.c | 36 +---
1 files changed, 17 insertions
is using the d-cache lock, so all of d-cache
access is cache-inhibited. so you can't see the issue.
- 85xx family is using d-cache, i-cache enable, partial
cache lock. you will see the issue.
The patch fix the cache issue.
Signed-off-by: Dave Liu [EMAIL PROTECTED]
---
Stefan,
I'm not familiar
family is using the dcache lock, so all of dcache
access is cache-inhibited. so you can't see the issue.
- 85xx family is using dcache, icache enable, partial
cache lock. you will see the issue.
The patch fix the cache issue.
Signed-off-by: Dave Liu [EMAIL PROTECTED]
---
nand_spl
The default DDR freq is 400MHz or 800M data rate,
the old settings is pure wrong for the default case.
Signed-off-by: Dave Liu [EMAIL PROTECTED]
---
include/configs/MPC8572DS.h | 26 +-
1 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/include/configs
According to the latest 8572 UM, the DDR3 controller
is expanding the bit mask, and we use the extend ACTTOPRE
mode when tRAS more than 19 MCLK.
Signed-off-by: Dave Liu [EMAIL PROTECTED]
---
cpu/mpc8xxx/ddr/ctrl_regs.c | 12
1 files changed, 8 insertions(+), 4 deletions(-)
diff
to the DDR controller, it will
reset the counter and exit self refresh state.
Signed-off-by: Dave Liu [EMAIL PROTECTED]
---
cpu/mpc8xxx/ddr/ctrl_regs.c | 12
include/asm-ppc/fsl_ddr_sdram.h |4
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/cpu/mpc8xxx
For light loaded system, we use the 1T timing to gain better
memory performance, but for some heavily loaded system,
you have to add the 2T timing options to board files.
Signed-off-by: Dave Liu [EMAIL PROTECTED]
---
board/freescale/mpc8540ads/ddr.c |3 +++
board/freescale/mpc8544ds/ddr.c
The wake up ARP feature need use the memory to process
wake up packet, we enable auto self refresh to support it.
Signed-off-by: Dave Liu [EMAIL PROTECTED]
---
board/freescale/mpc8536ds/ddr.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/board/freescale/mpc8536ds
According to the latest 8572 UM, the DDR3 controller
is expanding the bit mask, and we use the extend ACTTOPRE
mode when tRAS more than 19 MCLK.
Signed-off-by: Dave Liu [EMAIL PROTECTED]
---
cpu/mpc8xxx/ddr/ctrl_regs.c | 12
1 files changed, 8 insertions(+), 4 deletions(-)
diff
these values without a problem,
thereby decreasing the latency of memory a little.
Signed-off-by: Howard Gregory [EMAIL PROTECTED]
Signed-off-by: Dave Liu [EMAIL PROTECTED]
---
include/configs/MPC8315ERDB.h | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/include
Signed-off-by: Dave Liu [EMAIL PROTECTED]
---
include/configs/MPC8315ERDB.h | 12 +++-
1 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 1225270..64bb62a 100644
--- a/include/configs/MPC8315ERDB.h
+++ b
We must invalidate TLBs before MMU turn on, but
currently the code is not, if there are some stale
TLB entry valid in the TLBs, it will cause strange
issue.
Signed-off-by: Dave Liu [EMAIL PROTECTED]
---
cpu/mpc86xx/start.S |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff
The DDR controller of 86xx processors have the ECC data init
feature, and the new DDR code is using the feature, we don't
need the way with DMA to init memory again.
Signed-off-by: Dave Liu [EMAIL PROTECTED]
---
board/freescale/mpc8610hpcd/mpc8610hpcd.c | 11 ---
board/freescale
The DDR1 LAW will precedence the DDR2 LAW, so remove
the second DDR LAW.
Signed-off-by: Dave Liu [EMAIL PROTECTED]
---
board/freescale/mpc8641hpcn/law.c |3 ---
1 files changed, 0 insertions(+), 3 deletions(-)
diff --git a/board/freescale/mpc8641hpcn/law.c
b/board/freescale/mpc8641hpcn
I believe these code was copied from 74xx family, but for
86xx, it is unused.
Signed-off-by: Dave Liu [EMAIL PROTECTED]
---
cpu/mpc86xx/start.S | 14 --
1 files changed, 0 insertions(+), 14 deletions(-)
diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index 30e6047..ab672d1
The commit 67256678f00c09b0a7f19e862e5c1847553d31bc add
the another global data pointer save, but in fact the
global data pointer will be initialized in the board_init_r,
so remove it such as the 85xx/83xx family.
Signed-off-by: Dave Liu [EMAIL PROTECTED]
---
cpu/mpc86xx/start.S |1 -
1
The DDR controller of 8548/8544/8568/8572/8536 processors
have the ECC data init feature, and the new DDR code is
using the feature, and we don't need the way with DMA to
init memory any more.
Signed-off-by: Dave Liu [EMAIL PROTECTED]
---
board/atum8548/atum8548.c | 10
We must invalidate TLBs before MMU turn on, but
currently the code is not, if there are some stale
TLB entry valid in the TLBs, it will cause strange
issue.
Signed-off-by: Dave Liu [EMAIL PROTECTED]
---
cpu/mpc86xx/start.S |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff
Signed-off-by: Dave Liu [EMAIL PROTECTED]
---
include/configs/MPC8536DS.h |8
include/configs/MPC8572DS.h | 10 --
2 files changed, 0 insertions(+), 18 deletions(-)
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 38be10d..dbddb63 100644
for DDR_1
and CCSRBAR offset + 0x6f00 for DDR_2).
Currenlty, the code is using incorrect register DDR_SDRAM_CFG_2
as condition, but it should be DDR_SDRAM_CFG register.
Signed-off-by: Dave Liu [EMAIL PROTECTED]
---
cpu/mpc85xx/ddr-gen3.c |9 ++---
1 files changed, 6 insertions(+), 3
Signed-off-by: Dave Liu [EMAIL PROTECTED]
---
include/configs/MPC8610HPCD.h |9 -
include/configs/MPC8641HPCN.h | 11 ---
2 files changed, 0 insertions(+), 20 deletions(-)
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 678e1e1..d92bed9
.
lock_ram_in_cache() is modified similarly as good coding practice, but
is not called from C.
Signed-off-by: Nick Spence [EMAIL PROTECTED]
also, the r2 is used as global data pointer.
Signed-off-by: Dave Liu [EMAIL PROTECTED]
---
cpu/74xx_7xx/start.S |8
1 files changed, 4 insertions(+), 4
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