u-boot binary size for Freescale mpc8536DS platforms is 512KB.
This has been reached to upper limit of the platforms and causig
linker error. So increase the u-boot binary size to 768KB.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
include/configs/MPC8536DS.h | 4 ++--
1 file
for read and write command.
3. Add CONFIG_SYS_FSL_ERRATUM_ESDHC111 to enable its workaround.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V2
- Rewrite the comments.
arch/powerpc/include/asm/config_mpc85xx.h | 5 +
drivers/mmc/fsl_esdhc.c | 5
CONFIG_SYS_FSL_ERRATUM_ESDHC111 to enable its workaround.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
arch/powerpc/include/asm/config_mpc85xx.h | 5 +
drivers/mmc/fsl_esdhc.c | 5 -
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm
There was wrong phy_mask for AR8021 device,
so the AR8021 can't be probed correctly.
Changed it from 0x4f to 0x40.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
drivers/net/phy/atheros.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy
u-boot binary size for Freescale mpc8536DS platforms is 512KB.
This has been reached to upper limit of the platforms and causig
linker error. So increase the u-boot binary size to 768KB.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
include/configs/MPC8536DS.h | 10 +++---
1
The upper 4 data signals of esdhc are shared with spi flash.
So detect if the upper 4 pins are assigned to esdhc before
enable sdhc 8 bit width.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V3:
- Define quirk in board specific file instead of code in driver
and initialize the card
regardless of whether the card is inserted or not in case Rev1.0.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V3:
- Define quirk in board specific file instead of code in driver
changes for V2:
- Add the judgement condition
to calculate the envaddr.
If there is no enough space for environment variables or envaddr
is larger than 4GiB, we relocate the envaddr to 0x400. The address
relocated is in the front of the first partition that is assigned
for sdboot only.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
Manufacturer ID: 0
OEM: 0
Name: Tran Speed: 0
Rd Block Len: 0
MMC version 0.0
High Capacity: No
Capacity: 0 Bytes
Bus Width: 1-bit
=
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V5:
- Exclude the judgement of EXT_CSD_REV in case of read EXT_CSD err
drivers/mmc/mmc.c
Rd Block Len: 0
MMC version 0.0
High Capacity: No
Capacity: 0 Bytes
Bus Width: 1-bit
= mmcinfo
Device: FSL_SDHC
Manufacturer ID: 0
OEM: 0
Name: Tran Speed: 0
Rd Block Len: 0
MMC version 0.0
High Capacity: No
Capacity: 0 Bytes
Bus Width: 1-bit
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
return, has failed.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V5:
- Changed the judgement way of block number returned from erase command
common/cmd_mmc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c
index
used for busy state release.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V5:
- no changes
drivers/mmc/fsl_esdhc.c | 164 +++-
1 file changed, 106 insertions(+), 58 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b
Add command class define.
Add mmc erase and secure erase define.
Add secure erase and trim support bit define.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V5:
- Add some comments for definitions
include/mmc.h | 50
From: Haijun Zhang haijun.zh...@freescale.com
Esdhc host version number is incorrect in host capacity register.
The value read from was 0x14. Correct it to 0x13.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V5:
- no changes
arch/powerpc/include/asm
0x.(Trim and discard are ignored here)
6. Check card status after erase operation is completed.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V5:
- re-write the code to let it seem simple
drivers/mmc/mmc_write.c | 62
Rd Block Len: 0
MMC version 0.0
High Capacity: No
Capacity: 0 Bytes
Bus Width: 1-bit
= mmcinfo
Device: FSL_SDHC
Manufacturer ID: 0
OEM: 0
Name: Tran Speed: 0
Rd Block Len: 0
MMC version 0.0
High Capacity: No
Capacity: 0 Bytes
Bus Width: 1-bit
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
From: Haijun Zhang haijun.zh...@freescale.com
Add command class define.
Add mmc erase and secure erase define.
Add secure erase and trim support bit define.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V4:
- no changes
changes for V3:
- No changes
Manufacturer ID: 0
OEM: 0
Name: Tran Speed: 0
Rd Block Len: 0
MMC version 0.0
High Capacity: No
Capacity: 0 Bytes
Bus Width: 1-bit
=
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V4:
- update the commit message
- mask the cmdclass to 12 bit only
drivers/mmc/mmc.c
0x.(Trim and discard are ignored here)
6. Check card status after erase operation is completed.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V4:
- Update the commit message
changes for V3:
- update the commit message and secure feature supporting
.
Error return, zero return, has failed.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V4:
- update commit message
changes for V3:
- no changes
common/cmd_mmc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c
index
From: Haijun Zhang haijun.zh...@freescale.com
Esdhc host version number is incorrect in host capacity register.
The value read from was 0x14. Correct it to 0x13.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V4:
- no changes
arch/powerpc/include/asm
used for busy state release.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V4:
- no changes
changes for V3:
- changed the '-1' to '0xU'
- redundant check command and data error after while loop.
drivers/mmc/fsl_esdhc.c | 164
and initialize the card
regardless of whether the card is inserted or not in case Rev1.0.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V2:
- Add the judgement condition for this broken card
drivers/mmc/fsl_esdhc.c| 9 +
include/configs/T4240QDS.h | 2
to calculate the envaddr.
If there is no enough space for environment variables or envaddr
is larger than 4GiB, we relocate the envaddr to 0x400. The address
relocated is in the front of the first partition that is assigned
for sdboot only.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
The upper 4 data signals of esdhc are shared with spi flash.
So detect if the upper 4 pins are assigned to esdhc before
enable sdhc 8 bit width.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changs for V2:
- No changes
drivers/mmc/fsl_esdhc.c| 5 +
include/configs
Manufacturer ID: 0
OEM: 0
Name: Tran Speed: 0
Rd Block Len: 0
MMC version 0.0
High Capacity: No
Capacity: 0 Bytes
Bus Width: 1-bit
=
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V3:
- Change the erase group size to be block aligned.
drivers/mmc/mmc.c | 52
, erase with arg 0x8000(Spec eMMC 4.41).
else erase with arg 0x.(Trim and discard is ingnored here)
6. Check card status after erase.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V3:
- update the commit message and secure feature supporting judgment
used for busy state release.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V3:
- changed the '-1' to '0xU'
- redundant check command and data error after while loop.
drivers/mmc/fsl_esdhc.c | 164 +++-
1
From: Haijun Zhang haijun.zh...@freescale.com
Add command class define.
Add mmc erase and secure erase define.
Add secure erase and trim support bit define.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V3:
- No changes
include/mmc.h | 50
: Tran Speed: 0
Rd Block Len: 0
MMC version 0.0
High Capacity: No
Capacity: 0 Bytes
Bus Width: 1-bit
= mmcinfo
Device: FSL_SDHC
Manufacturer ID: 0
OEM: 0
Name: Tran Speed: 0
Rd Block Len: 0
MMC version 0.0
High Capacity: No
Capacity: 0 Bytes
Bus Width: 1-bit
Signed-off-by: Haijun Zhang haijun.zh
of them.
Error number and zero number mean erase operation was failed.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V3:
- no changes
common/cmd_mmc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c
index 67a94a7
From: Haijun Zhang haijun.zh...@freescale.com
Esdhc host version number is incorrect in host capacity register.
The value read from was 0x14. Correct it to 0x13.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V3:
- no changes
arch/powerpc/include/asm
The upper 4 data signals of esdhc are shared with spi flash.
So detect if the upper 4 pins are assigned to esdhc
before enable sdhc 8 bit width.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
drivers/mmc/fsl_esdhc.c| 6 ++
include/configs/T4240QDS.h | 2 ++
2 files changed, 8
to calculate the envaddr.
If there is no enough space for environment variables or envaddr
is larger than 4GiB, we relocate the envaddr to 0x400. The address
relocated is in the front of the first partition that is assigned
for sdboot only.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
Card detection pin is ineffective on T4240QDS.
This workaround force sdhc driver scan and initialize the card regardless
of whether the card is inserted. if no card is in the slot, the error message
card is not inserted will be prompted.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
Add command class define.
Add mmc erase and secure erase define.
Add secure erase and trim support bit define.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V2:
- Changed the comment, no other change
include/mmc.h | 50
state release.
6. In case eSDHC host version 2.3, host will signal transfer complete
interrupt once busy state was release.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
drivers/mmc/fsl_esdhc.c | 165 +++-
1 file changed, 108 insertions
state release.
6. In case eSDHC host version 2.3, host will signal transfer complete
interrupt once busy state was release.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
Changes for V2:
- Initialize the irqstat = 0 to avoid compile warning
drivers/mmc/fsl_esdhc.c | 165
: Tran Speed: 0
Rd Block Len: 0
MMC version 0.0
High Capacity: No
Capacity: 0 Bytes
Bus Width: 1-bit
= mmcinfo
Device: FSL_SDHC
Manufacturer ID: 0
OEM: 0
Name: Tran Speed: 0
Rd Block Len: 0
MMC version 0.0
High Capacity: No
Capacity: 0 Bytes
Bus Width: 1-bit
Signed-off-by: Haijun Zhang haijun.zh
Manufacturer ID: 0
OEM: 0
Name: Tran Speed: 0
Rd Block Len: 0
MMC version 0.0
High Capacity: No
Capacity: 0 Bytes
Bus Width: 1-bit
=
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
Changes for V2:
- No changes
drivers/mmc/mmc.c | 51 ++-
1
of them.
Error number and zero number mean erase operation was failed.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
Changes for V2:
- Removed the compiling warning
common/cmd_mmc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c
Esdhc host version number is incorrect in host capacity register.
The value read from was 0x14. Correct it to 0x13.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
Change for V2:
- No changes
arch/powerpc/include/asm/config_mpc85xx.h | 1 +
1 file changed, 1 insertion
status after erase.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
Changes for V2:
- No changes
drivers/mmc/mmc_write.c | 70 ++---
1 file changed, 60 insertions(+), 10 deletions(-)
diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc
Manufacturer ID: 0
OEM: 0
Name: Tran Speed: 0
Rd Block Len: 0
MMC version 0.0
High Capacity: No
Capacity: 0 Bytes
Bus Width: 1-bit
=
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
drivers/mmc/mmc.c | 51 ++-
1 file changed, 38 insertions(+), 13
Add command class define.
Add mmc erase and secure erase define.
Add secure erase and trim support bit define.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
include/mmc.h | 49 +
1 file changed, 49 insertions(+)
diff --git a/include
: Tran Speed: 0
Rd Block Len: 0
MMC version 0.0
High Capacity: No
Capacity: 0 Bytes
Bus Width: 1-bit
= mmcinfo
Device: FSL_SDHC
Manufacturer ID: 0
OEM: 0
Name: Tran Speed: 0
Rd Block Len: 0
MMC version 0.0
High Capacity: No
Capacity: 0 Bytes
Bus Width: 1-bit
Signed-off-by: Haijun Zhang haijun.zh
status after erase.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
drivers/mmc/mmc_write.c | 70 ++---
1 file changed, 60 insertions(+), 10 deletions(-)
diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c
index aa2fdef..f2e9baf
Esdhc host version number is incorrect in host capacity register.
The value read from was 0x14. Correct it to 0x13.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
arch/powerpc/include/asm/config_mpc85xx.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/include/asm
of them.
Error number and zero number mean erase operation was failed.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
common/cmd_mmc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c
index 67a94a7..15cecb7 100644
--- a/common/cmd_mmc.c
state release.
6. In case eSDHC host version 2.3, host will signal transfer complete
interrupt once busy state was release.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
drivers/mmc/fsl_esdhc.c | 165 +++-
1 file changed, 108 insertions
: 0
Name: Tran Speed: 0
Rd Block Len: 0
MMC version 0.0
High Capacity: No
Capacity: 0 Bytes
Bus Width: 0-bit
=
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
Signed-off-by: Xie Shaohui-B21989 b21...@freescale.com
Tested-by: Ryan Barnett rjbar...@rockwellcollins.com
---
changes for V3
T4240QDS eSDHC host capabilities reigster should have VS33 bit define.
Add quirk CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 to deal with capacity
missing
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V3:
- Move the macro
T4240QDS eSDHC host capabilities reigster should have VS33 bit define.
Add quirk CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 to deal with capacity
missing
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V2:
- Limited
: 0
Name: Tran Speed: 0
Rd Block Len: 0
MMC version 0.0
High Capacity: No
Capacity: 0 Bytes
Bus Width: 0-bit
=
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
Signed-off-by: Xie Shaohui-B21989 b21...@freescale.com
---
drivers/mmc/fsl_esdhc.c | 1 +
1 file changed, 1 insertion(+)
diff --git
Add some descriptions for esdhc register for easily using.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
drivers/mmc/fsl_esdhc.c | 74 -
1 file changed, 37 insertions(+), 37 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers
eSDHC host controller has new register to support SD Spec 3.0.
And the according host controller version was Freescale eSDHC
Version 3.0.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes:
- Split from patch [PATCH] powerpc/esdhc: Map
register for eSDHC host
eSDHC host controller has new register to support SD Spec 3.0.
And the according host controller version was Freescale eSDHC
Version 3.0. Add some new register and it simple description.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
drivers/mmc/fsl_esdhc.c | 62
eSDHC host controller has new register to support SD Spec 3.0.
And the according host controller version was Freescale eSDHC
Version 3.0. Add some new register and it simple description.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
drivers/mmc/fsl_esdhc.c | 62
: 0
Name: Tran Speed: 0
Rd Block Len: 0
MMC version 0.0
High Capacity: No
Capacity: 0 Bytes
Bus Width: 0-bit
=
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
Signed-off-by: Xie Shaohui-B21989 b21...@freescale.com
---
drivers/mmc/fsl_esdhc.c | 1 +
1 file changed, 1 insertion(+)
diff --git
T4240 eSDHC host capabilities reigster should have VS33 bit define.
hack the code to add the 3.3 voltage support
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
arch/powerpc/include/asm/config_mpc85xx.h | 1 +
drivers/mmc/fsl_esdhc.c
: 0
Name: Tran Speed: 0
Rd Block Len: 0
MMC version 0.0
High Capacity: No
Capacity: 0 Bytes
Bus Width: 0-bit
=
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
Signed-off-by: Xie Shaohui-B21989 b21...@freescale.com
---
drivers/mmc/fsl_esdhc.c | 1 +
1 file changed, 1 insertion(+)
diff --git
T4240 eSDHC host capabilities reigster should have VS33 bit define.
Add quirk CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 to deal with capacity
missing
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V2:
- Rewrite
-by: Haijun Zhang haijun.zh...@freescale.com
---
drivers/mmc/fsl_esdhc.c | 10 +-
include/fsl_esdhc.h | 3 ++-
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index dc1d002..5aa592b 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b
Fill the right command type when using CMD12 to stop data transfer.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
CC: Fleming Andrew-AFLEMING aflem...@freescale.com
CC: Scott Wood scottw...@freescale.com
---
drivers/mmc/fsl_esdhc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
From: Haijun.Zhang haijun.zh...@freescale.com
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
CC: Scott Wood scottw...@freescale.com
CC: Sun Yusong-R58495 york...@freescale.com
---
board/freescale/p1_p2_rdb_pc/ddr.c | 2 +-
board
...@freescale.com
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
CC: Scott Wood scottw...@freescale.com
CC: Sun Yusong-R58495 york...@freescale.com
---
changes for V2:
- Add change log and update the config name for pc board
board/freescale/p1_p2_rdb_pc/README | 1 +
board
From: Haijun.Zhang haijun.zh...@freescale.com
The logic for the whether to configure for polling or DMA
was mistakenly reversed in this patch:
Commit 7b43db92110ec2f15c5f7187a165f2928464966b
drivers/mmc/fsl_esdhc.c: fix compiler warnings
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
CC
From: Haijun.Zhang haijun.zh...@freescale.com
The logic for the whether to configure for polling or DMA
was mistakenly reversed in this patch:
Commit 7b43db92110ec2f15c5f7187a165f2928464966b
drivers/mmc/fsl_esdhc.c: fix compiler warnings
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
CC
From: Haijun.Zhang haijun.zh...@freescale.com
Add platform support for p1020rdb-pd
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
CC: Sun Yusong-R58495 york...@freescale.com
CC: u-boot@lists.denx.de
---
board/freescale
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