Populate the device tree with the MC reserved memory regions.
Signed-off-by: Laurentiu Tudor
---
board/freescale/ls1088a/ls1088a.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/freescale/ls1088a/ls1088a.c
b/board/freescale/ls1088a/ls1088a.c
index 65593f10a3f5..7674e31a268a 100644
Populate the device tree with the MC reserved memory regions.
Signed-off-by: Laurentiu Tudor
---
board/freescale/ls2080aqds/ls2080aqds.c | 1 +
board/freescale/ls2080ardb/ls2080ardb.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c
b/board
.
For now this support is used only on LX2160A SoCs.
Signed-off-by: Laurentiu Tudor
---
board/freescale/lx2160a/lx2160a.c | 1 +
drivers/net/fsl-mc/mc.c | 110 ++
include/fsl-mc/fsl_mc.h | 1 +
3 files changed, 112 insertions(+)
diff --git
Some functions are not used outside this file, so make them static.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/icid.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
b/arch/arm/cpu/armv8/fsl
.
Changes in v2:
- added a cover letter
- dropped patch creating useless bypass mapping in SMMU
Laurentiu Tudor (4):
armv8: fsl-layerscape: make some functions static
drivers: net: fsl-mc: add support for MC reserved memory
board: freescale: ls2080a: declare MC reserved regions
board
On 9/6/2023 11:09 PM, Robin Murphy wrote:
> On 2023-09-06 19:10, Laurentiu Tudor wrote:
>>
>>
>> On 9/6/2023 8:21 PM, Robin Murphy wrote:
>>> On 2023-09-06 17:01, Laurentiu Tudor wrote:
>>>> MC being a plain DMA master as any other device in the SoC an
On 9/6/2023 8:21 PM, Robin Murphy wrote:
On 2023-09-06 17:01, Laurentiu Tudor wrote:
MC being a plain DMA master as any other device in the SoC and
being live at OS boot time, as soon as the SMMU is probed it
will immediately start triggering faults because there is no
mapping in the SMMU
Populate the device tree with the MC reserved memory regions.
Signed-off-by: Laurentiu Tudor
---
board/freescale/ls1088a/ls1088a.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/freescale/ls1088a/ls1088a.c
b/board/freescale/ls1088a/ls1088a.c
index 65593f10a3f5..7674e31a268a 100644
Populate the device tree with the MC reserved memory regions.
Signed-off-by: Laurentiu Tudor
---
board/freescale/ls2080aqds/ls2080aqds.c | 1 +
board/freescale/ls2080ardb/ls2080ardb.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c
b/board
it.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 26 ---
.../asm/arch-fsl-layerscape/immap_lsch3.h | 9 +++
2 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8
.
For now this support is used only on LX2160A SoCs.
Signed-off-by: Laurentiu Tudor
---
board/freescale/lx2160a/lx2160a.c | 1 +
drivers/net/fsl-mc/mc.c | 110 ++
include/fsl-mc/fsl_mc.h | 1 +
3 files changed, 112 insertions(+)
diff --git
Some functions are not used outside this file, so make them static.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/icid.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
b/arch/arm/cpu/armv8/fsl
Hi Tom,
On 8/23/2023 5:43 PM, Tom Rini wrote:
On Wed, Aug 23, 2023 at 04:25:43PM +0300, laurentiu.tu...@nxp.com wrote:
From: Laurentiu Tudor
Support for this in-house secure firmware was discontinued long time
ago so remove it. First couple of patches delete the defconfigs that
use it (split
From: Laurentiu Tudor
PPA was a secure firmware developed in-house which is no longer
supported and replaced by TF-A quite some years ago. This makes
the defconfigs that make use of PPA obsolete, so remove them.
Signed-off-by: Laurentiu Tudor
---
configs/ls1046aqds_SECURE_BOOT_defconfig
From: Laurentiu Tudor
PPA was a secure firmware developed in-house which is no longer
supported and replaced by TF-A quite some years ago. This makes
the defconfigs that make use of PPA obsolete, so remove them.
Signed-off-by: Laurentiu Tudor
---
configs/ls1012a2g5rdb_qspi_defconfig
From: Laurentiu Tudor
PPA was a secure firmware developed in-house which is no longer
supported and replaced by TF-A quite some years ago. Drop support
for it.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 60
arch/arm/cpu/armv8/fsl-layerscape
From: Laurentiu Tudor
Support for this in-house secure firmware was discontinued long time
ago so remove it. First couple of patches delete the defconfigs that
use it (split in two to be <100KB) and the third one removes the
actual PPA support.
Changes in v3:
- fixed some merge confli
From: Laurentiu Tudor
PPA was a secure firmware developed in-house which is no longer
supported and replaced by TF-A quite some years ago. This makes
the defconfigs that make use of PPA obsolete, so remove them.
Signed-off-by: Laurentiu Tudor
---
configs/ls1046aqds_SECURE_BOOT_defconfig
From: Laurentiu Tudor
PPA was a secure firmware developed in-house which is no longer
supported and replaced by TF-A quite some years ago. This makes
the defconfigs that make use of PPA obsolete, so remove them.
Signed-off-by: Laurentiu Tudor
---
configs/ls1012a2g5rdb_qspi_defconfig
From: Laurentiu Tudor
PPA was a secure firmware developed in-house which is no longer
supported and replaced by TF-A quite some years ago. Drop support
for it.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 60
arch/arm/cpu/armv8/fsl-layerscape
From: Laurentiu Tudor
Support for this in-house secure firmware was discontinued long time
ago so remove it. First couple of patches delete the defconfigs that
use it (split in two to be <100KB) and the third one removes the
actual PPA support.
Changes in v2:
- split the defconfig remo
From: Laurentiu Tudor
PPA was a secure firmware developed in-house which is no longer
supported and replaced by TF-A quite some years ago. Drop support
for it.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 60
arch/arm/cpu/armv8/fsl-layerscape
From: Laurentiu Tudor
Support for this in-house secure firmware was discontinued long time
ago so remove it. First patch deletes the defconfigs that use it and
the second one removes the actual support.
Laurentiu Tudor (2):
configs: layerscape: delete defconfigs using legacy PPA secure FW
Hi Zhiqiang,
On 3/5/2021 4:21 AM, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> The GICv3 RM requires "The first 1KB of memory for the LPI Pending tables
> must contain only zeros on initial allocation, and this must be visible
> to the Redistributors, or else the effect is UNPREDICTABLE".
>
>
From: Laurentiu Tudor
In the current implementation, u-boot creates iommu mappings only
for PCI devices enumarated at boot time thus does not take into
account more dynamic scenarios such as SR-IOV or PCI hot-plug.
Add an u-boot env var and a device tree property (to be used for
example in more
From: Laurentiu Tudor
Add a few defines related to PCI ARI configuration.
Signed-off-by: Laurentiu Tudor
---
include/pci.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/pci.h b/include/pci.h
index 1c5b36617e..d1ccf6c963 100644
--- a/include/pci.h
+++ b/include/pci.h
From: Laurentiu Tudor
In the current implementation, u-boot creates iommu mappings only
for PCI devices enumarated at boot time thus does not take into
account more dynamic scenarios such as SR-IOV or PCI hot-plug.
Add support for specifying extra IOMMU mappings for PCI
controllers through
From: Laurentiu Tudor
Fix duplication of this code by placing it in a common function.
Furthermore, the resulting function will be re-used in upcoming
patches.
Signed-off-by: Laurentiu Tudor
---
drivers/pci/pcie_layerscape_fixup.c | 76 +
1 file changed, 34
From: Laurentiu Tudor
Move the pci device related fdt fixup in a function in order to
re-use it in a following patch. While at it, improve the error
handling.
Signed-off-by: Laurentiu Tudor
---
drivers/pci/pcie_layerscape_fixup.c | 60 -
1 file changed, 34
From: Laurentiu Tudor
In the current implementation, u-boot creates iommu mappings only
for PCI devices enumarated at boot time thus does not take into
account more dynamic scenarios such as SR-IOV or PCI hot-plug.
Add an u-boot env var and a device tree property (to be used for
example in more
From: Laurentiu Tudor
Add a few defines related to PCI ARI configuration.
Signed-off-by: Laurentiu Tudor
---
include/pci.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/pci.h b/include/pci.h
index 1c5b36617e..d1ccf6c963 100644
--- a/include/pci.h
+++ b/include/pci.h
From: Laurentiu Tudor
Fix duplication of this code by placing it in a common function.
Furthermore, the resulting function will be re-used in upcoming
patches.
Signed-off-by: Laurentiu Tudor
---
drivers/pci/pcie_layerscape_fixup.c | 78 +
1 file changed, 36
From: Laurentiu Tudor
Move the pci device related fdt fixup in a function in order to
re-use it in a following patch. While at it, improve the error
handling.
Signed-off-by: Laurentiu Tudor
---
drivers/pci/pcie_layerscape_fixup.c | 60 -
1 file changed, 34
From: Laurentiu Tudor
In the current implementation, u-boot creates iommu mappings only
for PCI devices enumarated at boot time thus does not take into
account more dynamic scenarios such as SR-IOV or PCI hot-plug.
Add support for specifying extra IOMMU mappings for PCI
controllers through
From: Laurentiu Tudor
In the current implementation, u-boot creates iommu mappings only
for PCI devices enumarated at boot time thus does not take into
account more dynamic scenarios such as SR-IOV or PCI hot-plug.
Add an u-boot env var and a device tree property (to be used for
example in more
From: Laurentiu Tudor
Add a few defines related to ARI and SRIOV configuration.
Signed-off-by: Laurentiu Tudor
---
include/pci.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/include/pci.h b/include/pci.h
index 2089db9f16..88a09505a5 100644
--- a/include/pci.h
+++ b
From: Laurentiu Tudor
Move the pci device related fdt fixup in a function in order to
re-use it in a following patch. While at it, improve the error
handling.
Signed-off-by: Laurentiu Tudor
---
drivers/pci/pcie_layerscape_fixup.c | 60 -
1 file changed, 34
From: Laurentiu Tudor
Fix duplication of this code by placing it in a common function.
Furthermore, the resulting function will be re-used in upcoming
patches.
Signed-off-by: Laurentiu Tudor
---
drivers/pci/pcie_layerscape_fixup.c | 68 +
1 file changed, 30
From: Laurentiu Tudor
In the current implementation, u-boot creates iommu mappings only
for PCI devices enumarated at boot time thus does not take into
account more dynamic scenarios such as SR-IOV or PCI hot-plug.
Add support for specifying extra IOMMU mappings for PCI
controllers through
From: Laurentiu Tudor
In the current implementation, u-boot creates iommu mappings only
for PCI devices enumarated at boot time thus does not take into
account more dynamic scenarios such as SR-IOV or PCI hot-plug.
Add an u-boot env var and a device tree property (to be used for
example in more
From: Laurentiu Tudor
Add a few defines related to ARI and SRIOV configuration.
Signed-off-by: Laurentiu Tudor
---
include/pci.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/include/pci.h b/include/pci.h
index 281f353916..c76b73497d 100644
--- a/include/pci.h
+++ b/include
From: Laurentiu Tudor
In the current implementation, u-boot creates iommu mappings only
for PCI devices enumarated at boot time thus does not take into
account more dynamic scenarios such as SR-IOV or PCI hot-plug.
Add support for specifying extra IOMMU mappings for PCI
controllers through
From: Laurentiu Tudor
Fix duplication of this code by placing it in a common function.
Furthermore, the resulting function will be re-used in upcoming
patches.
Signed-off-by: Laurentiu Tudor
---
drivers/pci/pcie_layerscape_fixup.c | 87 ++---
1 file changed, 30
From: Laurentiu Tudor
Move the pci device related fdt fixup in a function in order to
re-use it in a following patch. While at it, improve the error
handling.
Signed-off-by: Laurentiu Tudor
---
drivers/pci/pcie_layerscape_fixup.c | 58 -
1 file changed, 33
From: Laurentiu Tudor
Move the pci device related fdt fixup in a function in order to
re-use it in a following patch. While at it, improve the error
handling.
Signed-off-by: Laurentiu Tudor
---
drivers/pci/pcie_layerscape_fixup.c | 58 -
1 file changed, 33
From: Laurentiu Tudor
In the current implementation, u-boot creates iommu mappings only
for PCI devices enumarated at boot time thus does not take into
account more dynamic scenarios such as SR-IOV or PCI hot-plug.
Add an u-boot env var and a device tree property (to be used for
example in more
From: Laurentiu Tudor
In the current implementation, u-boot creates iommu mappings only
for PCI devices enumarated at boot time thus does not take into
account more dynamic scenarios such as SR-IOV or PCI hot-plug.
Add support for specifying extra IOMMU mappings for PCI
controllers through
From: Laurentiu Tudor
Fix duplication of this code by placing it in a common function.
Furthermore, the resulting function will be re-used in upcoming
patches.
Signed-off-by: Laurentiu Tudor
---
drivers/pci/pcie_layerscape_fixup.c | 87 ++---
1 file changed, 30
Similarly to iommu-map, the msi-map property must also be fixed up
in the device tree, in order for the icid -> streamid translation
be possible in the MSI case as well.
Signed-off-by: Laurentiu Tudor
---
drivers/net/fsl-mc/mc.c | 17 -
1 file changed, 16 insertions(+)
ver letter
Laurentiu Tudor (2):
fdtdec: support multiple phandles in memory carveout
test: fdtdec: test fdtdec_set_carveout()
lib/fdtdec.c | 36 +
test/dm/Makefile | 1 +
test/dm/fdtdec.c | 60
3 files changed, 87
fdtdec_set_carveout() is limited to only one phandle. Fix this
limitation by adding support for multiple phandles.
Signed-off-by: Laurentiu Tudor
---
lib/fdtdec.c | 36 ++--
1 file changed, 26 insertions(+), 10 deletions(-)
diff --git a/lib/fdtdec.c b/lib
Add a new test for fdtdec_set_carveout().
Signed-off-by: Laurentiu Tudor
---
test/dm/Makefile | 1 +
test/dm/fdtdec.c | 60
2 files changed, 61 insertions(+)
create mode 100644 test/dm/fdtdec.c
diff --git a/test/dm/Makefile b/test/dm/Makefile
Hi Simon,
On 4/2/2020 5:34 AM, Simon Glass wrote:
> Hi,
>
> On Tue, 31 Mar 2020 at 07:16, Laurentiu Tudor wrote:
>>
>> fdtdec_set_carveout() is limited to only one phandle. Fix this
>> limitation by adding support for multiple phandles.
>>
>> Signed-
fdtdec_set_carveout() is limited to only one phandle. Fix this
limitation by adding support for multiple phandles.
Signed-off-by: Laurentiu Tudor
---
lib/fdtdec.c | 36 ++--
1 file changed, 26 insertions(+), 10 deletions(-)
diff --git a/lib/fdtdec.c b/lib
Hi Priyanka,
On 18.10.2019 12:01, Laurentiu Tudor wrote:
> From: Laurentiu Tudor
>
> These macros should only be used when CONFIG_FSL_CAAM is present.
>
> Signed-off-by: Laurentiu Tudor
> Reviewed-by: Horia Geant??
Looks like our mail server messed Horia's name here. Do yo
From: Laurentiu Tudor
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec.
Signed-off-by: Laurentiu Tudor
Reviewed-by: Horia Geant??
---
Changes in v2:
- added Reviewed-by tag
arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
.../arm/cpu/armv8/fsl
From: Laurentiu Tudor
Erratum A-050382 states that the eDMA ICID programmed in the eDMA_AMQR
register in DCFG is not correctly forwarded to the SMMU.
The workaround consists in programming the eDMA ICID in the eDMA_AMQR
register in DCFG to 40.
Signed-off-by: Laurentiu Tudor
---
Changes in v2
From: Laurentiu Tudor
LX2160A chips have 4 sata controllers. Add missing base addresses for
SATA3 and SATA4.
Signed-off-by: Laurentiu Tudor
---
Changes in v2:
- explicitly mention the chip on which these are needed (Priyanka)
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++
1
From: Laurentiu Tudor
If SEC FW support is not enabled (ARMV8_SEC_FIRMWARE_SUPPORT=n) this
compilation error happens:
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h:169:4: error:
'CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT' undeclared here (not in a function)
Fix it by wrapping
From: Laurentiu Tudor
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec.
Signed-off-by: Laurentiu Tudor
---
Changes in v2:
- setup ICIDs for all 6 DECOs not only 4 (Horia)
arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
.../arm/cpu/armv8/fsl
From: Laurentiu Tudor
These macros should only be used when CONFIG_FSL_CAAM is present.
Signed-off-by: Laurentiu Tudor
Reviewed-by: Horia Geant??
---
Changes in v2:
- added Reviewed-by tag
arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c | 2 ++
arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
On 18.10.2019 09:20, Priyanka Jain wrote:
>
>
>> -Original Message-
>> From: u-boot-boun...@linux.nxdi.nxp.com > boun...@linux.nxdi.nxp.com> On Behalf Of Laurentiu Tudor
>> Sent: Thursday, October 17, 2019 2:52 PM
>> To: u-boot@lists.denx.de; Prabha
On 18.10.2019 09:32, Horia Geanta wrote:
> On 10/17/2019 12:21 PM, Laurentiu Tudor wrote:
>> From: Laurentiu Tudor
>>
>> If SEC FW support is not enabled (ARMV8_SEC_FIRMWARE_SUPPORT=n) this
>> compilation error happens:
>> arch/arm/include/asm/arch-fsl-l
From: Laurentiu Tudor
Description:
The eDMA ICID programmed in the eDMA_AMQR register in DCFG is not
correctly forwarded to the SMMU.
Workaround:
Program eDMA ICID in the eDMA_AMQR register in DCFG to 0x28.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
From: Laurentiu Tudor
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
.../arm/cpu/armv8/fsl-layerscape/lx2160_ids.c | 48 +++
arch/arm/cpu/armv8/fsl
From: Laurentiu Tudor
There are chips that have 4 sata controllers. Add missing base
addresses for SATA3 and SATA4.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl
From: Laurentiu Tudor
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
.../arm/cpu/armv8/fsl-layerscape/ls2088_ids.c | 33 +++
arch/arm/cpu/armv8/fsl
From: Laurentiu Tudor
If SEC FW support is not enabled (ARMV8_SEC_FIRMWARE_SUPPORT=n) this
compilation error happens:
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h:169:4: error:
'CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT' undeclared here (not in a function)
Fix it by adding an intermediate macro
From: Laurentiu Tudor
These macros should only be used when CONFIG_FSL_CAAM is present.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c | 2 ++
arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/cpu
From: Laurentiu Tudor
The current implementation assumes that the registers holding the ICIDs
are universally big endian. That's no longer the case on newer
platforms so update the code to take into account the endianness of
each register.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8
From: Laurentiu Tudor
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec. The ICID macros for SEC needed to be adapted because
the format of the registers is different.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1
From: Laurentiu Tudor
Add CCSR base addresses for ESDHC2, EDMA QDMA, DISPLAY and GPU devices.
Signed-off-by: Laurentiu Tudor
---
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape
From: Laurentiu Tudor
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, edma, qdma, gpu, display and sec.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
.../arm/cpu/armv8/fsl-layerscape/ls1028_ids.c | 33
From: Laurentiu Tudor
Add defines for all the SEC job rings base addresses.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm
On 21.03.2019 17:10, Horia Geanta wrote:
> On 3/21/2019 2:42 PM, Tudor Laurentiu-B10716 wrote:
>> Hi Horia,
>>
>> On 21.03.2019 12:36, Horia Geanta wrote:
>>> On 3/20/2019 4:31 PM, laurentiu.tu...@nxp.com wrote:
#define SET_SEC_QI_ICID(streamid) \
- SET_ICID_ENTRY("fsl,sec-v4.0",
Hi Horia,
On 21.03.2019 12:36, Horia Geanta wrote:
> On 3/20/2019 4:31 PM, laurentiu.tu...@nxp.com wrote:
>> +struct icid_id_table icid_tbl[] = {
>> +SET_SDHC_ICID(FSL_SDMMC_STREAM_ID),
>> +SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
>> +SET_USB_ICID(2, "snps,dwc3",
Hi Horia,
On 21.03.2019 12:36, Horia Geanta wrote:
> On 3/20/2019 4:31 PM, laurentiu.tu...@nxp.com wrote:
>> +struct icid_id_table icid_tbl[] = {
>> +SET_SDHC_ICID(FSL_SDMMC_STREAM_ID),
>> +SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
>> +SET_USB_ICID(2, "snps,dwc3",
Hi Horia,
On 21.03.2019 12:36, Horia Geanta wrote:
> On 3/20/2019 4:31 PM, laurentiu.tu...@nxp.com wrote:
>> +struct icid_id_table icid_tbl[] = {
>> +SET_SDHC_ICID(FSL_SDMMC_STREAM_ID),
>> +SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
>> +SET_USB_ICID(2, "snps,dwc3",
Hello,
Please disregards these 3 patches as I've resubmitted them by mistake.
I've updated their state in patchworks accordingly.
---
Best regards, Laurentiu
On 20.03.2019 16:31, laurentiu.tu...@nxp.com wrote:
> From: Laurentiu Tudor
>
> On Layerscape architectures the SEC memory m
From: Laurentiu Tudor
The SEC QI ICID setup in the QIIC_LS register is actually an offset
that is being added to the ICID coming from the qman portal. Setting
it with a non-zero value breaks SMMU setup as the resulting ICID is
not known. On top of that, the SEC QI ICID must match the qman portal
From: Laurentiu Tudor
sec_firmware reserves JR3 for it's own usage and deletes the JR3 node
from the device tree. This causes this warning to be issued when doing
the device tree fixup:
WARNING could not find node fsl,sec-v4.0-job-ring: FDT_ERR_NOTFOUND.
Fix it by excluding the device tree
From: Laurentiu Tudor
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec. The ICID macros for SEC needed to be adapted because
the format of the registers is different. Also, the initial static ICID
allocation left SEC out so update it by grabbing an ICID from
From: Laurentiu Tudor
On Layerscape architectures the SEC memory map is 1MB and the
register blocks contained in it are 64KB aligned, not 4KB as
the ccsr_sec structure currently assumes. Fix the layout of
the structure for these architectures.
Signed-off-by: Laurentiu Tudor
Reviewed-by: Horia
From: Laurentiu Tudor
Add defines for all the SEC job rings base addresses.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm
o be ignored by MC.
>
> Fixes: 1161dbcc0a36 ("drivers: net: fsl-mc: Include MAC addr fixup to DPL")
>
> Signed-off-by: Ioana Radulescu
> ---
> drivers/net/fsl-mc/mc.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Lau
From: Laurentiu Tudor
sec_firmware reserves JR3 for it's own usage and deletes the JR3 node
from the device tree. This causes this warning to be issued when doing
the device tree fixup:
WARNING could not find node fsl,sec-v4.0-job-ring: FDT_ERR_NOTFOUND.
Fix it by excluding the device tree
From: Laurentiu Tudor
The SEC QI ICID setup in the QIIC_LS register is actually an offset
that is being added to the ICID coming from the qman portal. Setting
it with a non-zero value breaks SMMU setup as the resulting ICID is
not known. On top of that, the SEC QI ICID must match the qman portal
From: Laurentiu Tudor
On Layerscape architectures the SEC memory map is 1MB and the
register blocks contained in it are 64KB aligned, not 4KB as
the ccsr_sec structure currently assumes. Fix the layout of
the structure for these architectures.
Signed-off-by: Laurentiu Tudor
Reviewed-by: Horia
From: Laurentiu Tudor
sec_firmware reserves JR3 for it's own usage and deletes the JR3 node
from the device tree. This causes this warning to be issued when doing
the device tree fixup:
WARNING could not find node fsl,sec-v4.0-job-ring: FDT_ERR_NOTFOUND.
Fix it by excluding the device tree
From: Laurentiu Tudor
The SEC QI ICID setup in the QIIC_LS register is actually an offset
that is being added to the ICID coming from the qman portal. Setting
it with a non-zero value breaks SMMU setup as the resulting ICID is
not known. On top of that, the SEC QI ICID must match the qman portal
From: Laurentiu Tudor
On Layerscape architectures the SEC memory map is 1MB and the
register blocks contained in it are 64KB aligned, not 4KB as
the ccsr_sec structure currently assumes. Fix the layout of
the structure for these architectures.
Signed-off-by: Laurentiu Tudor
---
include
xdi.nxp.com > boun...@linux.nxdi.nxp.com> On Behalf Of laurentiu.tu...@nxp.com
>> Sent: Wednesday, January 30, 2019 5:31 PM
>> To: u-boot@lists.denx.de; Prabhakar Kushwaha
>> ; York Sun
>> Cc: Laurentiu Tudor
>> Subject: [upstream-release] [PATCH] pci: layerscape: add opt
From: Laurentiu Tudor
Certain PCI scenarios have more dynamic requirements, e.g. endpoints
are "hot-plugged" later in the system lifetime. Add a Kconfig option
that allows specifying a maximum number of end-points, per PCI controller
and allocate a StreamID for each one.
From: Laurentiu Tudor
sec_firmware reserves JR3 for it's own usage and deletes the JR3 node
from the device tree. This causes this warning to be issued when doing
the device tree fixup:
WARNING could not find node fsl,sec-v4.0-job-ring: FDT_ERR_NOTFOUND.
Fix it by excluding the device tree
From: Laurentiu Tudor
The SEC QI ICID setup in the QIIC_LS register is actually an offset
that is being added to the ICID coming from the qman portal. Setting
it with a non-zero value breaks SMMU setup as the resulting ICID is
not known. On top of that, the SEC QI ICID must match the qman portal
From: Laurentiu Tudor
On Layerscape architectures the SEC memory map is 1MB and the
register blocks contained in it are 64KB aligned, not 4KB as
the ccsr_sec structure currently assumes. Fix the layout of
the structure for these architectures.
Signed-off-by: Laurentiu Tudor
---
include
From: Laurentiu Tudor
The ICIDs for the qdma device are not configured through SCFG but
through some registers found in the actual device register block.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h| 6 +-
arch/arm/include/asm/arch-fsl
From: Laurentiu Tudor
Enable support for ICID setup of qman portals and the required device
tree fixups.
Signed-off-by: Laurentiu Tudor
---
drivers/misc/fsl_portals.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/misc/fsl_portals.c b/drivers/misc
From: Laurentiu Tudor
The QMan IP block in this SoC is version 3.2 so advertise
this in the SoC configuration header.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-fsl
From: Laurentiu Tudor
Reuse the existing ICID setup code done for LS1046A smmu enablement
and add the equivalent setup for LS1043A chips.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
.../arm/cpu/armv8/fsl-layerscape/ls1043_ids.c | 90
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