andard extension for Single-Precision Floating Point"
> + default y
Shall this default y need to depend on RV32 ?
Reviewed-by: Rick Chen
> + help
> + Adds "F" to the ISA string passed to the compiler.
> +
> +config RISCV_ISA_D
> +
cv/include/asm/spl.h | 1 +
> arch/riscv/lib/Makefile | 2 ++
> arch/riscv/lib/interrupts.c | 25 +
> arch/riscv/lib/semihosting.c | 24
> lib/Kconfig | 10 +-
> 5 files changed, 57 insertions(+), 5 deletions(-) create mode 100644
> arch/riscv/lib/semihosting.c
Reviewed-by: Rick Chen
configs/qemu-riscv32_smode_defconfig | 4
> configs/qemu-riscv32_spl_defconfig | 7 +++
> configs/qemu-riscv64_defconfig | 4
> configs/qemu-riscv64_smode_defconfig | 4
> configs/qemu-riscv64_spl_defconfig | 7 +++
> 6 files changed, 30 insertions(+)
Reviewed-by: Rick Chen
buildman: differentiate between riscv32, riscv64
>
> riscv32 needs a different toolchain than riscv64
>
> Signed-off-by: Heinrich Schuchardt
> ---
> v4:
> no change
> v3:
> new patch
> ---
> tools/buildman/boards.py | 11 +++
> 1 file changed, 11 insertions(+)
Reviewed-by: Rick Chen
drop riscv toolchain-alias
> v3:
> new patch
> ---
> tools/docker/Dockerfile | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rick Chen
arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0'
>
> Signed-off-by: Alexandre Ghiti
> Reviewed-by: Bin Meng
> Tested-by: Heinrich Schuchardt
> Tested-by: Heiko Stuebner
> Tested-by: Christian Stewart
> ---
> v3:
> no change
> ---
> arch/riscv/Makefile | 11 ++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
Reviewed-by: Rick Chen
nd use the same short texts for the legacy extensions as the
> SBI specification 1.0.0.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> cmd/riscv/sbi.c | 18 +-
> 1 file changed, 9 insertions(+), 9 deletions(-)
Reviewed-by: Rick Chen
ling 'Get SBI specification version' fails, write an error message and
> return CMD_RET_FAILURE.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> cmd/riscv/sbi.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
Reviewed-by: Rick Chen
rint out the version number of the SBI implementation.
> Choose the correct output format for RustSBI.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> cmd/riscv/sbi.c | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Rick Chen
> From: Nikita Shubin
> Sent: Friday, September 02, 2022 4:48 PM
> To: u-boot@lists.denx.de
> Cc: li...@yadro.com; Sean Anderson ; Rick Chen
> ; Nikita Shubin ; Rick Jian-Zhi
> Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊)
> ; Simon Glass ; Bin Meng
> ; Ilias Apalodimas
HI all,
> On Mon, 5 Sep 2022 11:30:38 -0400
> Sean Anderson wrote:
>
> > On 9/5/22 3:47 AM, Nikita Shubin wrote:
> > > Hi Rick!
> > >
> > > On Mon, 5 Sep 2022 14:22:41 +0800
> > > Rick Chen wrote:
> > >
> > >> Hi,
> >
Hi,
When I free-run a SMP system, I once hit a failure case where some
harts didn't boot to the kernel shell successfully.
However it can't be duplicated anymore even if I try many times.
But when I set a break during debugging with GDB, it can trigger the
failure case each time.
I think the
; #include
> #include
>
> -#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */
> +#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 2) /* 250 ms */
Reviewed-by: Rick Chen
Hi Nikita,
> From: Nikita Shubin
> Sent: Wednesday, August 31, 2022 3:25 PM
> To: u-boot@lists.denx.de
> Cc: li...@yadro.com; Nikita Shubin ; Rick Jian-Zhi
> Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊)
> ; Simon Glass ; Bin Meng
> ; Heinrich Schuchardt ; Ilias
> Apalodimas ; Alexandru Gagniuc
> ;
MAGE_ENABLE_OF_LIBFDT")
> Signed-off-by: Michal Simek
> ---
>
> arch/arm/lib/bootm.c | 2 --
> arch/riscv/lib/bootm.c | 2 --
> 2 files changed, 4 deletions(-)
Reviewed-by: Rick Chen
> to the Kconfig file. If this is user configurable, it needs to be exposed
> rather than hidden, and should probably be renamed as well.
>
> Cc: Rick Chen
> Signed-off-by: Tom Rini
> ---
> board/AndesTech/ax25-ae350/Kconfig | 4
> include/configs/ax25-ae350.h |
> On Fri, Apr 22, 2022 at 04:45:28PM +0800, Rick Chen wrote:
> > Hi, Tom,
> >
> > > From: Tom Rini
> > > Sent: Wednesday, April 20, 2022 2:43 AM
> > > To: u-boot@lists.denx.de; Rick Jian-Zhi Chen(陳建志)
> > > Subject: Re: [PATCH] nds32: Remov
as been ack'd for the Linux kernel, remove
> > support here as well.
> >
> > Cc: Rick Chen
> > Signed-off-by: Tom Rini
>
> Ping?
Sorry for the late responses.
Thanks for the information.
Thanks,
Rick
>
> --
> Tom
>
> Move the setting to /Kconfig where we define SYS_MALLOC_F_LEN for other
> architectures too.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> v2:
> move the setting to /Kconfig
> ---
> Kconfig| 2 +-
> arch/riscv/Kconfig | 3 ---
> 2 files changed, 1 insertion(+), 4 deletions(-)
Reviewed-by: Rick Chen
HI Anup,
> From: Anup Patel
> Sent: Sunday, February 06, 2022 4:41 PM
> To: Rick Jian-Zhi Chen(陳建志)
> Cc: Bin Meng ; Atish Patra ;
> Alistair Francis ; Anup Patel
> ; U-Boot Mailing List
> Subject: Re: [PATCH v2 0/4] QEMU spike machine support for U-Boot
>
> Hi Rick,
>
> On Thu, Jan 27, 2022
or qemu-riscv board which will return 1
> only if CFI flash DT node is present.
>
> Fixes: d248627f9d42 ("riscv: qemu: Enable MTD NOR flash support")
> Signed-off-by: Anup Patel
> ---
> board/emulation/qemu-riscv/qemu-riscv.c | 17 +++++
> 1 file changed, 17 insertions(+)
Reviewed-by: Rick Chen
console support
>
> Enable support for HTIF console so that we can use QEMU RISC-V U-Boot on
> RISC-V emulators and ISS having it.
>
> Signed-off-by: Anup Patel
> Reviewed-by: Philipp Tomsich
> ---
> board/emulation/qemu-riscv/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Rick Chen
f-by: Anup Patel
> Reviewed-by: Philipp Tomsich
> ---
> drivers/serial/Kconfig | 8 ++
> drivers/serial/Makefile | 1 +
> drivers/serial/serial_htif.c | 178 +++
> 3 files changed, 187 insertions(+)
Reviewed-by: Rick Chen
"
>
> echo $cmd
> eval $cmd
> }
>
> The address where the kernel is loaded can be altered by changing the value
> of KERNEL_IMAGE_ADDR.
>
> Signed-off-by: Leo Yu-Chi Liang
> ---
> include/configs/ax25-ae350.h | 13 -
> 1 file changed, 12 insertions(+), 1 deletion(-)
Reviewed-by: Rick Chen
> Hi Rick,
>
> On Mon, Oct 25, 2021 at 10:24 AM Rick Chen wrote:
> >
> > Hi, Bin
> >
> > > Hi Rick,
> > >
> > > On Mon, Oct 25, 2021 at 9:49 AM Rick Chen wrote:
> > > >
> > > > Hi Bin,
> > > >
> >
/include/linux/kconfig.h,
> CONFIG_IS_ENABLED(OF_BOARD) expands to 0 when CONFIG_SPL_BUILD is defined
> because there is no CONFIG_SPL_OF_BOARD.
>
> Use #if defined instead.
>
> Signed-off-by: Leo Yu-Chi Liang
> ---
> board/AndesTech/ax25-ae350/ax25-ae350.c | 4 ++--
> 1 file changed,
> include/configs/imx8qxp_mek.h | 2 --
> 8 files changed, 2 insertions(+), 15 deletions(-)
Reviewed-by: Rick Chen
show the SBI implementation version
>
> Signed-off-by: Heinrich Schuchardt
> ---
> cmd/riscv/sbi.c | 26 ++
> 1 file changed, 18 insertions(+), 8 deletions(-)
Reviewed-by: Rick Chen
>
> Provide function sbi_get_impl_version() to retrieve the SBI implementation
> version.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> arch/riscv/include/asm/sbi.h | 1 +
> arch/riscv/lib/sbi.c | 19 +++
> 2 files changed, 20 insertions(+)
Reviewed-by: Rick Chen
Hi, Bin
> Hi Rick,
>
> On Mon, Oct 25, 2021 at 9:49 AM Rick Chen wrote:
> >
> > Hi Bin,
> >
> > > From: Bin Meng
> > > Sent: Tuesday, October 19, 2021 4:55 PM
> > > To: Alexandre Ghiti
> > > Cc: Heinrich Schuchardt ; Tom Rini
t; > #define CONFIG_SPL_STACK (0x0800 + 0x001D - \
> > > > GENERATED_GBL_DATA_SIZE)
> > >
> > > What caused this?
> > >
> > > Last time this was seen on Ax25-AE350, CONFIG_SPL_SYS_MALLOC_F_LEN
> &
in the beginning, u-boot-spl would
> sometimes fail to boot to u-boot proper.
>
> Enable CM and I/D cache at the same time in harts_early_init
>
> Signed-off-by: Leo Yu-Chi Liang
> ---
> arch/riscv/cpu/ax25/cpu.c | 42 +++
> 1 file changed, 42 insertions(+)
Reviewed-by: Rick Chen
unleashed.c | 4 ++--
> board/sifive/unmatched/unmatched.c | 4 ++--
> 2 files changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Rick Chen
9f179a ("riscv: Provide a mechanism to fix DT for reserved
> memory")
> Signed-off-by: Samuel Holland
> ---
>
> arch/riscv/lib/fdt_fixup.c | 5 +----
> 1 file changed, 1 insertion(+), 4 deletions(-)
Reviewed-by: Rick Chen
>
> Add arch_lmb_reserve() implemented using arch_lmb_reserve_generic().
> It is rather likely this architecture also needs to cover U-Boot with LMB
> before booting Linux.
>
> Signed-off-by: Marek Vasut
> Cc: Atish Patra
> Cc: Leo
> Cc: Rick Chen
> Cc: Simon Goldsc
reserve() implemented using arch_lmb_reserve_generic().
> It is rather likely this architecture also needs to cover U-Boot with LMB
> before booting Linux.
>
> Signed-off-by: Marek Vasut
> Cc: Rick Chen
> Cc: Simon Goldschmidt
> Cc: Tom Rini
> ---
> arch/nds32/lib/bootm.c | 13 +
n/board_r.c | 4 ++--
> 2 files changed, 6 insertions(+), 2 deletions(-)
Reviewed-by: Rick Chen
; Subject: [PATCH v5 5/5] riscv: lib: modify the indent
>
> We usually use a space in function declaration, rather than a tab.
>
> Signed-off-by: Zong Li
> Reviewed-by: Sean Anderson
> ---
> arch/riscv/include/asm/cache.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rick Chen
-
> arch/riscv/include/asm/arch-fu540/cache.h | 14 --
> arch/riscv/include/asm/arch-fu740/cache.h | 14 --
> board/sifive/unleashed/unleashed.c| 10 +----
> board/sifive/unmatched/unmatched.c| 11 ++---
Reviewed-by: Rick Chen
interface of cache
> uclass to execute the relative implementation in SiFive ccache driver.
>
> Signed-off-by: Zong Li
> ---
> arch/riscv/Kconfig| 5 +
> arch/riscv/lib/Makefile | 1 +
> arch/riscv/lib/sifive_cache.c | 27 +++++++
> 3 files changed, 33 insertions(+)
Reviewed-by: Rick Chen
> From: Zong Li
> Sent: Tuesday, August 31, 2021 5:21 PM
> To: Rick Jian-Zhi Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊)
> ; bmeng...@gmail.com; sean...@gmail.com;
> green@sifive.com; paul.walms...@sifive.com; s...@chromium.org;
> u-boot@lists.denx.de
> Cc: Zong Li
> Subject: [PATCH v4 2/4] riscv:
.c | 75 +
> 3 files changed, 83 insertions(+)
> create mode 100644 drivers/cache/cache-sifive-ccache.c
Reviewed-by: Rick Chen
> ---
For riscv,
Reviewed-by: Rick Chen
; Cc: Daniel Schwierzeck
> Cc: Leo
> Cc: Palmer Dabbelt
> Cc: Paul Walmsley
> Cc: Rick Chen
> Cc: Sean Anderson
> Cc: Simon Glass
> Signed-off-by: Tom Rini
> ---
> I'm Cc'ing a bunch of RISC-V folks since that's where I'm least confident and
> just put it per-bo
configs/ae350_rv64_spl_xip_defconfig | 1 +
> configs/ae350_rv64_xip_defconfig | 1 +
Reviewed-by: Rick Chen
ivetree API for this driver.
>
> Signed-off-by: Simon Glass
> ---
>
> drivers/mmc/ftsdc010_mci.c | 22 +++---
> 1 file changed, 7 insertions(+), 15 deletions(-)
Reviewed-by: Rick Chen
; arch/riscv/cpu/fu740/spl.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rick Chen
ir interrupt parent have 2
> cells encoded in their interrupts property, but plic0 only provides 1 cell in
> #interrupt-cells which is incorrect.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/dts/ae350_32.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rick Chen
nodes, so #address-cells is not needed.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/dts/ae350_32.dts | 2 --
> arch/riscv/dts/ae350_64.dts | 2 --
> 2 files changed, 4 deletions(-)
Reviewed-by: Rick Chen
gt; Signed-off-by: Bin Meng
> ---
>
> arch/riscv/dts/ae350_32.dts | 2 ++
> arch/riscv/dts/ae350_64.dts | 2 ++
> 2 files changed, 4 insertions(+)
Reviewed-by: Rick Chen
> Hi Rick,
>
> On Sat, Jun 12, 2021 at 9:30 PM Rick Chen wrote:
> >
> > HI Bin
> >
> > > Hi Rick,
> > >
> > > On Wed, Jun 9, 2021 at 3:06 PM Rick Chen wrote:
> > > >
> > > > Hi Bin,
> > > >
> > > &
g on Andes hardware, which I don't have access to.
> >
> > arch/riscv/lib/andes_plic.c | 4 +++-
> > 1 file changed, 3 insertions(+), 1 deletion(-)
> >
>
> Ping?
Though there will be only one hart will jump to U-Boot proper currently,
and this delay loop seem to be unnecessary.
But it is still a good catch.
Thanks,
Rick
Tested-by: Rick Chen
Reviewed-by: Rick Chen
HI Bin
> Hi Rick,
>
> On Wed, Jun 9, 2021 at 3:06 PM Rick Chen wrote:
> >
> > Hi Bin,
> >
> > > From: Bin Meng
> > > Sent: Friday, June 04, 2021 1:51 PM
> > > To: Rick Jian-Zhi Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊)
> > > ; U-Boot
Hi Bin,
> From: Bin Meng
> Sent: Friday, June 04, 2021 1:51 PM
> To: Rick Jian-Zhi Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊)
> ; U-Boot Mailing List
> Subject: [PATCH 5/5] riscv: ae350: dts: Add missing "u-boot,dm-spl" for SPL
> config
>
> At present the AE350 SPL defconfig is using OF_PRIOR_STAGE.
ootargs. Drop one.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/dts/ae350_32.dts | 2 +-
> arch/riscv/dts/ae350_64.dts | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Rick Chen
s in ax25-ae350.h, while actually it
> is not. Remove it.
>
> Signed-off-by: Bin Meng
> ---
>
> doc/board/AndesTech/ax25-ae350.rst | 19 ---
> 1 file changed, 4 insertions(+), 15 deletions(-)
Reviewed-by: Rick Chen
> Reviewed-by: Bin Meng
> ---
> v2:
> fix typo in commit message
> ---
> common/board_f.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Rick Chen
ch/riscv/cpu/fu540/Kconfig | 2 +-
> arch/riscv/cpu/generic/Kconfig | 3 ++-
> arch/riscv/include/asm/global_data.h | 2 +-
> arch/riscv/lib/Makefile | 2 +-
> drivers/timer/Makefile | 2 +-
> 6 files changed, 14 insertions(+), 6 deletions(-)
Reviewed-by: Rick Chen
Hi Bin
> Hi Rick,
>
> On Wed, May 12, 2021 at 11:25 AM Rick Chen wrote:
> >
> > HI Bin,
> >
> > >
> > > > Hi Rick,
> > > >
> > > > On Tue, May 11, 2021 at 8:49 AM Rick Chen wrote:
> > > > >
> > > &g
> From: Bin Meng
> Sent: Friday, May 14, 2021 11:50 AM
> To: Green Wan
> Cc: Rick Jian-Zhi Chen(陳建志) ; Sean Anderson
> ; U-Boot Mailing List
> Subject: Re: [PATCH] Revert "riscv: cpu: fu740: clear feature disable CSR"
>
> On Fri, May 14, 2021 at 11:45 AM Green Wan wrote:
> >
> > Hi Bin,
> >
>
gt; Signed-off-by: Bin Meng
> ---
>
> doc/board/AndesTech/ax25-ae350.rst | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Rick Chen
/binman/etype/opensbi.py | 23 +++
> tools/binman/ftest.py | 7 +++
> tools/binman/test/201_opensbi.dts | 14 ++
> 4 files changed, 57 insertions(+)
Reviewed-by: Rick Chen
Bin Meng
> Reviewed-by: Simon Glass
> ---
>
> (no changes since v1)
>
> tools/binman/binman.rst | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Rick Chen
Bin Meng
> Reviewed-by: Simon Glass
> ---
>
> (no changes since v1)
>
> common/Kconfig.boot | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rick Chen
configs/ae350_rv64_spl_xip_defconfig | 2 ++
> 7 files changed, 13 insertions(+)
Reviewed-by: Rick Chen
HI Bin,
>
> > Hi Rick,
> >
> > On Tue, May 11, 2021 at 8:49 AM Rick Chen wrote:
> > >
> > > Hi Bin,
> > >
> > > > Hi Rick,
> > > >
> > > > On Mon, May 10, 2021 at 3:22 PM Rick Chen wrote:
> > >
> 1 file changed, 11 insertions(+), 10 deletions(-)
Reviewed-by: Rick Chen
> Hi Rick,
>
> On Tue, May 11, 2021 at 8:49 AM Rick Chen wrote:
> >
> > Hi Bin,
> >
> > > Hi Rick,
> > >
> > > On Mon, May 10, 2021 at 3:22 PM Rick Chen wrote:
> > > >
> > > > Hi Bin
> > > >
> > &g
/binman/etype/opensbi.py | 23 +++
> tools/binman/ftest.py | 7 +++
> tools/binman/test/201_opensbi.dts | 14 ++
> 4 files changed, 57 insertions(+)
Reviewed-by: Rick Chen
Hi Bin,
> Hi Rick,
>
> On Mon, May 10, 2021 at 3:22 PM Rick Chen wrote:
> >
> > Hi Bin
> >
> > > Hi Bin,
> > >
> > > > From: Bin Meng
> > > > Sent: Monday, May 10, 2021 2:58 PM
> > > > To: Simon Glass ; Rick Ji
Hi Bin
> Hi Bin,
>
> > From: Bin Meng
> > Sent: Monday, May 10, 2021 2:58 PM
> > To: Simon Glass ; Rick Jian-Zhi Chen(陳建志)
> > ; u-boot@lists.denx.de
> > Subject: [PATCH v4 00/13] riscv: Switch to use binman to generate u-boot.itb
> >
> > This series updates binman to handle creation of
Hi Bin,
> From: Bin Meng
> Sent: Monday, May 10, 2021 2:58 PM
> To: Simon Glass ; Rick Jian-Zhi Chen(陳建志)
> ; u-boot@lists.denx.de
> Subject: [PATCH v4 00/13] riscv: Switch to use binman to generate u-boot.itb
>
> This series updates binman to handle creation of u-boot.itb image for RISC-V
>
uot;riscv: Move all fdt fixups together")
> Signed-off-by: Sean Anderson
> ---
> I have not actually tested this (nor observed the original failure). But this
> seemed buggy from inspection.
>
> arch/riscv/lib/fdt_fixup.c | 11 +++
> 1 file changed, 7 insertions(+)
rch/riscv/include/asm/arch-fu740/reset.h | 13 ++
> arch/riscv/include/asm/arch-fu740/spl.h | 14 ++
> arch/riscv/lib/sifive_clint.c | 1 -
Refer to comments about [PATCH v7 1/8].
https://www.mail-archive.com/u-boot@lists.denx.de/msg405522.html
Hope same code base can be effective re-use in the future.
Reviewed-by: Rick Chen
Hi Green,
> Hi Rick,
>
> Thanks for quick response. See my reply below.
>
> On Mon, May 3, 2021 at 10:34 AM Rick Chen wrote:
> >
> > Hi Green,
> >
> >
> > I did not sign the Reviewed-by for this patch "board: sifive: add
> > HiFive Unmatche
Hi Green,
I did not sign the Reviewed-by for this patch "board: sifive: add
HiFive Unmatched board support" from v1 to v6.
But it just has been tagged in [v7,7/8] board: sifive: add HiFive
Unmatched board support by yourself.
[v6,6/7] board: sifive: add HiFive Unmatched board support
10 --
> 1 file changed, 8 insertions(+), 2 deletions(-)
Reviewed-by: Rick Chen
io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf
>
> Signed-off-by: Green Wan
> Reviewed-by: Sean Anderson
> Reviewed-by: Bin Meng
> ---
> arch/riscv/cpu/fu740/spl.c | 15 +++
> 1 file changed, 15 insertions(+)
Reviewed-by: Rick Chen
is M-mode check can be remove, it is a repeat confirmation in
harts_early_init() of arch/riscv/cpu/fu740/spl.c
Other than that,
Reviewed-by: Rick Chen
> + /*
> +* Configure proprietary settings and customized CRSs of harts
> +*/
> +call_harts_early_init:
> +
Hi Green
> On Thu, Apr 15, 2021 at 1:25 PM Rick Chen wrote:
> >
> > Hi Green,
> >
> > > From: Green Wan [mailto:green@sifive.com]
> > > Sent: Thursday, April 08, 2021 9:40 PM
> > > Cc: bmeng...@gmail.com; Green Wan; Greentime Hu; Rick Jian-Zhi
t
doesn't make sense.
Maybe you can combine with the dts relative files in [PATCH v6 6/7]
into one patch and name as :
riscv: dts: ...
LGTM.
Other than that,
Reviewed-by: Rick Chen
> dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
> dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microc
Hi Green,
> From: Green Wan [mailto:green@sifive.com]
> Sent: Tuesday, April 13, 2021 5:32 PM
> Cc: Green Wan; Sean Anderson; Bin Meng; Rick Jian-Zhi Chen(陳建志); Paul
> Walmsley; Pragnesh Patel; Bin Meng; Simon Glass; Atish Patra; Leo Yu-Chi
> Liang(梁育齊); Brad Kim; open list
> Subject: [RFC
> From: Green Wan [mailto:green@sifive.com]
> Sent: Tuesday, April 13, 2021 5:32 PM
> Cc: Green Wan; Rick Jian-Zhi Chen(陳建志); Paul Walmsley; Pragnesh Patel; Sean
> Anderson; Bin Meng; Simon Glass; Atish Patra; Leo Yu-Chi Liang(梁育齊); Brad
> Kim; open list
> Subject: [RFC PATCH v5 1/2] arch:
Hi Sean,
> On 4/13/21 12:12 AM, Rick Chen wrote:
> > Hi Sean
> >
> >> On 4/12/21 10:39 PM, Rick Chen wrote:
> >>> Hi Green,
> >>>
> >>>> From: Green Wan [mailto:green@sifive.com]
> >>>> Sent: Monday, April 12, 2021
Hi Sean
> On 4/12/21 10:39 PM, Rick Chen wrote:
> > Hi Green,
> >
> >> From: Green Wan [mailto:green@sifive.com]
> >> Sent: Monday, April 12, 2021 10:33 AM
> >> To: Sean Anderson
> >> Cc: Rick Chen; Rick Jian-Zhi Chen(陳建志); Bin Meng; U-Boo
Hi Green,
> From: Green Wan [mailto:green@sifive.com]
> Sent: Tuesday, March 30, 2021 1:27 PM
> Cc: Green Wan; Rick Jian-Zhi Chen(陳建志); Paul Walmsley; Pragnesh Patel; Sean
> Anderson; Bin Meng; Simon Glass; Atish Patra; Leo Yu-Chi Liang(梁育齊); Brad
> Kim; u-boot@lists.denx.de
> Subject: [RFC
Hi Green,
> From: Green Wan [mailto:green@sifive.com]
> Sent: Monday, April 12, 2021 10:33 AM
> To: Sean Anderson
> Cc: Rick Chen; Rick Jian-Zhi Chen(陳建志); Bin Meng; U-Boot Mailing List; Paul
> Walmsley; Pragnesh Patel; Simon Glass; Atish Patra; Leo Yu-Chi Liang(梁育齊);
>
ction should generate a breakpoint exception.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> cmd/riscv/exception.c | 10 ++
> doc/usage/exception.rst | 3 +++
> 2 files changed, 13 insertions(+)
Reviewed-by: Rick Chen
for CPUs which previously only enabled them for the
> > boot hart. I think ax25 is the only CPU which currently does this. Bin,
> > would this be an issue?
No, they are functions shall be called in different stage about lottery.
riscv_hart_early_init() is called before lottery for
e()
> > This is mostly useful in tracing.
> >
> > Signed-off-by: Pragnesh Patel
> > ---
> >
> > Changes in v3:
> > - Add IS_ENABLED(CONFIG_TIMER_EARLY) for timer_early_get_rate()
> > and timer_early_get_count() functions.
>
> Reviewed-by: Rick C
Hi Padmarao
> From: Padmarao Begari [mailto:padmarao.beg...@microchip.com]
> Sent: Tuesday, December 22, 2020 9:12 PM
> To: u-boot@lists.denx.de; bmeng...@gmail.com; Rick Jian-Zhi Chen(陳建志);
> anup.pa...@wdc.com; lukas.a...@aisec.fraunhofer.de; joe.hershber...@ni.com;
> lu...@denx.de;
gnesh Patel
> ---
>
> Changes in v3:
> - Add IS_ENABLED(CONFIG_TIMER_EARLY) for timer_early_get_rate()
> and timer_early_get_count() functions.
Reviewed-by: Rick Chen
Hi Pragnesh
> On Tue, Jan 5, 2021 at 7:12 AM Sean Anderson wrote:
> >
> > On 1/4/21 8:37 PM, Rick Chen wrote:
> > > Hi Pragnesh
> > >
> > >>> From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com]
> > >>> Sent: Tuesday, Decemb
Hi Joe
> From: Padmarao Begari [mailto:padmarao.beg...@microchip.com]
> Sent: Tuesday, December 22, 2020 9:12 PM
> To: u-boot@lists.denx.de; bmeng...@gmail.com; Rick Jian-Zhi Chen(陳建志);
> anup.pa...@wdc.com; lukas.a...@aisec.fraunhofer.de; joe.hershber...@ni.com;
> lu...@denx.de;
; > drivers/timer/andes_plmt_timer.c | 21 -
> > drivers/timer/riscv_timer.c| 21 -
> > drivers/timer/sifive_clint_timer.c | 21 -
> > include/configs/ax25-ae350.h | 5 +
> > include/configs/qemu-riscv.h
s. If the DMA API only uses 32/64-bit
> addresses, dma_addr_t need only be 32/64 bits wide.
>
> Signed-off-by: Padmarao Begari
> Reviewed-by: Anup Patel
> Reviewed-by: Bin Meng
> ---
> arch/riscv/Kconfig | 4
> arch/riscv/include/asm/types.h | 4
> 2 files changed, 8 insertions(+)
>
Reviewed-by: Rick Chen
Rini
> Subject: [PATCH] doc: qemu-riscv: Fix opensbi build instructions
>
> Latest opensbi uses generic platform for Qemu. Update the build
> instructions.
>
> Signed-off-by: Atish Patra
> ---
> doc/board/emulation/qemu-riscv.rst | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rick Chen
-
> drivers/timer/sifive_clint_timer.c | 21 -
> include/configs/ax25-ae350.h | 5 +
> include/configs/qemu-riscv.h | 5 +
> include/configs/sifive-fu540.h | 5 +
> 6 files changed, 75 insertions(+), 3 deletions(-)
Reviewed-by: Rick Chen
will make gd->dm_root = NULL and gd->timer = NULL, so
> timer_get_us() -> get_ticks() -> dm_timer_init() will lead to an
> indefinite recursion.
>
> So select TIMER_EARLY when tracing got enabled.
>
> Signed-off-by: Pragnesh Patel
> ---
>
> Changes in v2:
> - new patch
>
> lib/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Rick Chen
>
> board/sipeed/maix/Kconfig | 16 ++
> configs/sipeed_maix_bitm_defconfig | 11 +
> doc/board/sipeed/maix.rst | 319 -
> include/configs/sipeed-maix.h | 7 +-
> 4 files changed, 301 insertions(+), 52 deletions(-)
Reviewed-by: Rick Chen
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